INTEGRATED CIRCUITS 74F569 4-bit bidirectional binary synchronous counter (3-State) Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) FEATURES 74F569 PIN CONFIGURATION • 4-bit bidirectional counting – binary counter • Synchronous counting and loading • Look ahead carry capability for easy cascading • Preset capability for programmable operation • Master Reset (MR) overrides all other inputs • Synchronous Reset (SR) overrides counting and parallel loading • Clock Carry (CC) output to be used as a clock for flip-flops, U/D 1 20 VCC CP 2 19 TC D0 3 18 CC D1 4 17 OE D2 5 16 Q0 D3 6 15 Q1 CEP 7 14 Q2 MR 8 13 Q3 SR 9 12 CET GND 10 11 PE register and counters • 3-State outputs for bus organized systems DESCRIPTION SF01072 The 74F569 is a fully synchronous Up/Down binary counter. It features preset capabilities for programmable operation, carry look ahead for programmable operation, carry look ahead for easy cascading, and U/D input to control the direction of counting. For maximum flexibility there are both Synchronous and Master Reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by rising edge of the clock. A High signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F569 115MHz 40mA ORDERING INFORMATION ORDER CODE LOGIC SYMBOL DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG. DWG. # 20-pin plastic DIP N74F569N SOT146-1 20-pin plastic SO N74F569D SOT163-1 LOGIC SYMBOL (IEEE/IEC) 3 4 5 CTR DIV 10 6 17 D0 D1 D2 1 D3 11 PE 1 U/D 2 CP 7 CEP CC 18 12 CET TC 19 8 MR 9 SR 17 OE EN10 M1[UP] M2[DOWN] 2 12 7 9 Q0 Q1 Q2 C5/1,4,7,8+/2,4,7,8– Z6 11 Q3 G7 6,7,8,9 G8 1,7(CT=15)G9 5CT=0 18 19 2,7(CT=0)G9 M3[LOAD] M4[COUNT] VCC = Pin 20 GND = Pin 10 8 16 15 14 13 CT=0 SF01056 3 3,5D 10 16 4 15 5 14 6 13 SF01057 1996 Jan 05 2 853–0376 16193 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) 74F569 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 - D3 Parallel data inputs 1.0/1.0 20µA/0.6mA CEP Count Enable parallel input (active Low) 1.0/1.0 20µA/0.6mA CET Count Enable Trickle input (active Low) 1.0/2.0 20µA/1.2mA CP Clock input (active rising edge) 1.0/1.0 20µA/0.6mA PE Parallel Enable input (active Low) 1.0/2.0 20µA/1.2mA U/D Up/Down count control input 1.0/1.0 20µA/0.6mA OE Output Enable input 1.0/1.0 20µA/0.6mA MR Master Reset input (active Low) 1.0/1.0 20µA/0.6mA SR Synchronous Reset (active Low) 1.0/1.0 20µA/0.6mA TC Terminal count output (active Low) 50/33 1.0mA/20mA CC Clocked carry output (active Low) 50/33 1.0mA/20mA Q0 - Q3 Data outputs 150/40 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state. 3.0mA/24mA FUNCTIONAL DESCRIPTION The 74F569 counts in the modulo-16 binary sequence. From state 0 (LLLL) it will increment to 15 in the up mode; in the down mode it will decrement from 15 to 0. The clock inputs of all flip-flops are driven parallel through a clock buffer. All state changes (except due to Master Reset) occur synchronously with the Low-to-High transition of the Clock Pulse (CP) input. To implement synchronous multistage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure 1 shows the connections for a simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry look ahead connections in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from Max to Min in the up mode, or Min to Max in the down mode, to start its final cycle. Since this takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, register or counters. The circuit has five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Six control inputs–Master Reset (MR), Synchronous Reset (SR), Count Enable Trickle (CET), Parallel Enable (PE), Count Enable Parallel (CEP), and the Up/Down (U/D) input – determine the mode of operation, as shown in the Function Table. A Low signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs Low. A Low signal on SR overrides counting and parallel loading and allows the Q output to go Low on the next rising edge of CP. A Low signal on PE overrides counting and allows information on the parallel data (Dn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR, and PE High, CEP and CET permit counting when both are Low. Conversely, a High signal on either CEP and CET inhibits counting. For such applications, the Clocked Carry (CC) output is provided. The CC output is normally High. When CEP, CET, and TC are Low, the CC output will go Low, when the clock next goes Low and will stay Low until the clock goes High again; as shown in the CC Function Table. When the Output Enable (OE) is Low, the parallel data outputs Q0–Q3 are active and follow the flip-flop Q outputs. A High signal on OE forces Q0–Q3 to the High impedance state but does not prevent counting, loading or resetting. The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally High and goes Low provided CET is Low, when the counter reaches zero in the down mode, or reaches maximum 15 in the up mode LOGIC EQUATIONS: Count Enable=CEP×CET×PE Up: TC=Q0×Q1×Q2×Q3×(Up)×CET Down: TC=Q0×Q1×Q2×Q3×(Down)×CET TC will then remain Low until a state change occurs by counting or presetting, or until U/D or CET is changed. 1996 Jan 05 3 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) COUNT CET TC CET TC CET TC CET 74F569 TC CET TC CP CP TO ALL STAGES SF01059 Figure 1. Multistage Counter with Ripple Carry COUNT CET CEP TC CP CET LOW CP CEP TC CEP CEP CET TC CET TC CET TO ALL STAGES SF01061 Figure 2. Multistage Counter with Look-Ahead Carry STATE DIAGRAM CC FUNCTION TABLE INPUTS 0 1 2 3 4 15 5 14 6 13 7 SR PE CEP CET TC* CP CC L X X X X X H X L X X X X H X X H X X X H X X X H X X H X X X X H X H H L L L H 12 11 10 9 8 * H L X COUNT DOWN COUNT UP SF01058 OUTPUT = = = = TC is generated internally High voltage level Low voltage level Don’t care = Low Pulse FUNCTION TABLE INPUTS OPERATING MODE MR SR PE CEP CET U/D CP L X X X X X X Asynchronous reset h l X X X X ↑ Synchronous reset h h l X X X ↑ Parallel load h h h l l h ↑ Count Up (increment) h h h l l l ↑ Count Down (decrement) h H H H X X X h H H X H X X Hold (do nothing) H h L l X ↑ = = = = = = High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition Don’t care Low-to-High clock transition 1996 Jan 05 4 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) 74F569 LOGIC DIAGRAM OE 17 MR 8 D0 3 D Q CP Q RD D1 4 D Q CP Q RD D2 5 D 16 15 14 RD SR 6 D Q2 Q CP Q 9 Q1 Q CP Q D3 Q0 13 Q3 RD PE 11 7 CEP 12 CET CP U/D 2 1 19 TC 18 CC VCC = Pin 20 GND = Pin 10 SF01062 1996 Jan 05 5 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) 74F569 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state IOUT Current a applied lied to output out ut in Low output out ut state Tamb Operating free-air temperature range Tstg Storage temperature –0.5 to +VCC V 40 mA TC, CC Qn 48 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output out ut current TC, CC –1 mA Qn –3 mA IOL Low-level out output ut current TC, CC 20 mA Qn 24 mA Tamb Operating free-air temperature range 70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS S O SYMBOL S CONDITIONS CO O SNO TAG TEST PARAMETER MIN TYP NO TAG MAX UNIT output High-level out ut voltage VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX ±10%VCC 2.4 ±5%VCC 2.7 VOL Low-level out output ut voltage VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX ±10%VCC 0.35 0.50 V ±5%VCC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V VOH Others V 3.3 20 µA –0.6 mA –1.2 mA IIL Low-level in input ut current IOZH Off-state output current, High-level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current, High-level voltage applied VCC = MAX, VO = 0.5V –50 µA IOS Short-circuit output currentNO TAG CET, PE VCC = MAX, MAX VI = 0 0.5V 5V V VCC = MAX –60 ICCH ICC Supply current (total) ICCL VCC = MAX ICCZ –150 mA 38 60 mA 43 62 mA 40 60 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1996 Jan 05 6 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) 74F569 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = 0°C to +70°C VCC = +5.V VCC = +5.V ± 10% CL = 50pF, RL = 500Ω MIN TYP MAX UNIT CL = 50pF, RL = 500Ω MIN MAX Qn Waveform 1 100 115 90 CC, TC Waveform 2 50 65 45 MHz 6.0 7.5 9.5 11.0 3.0 4.0 10.0 12.0 ns ns fMAX Maximum clock frequency tPLH tPHL Propagation delay CP to Qn (PE, High or Low) Waveform 1 3.0 4.0 tPLH tPHL Propagation delay CP to TC Waveform 2 5.5 4.0 10.0 7.5 15.0 11.0 5.5 4.0 16.0 12.0 ns ns tPLH tPHL Propagation delay CET to TC Waveform 3 1.5 2.5 3.0 5.0 6.0 8.0 1.0 2.5 7.0 9.0 ns ns tPLH tPHL Propagation delay U/D to TC Waveform 4 4.0 4.0 7.5 6.5 11.0 11.0 4.0 4.0 12.0 12.0 ns ns tPLH tPHL Propagation delay CP to CC Waveform 2 2.5 2.0 4.5 4.0 7.5 6.6 2.0 2.0 6.0 7.0 ns ns tPLH tPHL Propagation delay CEP, CET to CC Waveform 2 2.0 3.5 4.0 5.5 7.0 9.0 1.5 3.0 7.5 10.0 ns ns tPHL Propagation delay MR to Qn Waveform 5 6.0 8.0 11.0 5.5 12.0 ns tPLH tPHL Propagation delay U/D to CC Waveform 4 4.5 5.0 9.0 11.0 12.0 16.0 4.0 5.0 13.5 17.0 ns ns tPHL Propagation delay MR to TC, CC Waveform 5 8.0 11.0 15.0 7.5 16.0 ns ns tPLH tPHL Propagation delay SR to CC Waveform 3 5.5 7.5 8.0 9.5 11.0 12.0 5.0 7.0 12.0 13.0 ns ns tPLH tPHL Propagation delay PE to CC Waveform 3 3.0 4.0 5.0 6.0 8.0 8.5 2.5 4.0 8.5 9.5 ns ns tPZH tPZL Output Enable time to High or Low level OE to Qn Waveform 10 Waveform 11 2.0 4.5 4.0 6.5 7.0 9.5 2.0 4.0 7.5 10.0 ns ns tPHZ tPLZ Output Disable time to High or Low level OE to Qn Waveform 10 Waveform 11 1.5 1.5 3.5 3.5 6.5 6.0 1.5 1.5 7.5 6.5 ns ns 1996 Jan 05 7 MHz Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) 74F569 AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = 0°C to +70°C VCC = +5.0V VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω MIN ts(H) ts(L) Setup time, High or Low Dn to CP th(H) th(L) TYP MIN UNIT MAX Waveform 6 4.0 4.0 4.5 4.5 ns ns Hold time, High or Low Dn to CP Waveform 6 2.0 2.0 2.5 2.5 ns ns ts(H) ts(L) Setup time, High or Low CEP or CET to CP Waveform 7 5.0 5.0 6.0 6.0 ns ns th(H) th(L) Hold time, High or Low CEP or CET to CP Waveform 7 0 0 0 0 ns ns ts(H) ts(L) Setup time, High or Low PE to CP Waveform 6 8.0 8.0 9.0 9.0 ns ns th(H) th(L) Hold time, High or Low PE to CP Waveform 6 0 0 0 0 ns ns ts(H) ts(L) Setup time, High or Low U/D to CP Waveform 8 10.0 8.0 12.5 8.0 ns ns th(H) th(L) Hold time, High or Low U/D to CP Waveform 8 0 0 0 0 ns ns ts(H) ts(L) Setup time, High or Low SR to CP Waveform 9 8.0 8.0 9.0 9.0 ns ns th(H) th(L) Hold time, High or Low SR to CP Waveform 9 0 0 0 0 ns ns tw(H) tw(L) CP Pulse width, High or Low Waveform 1 7.0 5.0 8.0 6.0 ns ns tw(H) MR Pulse width, Low Waveform 5 4.5 5.0 ns tREC Recovery time, MR to CP Waveform 5 6.0 7.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP VM CP, CEP, CET VM tW(H) VM VM tPLH tW(L) tPLH VM TC VM tPHL VM VM tPHL VM tPHL VM Qn CC tPLH VM VM SF01063 SF01064 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency 1996 Jan 05 Waveform 2. Propagation Delay, CP, CET, and CEP to CC and CP to TC 8 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) 74F569 AC WAVEFORMS (Continued) For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. CET, SR, PE VM VM tPHL TC, CC VM U/D tPLH VM tPHL VM VM tPLH TC, CC VM VM SF01065 SF01066 Waveform 3. Propagation Delays CET to TC and SR or PE to CC Waveform 4. Propagation Delays U/D to TC and CC tW(L) Dn MR tREC th ts VM CP DATA V STABLE M VM PE tPHL VM VM ts(L) VM th = 0 VM ts(H) th = 0 VM Qn VM CP SF01067 VM SF01068 Waveform 5. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time Waveform 6. Parallel Data and Parallel Enable Setup and Hold Times CET VM VM VM VM U/D VM VM VM VM CEP ts(L) CP VM Qn NO CHANGE th(L) ts(H) ts(L) th(H) VM VM CP VM COUNT NO CHANGE Qn th(L) ts(H) VM VM COUNT UP COUNT DOWN SF01070 SF01069 Waveform 7. Count Enable Data Setup and Hold Times SR VM ts(H) VM th(H) VM ts(L) Waveform 8. Up/Down Control Setup and Hold Times OE VM VM VM VM tPHZ VOH -0.3V VM 0V SF01084 SF01071 Waveform 10. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 9. Synchronous Reset Setup and Hold Times 1996 Jan 05 VM tPZH th(L) Qn CP th(H) 9 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) 74F569 AC WAVEFORMS (Continued) For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. OE VM VM tPZL tPLZ Qn VM VOL +0.3V SF01083 Waveform 11. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 1996 Jan 05 10 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) DIP20: plastic dual in-line package; 20 leads (300 mil) 1996 Jan 05 11 74F569 SOT146-1 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1996 Jan 05 12 74F569 SOT163-1 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) NOTES 1996 Jan 05 13 74F569 Philips Semiconductors Product specification 4-bit bidirectional binary synchronous counter (3-State) 74F569 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05139