TJA1021 LIN 2.1/SAE J2602 transceiver Rev. 05 — 22 October 2009 Product data sheet 1. General description The TJA1021 is the interface between the Local Interconnect Network (LIN) master/slave protocol controller and the physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates from 1 kBd up to 20 kBd and is LIN 2.1/SAE J2602 compliant. The TJA1021 is pin-to-pin compatible with the TJA1020 with an improved ElectroStatic Discharge (ESD) specification. The transmit data stream of the protocol controller at the transmit data input (TXD) is converted by the TJA1021 into a bus signal with optimized slew rate and wave shaping to minimize ElectroMagnetic Emission (EME). The LIN bus output pin is pulled HIGH via an internal termination resistor. For a master application, an external resistor in series with a diode should be connected between pin INH or pin VBAT and pin LIN. The receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller. In Sleep mode, the power consumption of the TJA1021 is very low. In failure modes, the power consumption is reduced to a minimum. 2. Features 2.1 General n n n n n n n n n n LIN 2.1/SAE J2602 compliant Baud rate up to 20 kBd Very low ElectroMagnetic Emission (EME) High ElectroMagnetic Immunity (EMI) Passive behavior in unpowered state Input levels compatible with 3.3 V and 5 V devices Integrated termination resistor for LIN slave applications Wake-up source recognition (local or remote) Supports K-line like functions Pin-to-pin compatible with TJA1020 2.2 Low power management n Very low current consumption in Sleep mode with local and remote wake-up 2.3 Protection mechanisms n High ESD robustness: ±6 kV according to IEC 61000-4-2 for pins LIN, VBAT and WAKE_N n Transmit data (TXD) dominant time-out function TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver n Bus terminal and battery pin protected against transients in the automotive environment (ISO 7637) n Bus terminal short-circuit proof to battery and ground n Thermally protected 3. Quick reference data Table 1. Quick reference data VBAT = 5.5 V to 27 V; Tvj = −40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit VBAT supply voltage on pin VBAT with respect to GND −0.3 - +40 V IBAT supply current on pin VBAT Sleep mode; VLIN = VBAT; VWAKE_N = VBAT; VTXD = 0 V; VSLP_N = 0 V 2 7 10 µA Standby mode; bus recessive VINH = VBAT; VLIN = VBAT; VWAKE_N = VBAT; VTXD = 0 V; VSLP_N = 0 V 150 450 1000 µA Standby mode; bus dominant VBAT = 12 V; VINH = 12 V; VLIN = 0 V VWAKE_N = 12 V; VTXD = 0 V; VSLP_N = 0 V 300 800 1200 µA Normal mode; bus recessive VINH = VBAT; VLIN = VBAT; VWAKE_N = VBAT; VTXD = 5 V; VSLP_N = 5 V 300 800 1600 µA Normal mode; bus dominant; VBAT = 12 V; VINH = 12 V; VWAKE_N = 12 V; VTXD = 0 V; VSLP_N = 5 V 1 2 4 mA −40 - +40 V −40 - +150 °C VLIN voltage on pin LIN with respect to GND, VBAT and VWAKE_N [2] virtual junction temperature Tvj [1] All parameters are guaranteed by design over the virtual junction temperature range. Products are 100 % tested at 125 °C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. [2] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tvj = Tamb + P × Rth(vj-a), where Rth(vj-a) is a fixed value. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). 4. Ordering information Table 2. Ordering information Type number[1] Package Name Description Version TJA1021T/10; TJA1021T/20 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 TJA1021TK/20 HVSON8 plastic thermal enhanced very small outline package; 8 leads; body width 3 mm; lead pitch 0.65 mm SOT782-1 [1] TJA1021T/10: for the low slope version that supports baud rates up to 10.4 kBd (SAE J2602); TJA1021T/20 and TJA1021TK/20: for the normal slope version that supports baud rates up to 20 kBd. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 2 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 5. Block diagram VBAT WAKE_N 7 3 WAKE-UP TIMER CONTROL 8 SLP_N 2 SLEEP/ NORMAL TIMER TEMPERATURE PROTECTION 6 TXD 4 INH LIN TXD TIME-OUT TIMER TJA1021 RXD 1 RXD/ INT BUS TIMER FILTER 5 GND 001aae066 Fig 1. Block diagram TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 3 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 6. Pinning information 6.1 Pinning RXD 1 SLP_N 2 WAKE_N 3 TXD 4 8 INH TJA1021T 7 VBAT TJA1021TK 6 LIN 5 GND 015aaa106 Fig 2. Pin configuration diagram 6.2 Pin description Table 3. Pin description Symbol Pin Description RXD 1 receive data output (open-drain); active LOW after a wake-up event SLP_N 2 sleep control input (active LOW); controls inhibit output; resets wake-up source flag on TXD and wake-up request on RXD WAKE_N 3 local wake-up input (active LOW); negative edge triggered TXD 4 transmit data input; active LOW output after a local wake-up event GND 5 ground LIN 6 LIN bus line input/output VBAT 7 battery supply INH 8 battery related inhibit output for controlling an external voltage regulator; active HIGH after a wake-up event 7. Functional description The TJA1021 is the interface between the LIN master/slave protocol controller and the physical bus in a Local Interconnect Network (LIN). The TJA1021 is LIN 2.1/SAE J2602 compliant and provides optimum ElectroMagnetic Compatibility (EMC) performance due to wave shaping of the LIN output. The /20 versions of the TJA1021 are optimized for the maximum specified LIN transmission speed of 20 kBd; the /10 version of the TJA1021 is optimized for the LIN transmission speed of 10.4 kBd as specified by the SAE J2602. 7.1 Operating modes The TJA1021 supports modes for normal operation (Normal mode), power-up (Power-on mode) and very-low-power operation (Sleep mode). An intermediate wake-up mode between Sleep and Normal modes is also supported (Standby mode). Figure 3 shows the state diagram. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 4 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver Power-on INH: high TERM. = 30 kΩ RXD: floating TXD: weak pull-down Transmitter: off t(SLP_N = 1) > tgotonorm Normal INH: high TERM. = 30 kΩ RXD: receive data output TXD: transmit data input Transmitter: on switching on VBAT t(SLP_N = 1) > tgotonorm t(SLP_N = 1) > tgotonorm t(SLP_N = 0) > tgotosleep Standby Sleep INH: high TERM. = 30 kΩ RXD: low TXD: wake source output Transmitter: off INH: floating TERM. = high ohmic RXD: floating TXD: weak pull-down Transmitter: off t(WAKE_N = 0; after 1→0) > tWAKE_N or t(LIN = 0→1; after LIN = 0) > tBUS 001aae073 TERM.: slave termination resistor, connected between pins LIN and VBAT. Fig 3. State diagram Table 4. Operating modes Mode SLP_N TXD (output) RXD INH Transmitter Remarks Sleep mode 0 weak pull-down floating floating off no wake-up request detected Standby[1] mode 0 weak pull-down if remote wake-up; strong pull-down if local wake-up[2] LOW[3] HIGH off wake-up request detected; in this mode the microcontroller can read the wake-up source: remote or local wake-up Normal mode 1 HIGH: recessive state HIGH: recessive state HIGH LOW: dominant state LOW: dominant state Normal mode [2][3][4] weak pull-down off [5] Power-on mode 0 floating HIGH [1] Standby mode is entered automatically upon any local or remote wake-up event during Sleep mode. Pin INH and the 30 kΩ termination resistor at pin LIN are switched on. [2] The internal wake-up source flag (set if a local wake-up did occur and fed to pin TXD) will be reset after a positive edge on pin SLP_N. [3] The wake-up interrupt (on pin RXD) is released after a positive edge on pin SLP_N. [4] Normal mode is entered after a positive edge on SLP_N. As long as TXD is LOW, the transmitter is off. In the event of a short-circuit to ground on pin TXD, the transmitter will be disabled. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 5 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver [5] Power-on mode is entered after switching on VBAT. 7.2 Sleep mode This mode is the most power-saving mode of the TJA1021. Despite its extreme low current consumption, the TJA1021 can still be woken up remotely via pin LIN, or woken up locally via pin WAKE_N, or activated directly via pin SLP_N. Filters at the inputs of the receiver (LIN), of pin WAKE_N and of pin SLP_N prevent unwanted wake-up events due to automotive transients or EMI. All wake-up events have to be maintained for a certain time period (twake(dom)LIN, twake(dom)WAKE_N and tgotonorm). Sleep mode is initiated by a falling edge on pin SLP_N in Normal mode. To enter Sleep mode successfully (INH becomes floating), the sleep command (pin SLP_N = LOW) must be maintained for at least tgotosleep. In Sleep mode the internal slave termination between pins LIN and VBAT is disabled to minimize the power dissipation in the event that pin LIN is short-circuited to ground. Only a weak pull-up between pins LIN and VBAT is present. Sleep mode can be activated independently from the actual level on pin LIN, pin TXD or pin WAKE_N. So it is guaranteed that the lowest power consumption is achievable even in case of a continuous dominant level on pin LIN or a continuous LOW on pin WAKE_N. When VBAT drops below the power-on-reset threshold Vth(POR)L, the TJA1021 enters Sleep mode. 7.3 Standby mode Standby mode is entered automatically whenever a local or remote wake-up occurs while the TJA1021 is in Sleep mode. These wake-up events activate pin INH and enable the slave termination resistor at the pin LIN. As a result of the HIGH condition on pin INH the voltage regulator and the microcontroller can be activated. Standby mode is signalled by a LOW-level on pin RXD which can be used as an interrupt for the microcontroller. In Standby mode (pin SLP_N is still LOW), the condition of pin TXD (weak pull-down or strong pull-down) indicates the wake-up source: weak pull-down for a remote wake-up request and strong pull-down for a local wake-up request. Setting pin SLP_N HIGH during Standby mode results in the following events: • An immediate reset of the wake-up source flag; thus releasing the possible strong pull-down at pin TXD before the actual mode change (after tgotonorm) is performed • A change into Normal mode if the HIGH level on pin SLP_N has been maintained for a certain time period (tgotonorm) • An immediate reset of the wake-up request signal on pin RXD 7.4 Normal mode In Normal mode the TJA1021 is able to transmit and receive data via the LIN bus line. The receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller (see Figure 1): HIGH at a recessive level and LOW at a dominant level on the bus. The receiver has a supply-voltage related threshold with hysteresis and an TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 6 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver integrated filter to suppress bus line noise. The transmit data stream of the protocol controller at the TXD input is converted by the transmitter into a bus signal with optimized slew rate and wave shaping to minimize EME. The LIN bus output pin is pulled HIGH via an internal slave termination resistor. For a master application an external resistor in series with a diode should be connected between pin INH or VBAT on one side and pin LIN on the other side (see Figure 6). When in Sleep, Standby or Power-up mode, the TJA1021 enters Normal mode whenever a HIGH level on pin SLP_N is maintained for a time of at least tgotonorm. The TJA1021 switches to Sleep mode in case of a LOW-level on pin SLP_N, maintained for a time of at least tgotosleep. 7.5 Wake-up When VBAT exceeds the power-on-reset threshold voltage Vth(POR)H, the TJA1021 enters Power-on mode. Though the TJA1021 is powered-up and INH is HIGH, both the transmitter and receiver are still inactive. If SLP_N = 1 for t > tgotonorm, the TJA1021 enters Normal mode. There are three ways to wake-up a TJA1021 which is in Sleep mode: 1. Remote wake-up via a dominant bus state of at least twake(dom)LIN 2. Local wake-up via a negative edge at pin WAKE_N 3. Mode change (pin SLP_N is HIGH) from Sleep mode to Normal mode 7.6 Remote and local wake-up A falling edge at pin LIN followed by a LOW level maintained for a certain time period (twake(dom)LIN) and a rising edge at pin LIN respectively (see Figure 4) results in a remote wake-up. It should be noted that the time period twake(dom)LIN is measured either in Normal mode while TXD is HIGH, or in Sleep mode irrespective of the status of pin TXD. A falling edge at pin WAKE_N followed by a LOW level maintained for a certain time period (twake(dom)WAKE_N) results in a local wake-up. The pin WAKE_N provides an internal pull-up towards pin VBAT. In order to prevent EMI issues, it is recommended to connect an unused pin WAKE_N to pin VBAT. After a local or remote wake-up, pin INH is activated (it goes HIGH) and the internal slave termination resistor is switched on. The wake-up request is indicated by a LOW active wake-up request signal on pin RXD to interrupt the microcontroller. 7.7 Wake-up via mode transition It is also possible to set pin INH HIGH with a mode transition towards Normal mode via pin SLP_N. This is useful for applications with a continuously powered microcontroller. 7.8 Wake-up source recognition The TJA1021 can distinguish between a local wake-up request on pin WAKE_N and a remote wake-up request via a dominant bus state. 'A local wake-up request sets the wake-up source flag. The wake-up source can be read on pin TXD in the Standby mode. If an external pull-up resistor on pin TXD to the power supply voltage of the microcontroller TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 7 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver has been added, a HIGH level indicates a remote wake-up request (weak pull-down at pin TXD) and a LOW level indicates a local wake-up request (strong pull-down at pin TXD; much stronger than the external pull-up resistor). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately after the microcontroller sets pin SLP_N HIGH. 7.9 TXD dominant time-out function A TXD dominant time-out timer circuit prevents the bus line from being driven to a permanent dominant state (blocking all network communication) if pin TXD is forced permanently LOW by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TXD. If the duration of the LOW-level on pin TXD exceeds the internal timer value (tto(dom)TXD), the transmitter is disabled, driving the bus line into a recessive state. The timer is reset by a positive edge on pin TXD. 7.10 Fail-safe features Pin TXD provides a pull-down to GND in order to force a predefined level on input pin TXD in case the pin TXD is unsupplied. Pin SLP_N provides a pull-down to GND in order to force the transceiver into Sleep mode in case the pin SLP_N is unsupplied. Pin RXD is set floating in case of lost power supply on pin VBAT. The current of the transmitter output stage is limited in order to protect the transmitter against short circuit to pins VBAT or GND. A loss of power (pins VBAT and GND) has no impact on the bus line and the microcontroller. There are no reverse currents from the bus. The LIN transceiver can be disconnected from the power supply without influencing the LIN bus. The output driver at pin LIN is protected against overtemperature conditions. If the junction temperature exceeds the shutdown junction temperature Tj(sd), the thermal protection circuit disables the output driver. The driver is enabled again when the junction temperature has dropped below Tj(sd) and a recessive level is present at pin TXD. If VBAT drops below Vth(VBATL)L, a protection circuit disables the output driver. The driver is enabled again when VBAT > Vth(VBATL)H and a recessive level is present at pin TXD. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 8 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver LIN recessive VBAT 0.6VBAT VLIN 0.4VBAT tdom(LIN) LIN dominant ground sleep mode standby mode 001aae071 Fig 4. Remote wake-up behavior TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 9 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND; unless otherwise specified. Positive currents flow into the IC. Symbol Parameter Conditions Min Max Unit VBAT supply voltage on pin VBAT with respect to GND −0.3 +40 V VTXD voltage on pin TXD ITXD no limitation −0.3 +6 V ITXD < 500 µA −0.3 +7 V −0.3 +6 V VRXD voltage on pin RXD IRXD no limitation IRXD < 500 µA −0.3 +7 V VSLP_N voltage on pin SLP_N ISLP_N no limitation −0.3 +6 V ISLP_N < 500 µA −0.3 +7 V with respect to GND, VBAT and VWAKE_N −40 +40 V −0.3 +40 V −15 - mA −0.3 VBAT +0.3 V −50 +15 mA −40 +150 °C −55 +150 °C [2] - - kV on pins WAKE_N, LIN, VBAT and INH [3] −8 +8 kV on pins RXD, SLP_N and TXD [3] −2 +2 kV −750 +750 V −200 +200 V VLIN voltage on pin LIN VWAKE_N voltage on pin WAKE_N IWAKE_N current on pin WAKE_N VINH voltage on pin INH IO(INH) output current on pin INH Tvj virtual junction temperature Tstg storage temperature VESD electrostatic discharge voltage only relevant if VWAKE_N < VGND − 0.3; current will flow into pin GND [1] according to IEC 61000-4-2 human body model charge device model machine model all pins [4] all pins [1] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj = Tamb + P × Rth(j-a), where Rth(j-a) is a fixed value. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). [2] Equivalent to discharging a 150 pF capacitor through a 330 Ω resistor. ESD performance of ±6 kV for pins LIN, VBAT and WAKE_N is verified by an external test house. [3] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor. [4] Equivalent to discharging a 200 pF capacitor through a 10 Ω resistor and a 0.75 µH coil. 9. Thermal characteristics Table 6. Thermal characteristics According to IEC 60747-1. Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient Unit SO8 package; in free air 145 K/W HVSON8 package; in free air 50 K/W TJA1021_5 Product data sheet Typ © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 10 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 10. Static characteristics Table 7. Static characteristics VBAT = 5.5 V to 27 V; Tvj = −40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit supply current on pin VBAT Sleep mode; VLIN = VBAT; VWAKE_N = VBAT; VTXD = 0 V; VSLP_N = 0 V 2 7 10 µA Standby mode; bus recessive; VINH = VBAT; VLIN = VBAT; VWAKE_N = VBAT; VTXD = 0 V; VSLP_N = 0 V 150 450 1000 µA Standby mode; bus dominant; VBAT = 12 V; VINH = 12 V; VLIN = 0 V; VWAKE_N = 12 V; VTXD = 0 V; VSLP_N = 0 V 300 800 1200 µA Normal mode; bus recessive; VINH = VBAT; VLIN = VBAT; VWAKE_N = VBAT; VTXD = 5 V; VSLP_N = 5 V 300 800 1600 µA Normal mode; bus dominant; VBAT = 12 V; VINH = 12 V; VWAKE_N = 12 V; VTXD = 0 V; VSLP_N = 5 V 1 2 4 mA power-on reset 1.6 3.1 3.9 V Supply IBAT Power-on reset Vth(POR)L LOW-level power-on reset threshold voltage Vth(POR)H HIGH-level power-on reset threshold voltage 2.3 3.4 4.3 V Vhys(POR) power-on reset hysteresis voltage 0.05 0.3 1 V Vth(VBATL)L LOW-level VBAT LOW threshold voltage 3.9 4.4 4.7 V Vth(VBATL)H HIGH-level VBAT LOW threshold voltage 4.2 4.7 4.9 V Vhys(VBATL) VBAT LOW hysteresis voltage 0.05 0.3 1 V VIH HIGH-level input voltage 2 - 7 V VIL LOW-level input voltage −0.3 - +0.8 V Vhys hysteresis voltage 50 200 400 mV RPD(TXD) pull-down resistance on VTXD = 5 V pin TXD 140 500 1200 kΩ IIL LOW-level input current VTXD = 0 V −5 - +5 µA IOL LOW-level output current 1.5 - - mA Pin TXD local wake-up request; Standby mode; VWAKE_N = 0 V; VLIN = VBAT; VTXD = 0.4 V TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 11 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver Table 7. Static characteristics …continued VBAT = 5.5 V to 27 V; Tvj = −40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit Pin SLP_N VIH HIGH-level input voltage 2 - 7 V VIL LOW-level input voltage −0.3 - +0.8 V Vhys hysteresis voltage 50 200 400 mV RPD(SLP_N) pull-down resistance on VSLP_N = 5 V pin SLP_N 140 500 1200 kΩ IIL LOW-level input current VSLP_N = 0 V −5 0 +5 µA Pin RXD (open-drain) IOL LOW-level output current Normal mode; VLIN = 0 V; VRXD = 0.4 V 1.5 - - mA ILH HIGH-level leakage current Normal mode; VLIN = VBAT; VRXD = 5 V −5 0 +5 µA Pin WAKE_N VIH HIGH-level input voltage VBAT − 1 - VBAT + 0.3 V VIL LOW-level input voltage −0.3 - VBAT − 3.3 V Ipu(L) LOW-level pull-up current VWAKE_N = 0 V −30 −12 −1 µA ILH HIGH-level leakage current VWAKE_N = 27 V; VBAT = 27 V −5 0 +5 µA Pin INH Rsw(VBAT-INH) switch-on resistance Standby; Normal and Power-on between pins VBAT and modes; IINH = −15 mA; VBAT = 12 V INH - 20 50 Ω ILH HIGH-level leakage current Sleep mode; VINH = 27 V; VBAT = 27 V −5 0 +5 µA IBUS_LIM current limitation for driver dominant state VBAT = 18 V; VLIN = 18 V; VTXD = 0 V 40 - 100 mA Rpu pull-up resistance Sleep mode; VSLP_N = 0 V 50 160 250 kΩ IBUS_PAS_rec receiver recessive input VLIN = 27 V; VBAT = 5.5 V; leakage current VTXD = 5 V - - 1 µA IBUS_PAS_dom receiver dominant input Normal mode; VTXD = 5 V; leakage current VLIN = 0 V; VBAT = 12 V including pull-up resistor −600 - - µA VSerDiode voltage drop at the serial diodes in pull-up path with Rslave; ISerDiode = 10 µA 0.4 - 1.0 V IL(log) loss of ground leakage current VBAT = 27 V; VLIN = 0 V −750 - +10 µA IL(lob) loss of battery leakage current VBAT = 0 V; VLIN = 27 V - - 1 µA Pin LIN TJA1021_5 Product data sheet [2][3] © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 12 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver Table 7. Static characteristics …continued VBAT = 5.5 V to 27 V; Tvj = −40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Parameter Vth(dom)RX Conditions Min Typ Max Unit receiver dominant threshold voltage - - 0.4VBAT V Vth(rec)RX receiver recessive threshold voltage 0.6VBAT - - V Vth(RX)cntr center receiver threshold voltage Vth(RX)AV = (Vth(rec)RX + Vth(dom)RX) / 2 0.475VBAT 0.5VBAT 0.525VBAT V Vth(hys)RX receiver hysteresis threshold voltage Vth(hys)RX = Vth(rec)RX − Vth(dom)RX - - 0.175VBAT V Rslave slave resistance connected between pins LIN and VBAT; VLIN = 0 V; VBAT = 12 V 20 30 47 kΩ CLIN capacitance on pin LIN - - 30 pF Vo(dom) dominant output voltage Normal mode; VTXD = 0 V; VBAT = 7.0 V - - 1.4 V Normal mode; VTXD = 0 V; VBAT = 18 V - - 2.0 V 150 175 200 °C [2][3] Thermal shutdown Tj(sd) [2][3] shutdown junction temperature [1] All parameters are guaranteed by design over the virtual junction temperature range. Products are 100 % tested at 125 °C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. [2] Guaranteed by design. [3] Not tested. 11. Dynamic characteristics Table 8. Dynamic characteristics VBAT = 5.5 V to 18 V; Tvj = −40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; see Figure 5; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max duty cycle 1 Vth(rec)(max) = 0.744 × VBAT; Vth(dom)(max) = 0.581 × VBAT; tbit = 50 µs; VBAT = 7 V to 18 V [2][3][4][7] 0.396 - - Vth(rec)(max) = 0.76 × VBAT; Vth(dom)(max) = 0.593 × VBAT; tbit = 50 µs; VBAT = 5.5 V to 7.0 V [2][3][4][7] 0.396 - - Vth(rec)(min) = 0.422 × VBAT; Vth(dom)(min) = 0.284 × VBAT; tbit = 50 µs; VBAT = 7.6 V to 18 V [2][4][5][7] - - 0.581 Vth(rec)(min) = 0.41 × VBAT; Vth(dom)(min) = 0.275 × VBAT; tbit = 50 µs; VBAT = 6.1 V to 7.6 V [2][4][5][7] - - 0.581 Unit Duty cycles δ1 δ2 duty cycle 2 TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 13 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver Table 8. Dynamic characteristics …continued VBAT = 5.5 V to 18 V; Tvj = −40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; see Figure 5; unless otherwise specified.[1] Symbol δ3 δ4 Parameter Conditions duty cycle 3 duty cycle 4 Min Typ Max Vth(rec)(max) = 0.778 × VBAT; Vth(dom)(max) = 0.616 × VBAT; tbit = 96 µs; VBAT = 7 V to 18 V [3][4][7] 0.417 - - Vth(rec)(max) = 0.797 × VBAT; Vth(dom)(max) = 0.630 × VBAT; tbit = 96 µs; VBAT = 5.5 V to 7 V [3][4][7] 0.417 - - Vth(rec)(min) = 0.389 × VBAT; Vth(dom)(min) = 0.251 × VBAT; tbit = 96 µs; VBAT = 7.6 V to 18 V [4][5][7] - - 0.590 Vth(rec)(min) = 0.378 × VBAT; Vth(dom)(min) = 0.242 × VBAT; tbit = 96 µs; VBAT = 6.1 V to 7.6 V [4][5][7] - - 0.590 Unit Timing characteristics tf fall time [2][4] - - 22.5 µs tr rise time [2][4] - - 22.5 µs ∆t(r-f) difference between rise and fall time [2][4] −5 - +5 µs tPD(TX) transmitter propagation delay - - 6 µs tPD(TX)sym transmitter propagation delay symmetry −2.5 - +2.5 µs tPD(RX) receiver propagation delay [6] - - 6 µs tPD(RX)sym receiver propagation delay symmetry [6] −2 - +2 µs twake(dom)LIN dominant wake-up time on pin LIN Sleep mode 30 80 150 µs twake(dom)WAKE_N dominant wake-up time on pin WAKE_N Sleep mode 7 30 50 µs tgotonorm go to normal time time period for mode change from Sleep, Power-on or Standby mode into Normal mode 2 5 10 µs tinit(norm) normal mode initialization time 5 - 20 µs tgotosleep go to sleep time time period for mode change from Normal slope mode into Sleep mode 2 5 10 µs tto(dom)TXD TXD dominant time-out time VTXD = 0 V 27 55 90 ms VBAT = 7.3 V [2] [1] All parameters are guaranteed by design over the virtual junction temperature range. Products are 100 % tested at 125 °C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. [2] Not applicable for the /10 version of the TJA1021. [3] t bus ( rec ) ( min ) δ1, δ3 = ------------------------------2 × t bit [4] Bus load conditions are: CL = 1 nF and RL = 1 kΩ; CL = 6.8 nF and RL = 660 Ω; CL = 10 nF and RL = 500 Ω. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 14 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver [5] t bus ( rec ) ( max ) δ2, δ4 = ------------------------------2 × t bit [6] Load condition pin RXD: CRXD = 20 pF and RRXD = 2.4 kΩ. [7] For VBAT > 18 V the LIN transmitter might be suppressed. If TXD is HIGH then the LIN transmitter output is recessive. tbit tbit tbit VTXD tbus(dom)(max) tbus(rec)(min) VBAT Vth(rec)(max) Vth(dom)(max) LIN BUS signal Vth(rec)(min) Vth(dom)(min) tbus(dom)(min) receiving node 1 thresholds of receiving node 2 tbus(rec)(max) VRXD tp(rx1)f receiving node 2 thresholds of receiving node 1 tp(rx1)r VRXD tp(rx2)r tp(rx2)f 001aae072 Fig 5. Timing diagram LIN transceiver TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 15 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 12. Application information ECU LIN BUS LINE BATTERY +5 V/ +3.3 V only for master node VBAT INH VDD RX0 MICROTX0 CONTROLLER GND Px.x RXD TXD SLP_N 1 8 7 4 TJA1021 2 5 3 6 1 kΩ WAKE_N LIN (1) 001aae070 (1) Master: C = 1 nF; slave: C = 220 pF. Fig 6. Typical application of the TJA1021 13. Test information VBAT INH WAKE_N 100 nF SLP_N TXD TJA1021 RXD RRXD RL CRXD LIN GND CL 001aae069 Fig 7. Test circuit for AC characteristics Immunity against automotive transients (malfunction and damage) in accordance with LIN EMC Test Specification / Version 1.0; August 1, 2004. The waveforms of the applied transients are according to ISO7637-2: Draft 2002-12, test pulses 1, 2a, 3a and 3b. 13.1 Quality information This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive applications. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 16 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 14. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Package outline SOT96-1 (SO8) TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 17 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm SOT782-1 X B D A A E A1 c detail X terminal 1 index area e1 terminal 1 index area e 1 4 C C A B C v w b y y1 C L K Eh 8 5 Dh 0 1 scale Dimensions Unit(1) mm 2 mm A A1 b max 1.00 0.05 0.35 nom 0.85 0.03 0.30 min 0.80 0.00 0.25 c 0.2 D Dh E Eh e e1 K L 0.35 0.45 3.10 2.45 3.10 1.65 3.00 2.40 3.00 1.60 0.65 1.95 0.30 0.40 0.25 0.35 2.90 2.35 2.90 1.55 v 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 maximum per side are not included. Fig 9. References Outline version IEC JEDEC JEITA SOT782-1 --- MO-229 --- sot782-1_po European projection Issue date 09-08-25 09-08-28 Package outline SOT782-1 (HVSON8) TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 18 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 19 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 10) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 10. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 10. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 20 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 21 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 17. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1021_5 20091022 Product data sheet - TJA1021_4 Modifications: • HVSON package added TJA1021_4 20090119 Product data sheet - TJA1021_3 TJA1021_3 20071008 Product data sheet - TJA1021_2 TJA1021_2 20070903 Preliminary data sheet - TJA1021_1 TJA1021_1 20061016 Objective data sheet - - TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 22 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 23 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TJA1021_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 22 October 2009 24 of 25 TJA1021 NXP Semiconductors LIN 2.1/SAE J2602 transceiver 20. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 13 13.1 14 15 16 16.1 16.2 16.3 16.4 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Low power management . . . . . . . . . . . . . . . . . 1 Protection mechanisms . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 4 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Remote and local wake-up . . . . . . . . . . . . . . . . 7 Wake-up via mode transition . . . . . . . . . . . . . . 7 Wake-up source recognition . . . . . . . . . . . . . . . 8 TXD dominant time-out function . . . . . . . . . . . . 8 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal characteristics. . . . . . . . . . . . . . . . . . 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Quality information . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Handling information. . . . . . . . . . . . . . . . . . . . 19 Soldering of SMD packages . . . . . . . . . . . . . . 19 Introduction to soldering . . . . . . . . . . . . . . . . . 19 Wave and reflow soldering . . . . . . . . . . . . . . . 19 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 October 2009 Document identifier: TJA1021_5