PHILIPS P89V52X2

P89V52X2
8-bit 80C51 low power 8 kB flash microcontroller with 256 B
RAM, 192 B data EEPROM
Rev. 01 — 7 June 2007
Preliminary data sheet
1. General description
The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data RAM, and
192 B of data EEPROM. This device is designed to be a drop in and software compatible
replacement for the P87C52, P87C52X2, P89C52, and P89C52X2 devices.
2. Features
2.1 Principal features
„
„
„
„
„
„
„
0 MHz to 33 MHz operating frequency in 12× mode, 20 MHz in 6× mode
8 kB of on-chip flash user code memory
256 B of RAM
Enhanced UART
Three 16-bit timers/counters
Four 8-bit I/O ports
Supports 12-clock (default) or 6-clock mode selection via software or In-Circuit
Programming (ICP)
„ DIP40, PLCC44, and LQFP44 packages
„ Six interrupt sources with four priority levels
„ Second DPTR register
2.2 Additional features
„
„
„
„
„
„
Low EMI mode (ALE inhibit)
Power-down mode with external interrupt wake-up
Idle mode
Extended temperature range
Three security bits
Programmable clock-out pin
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
3. Ordering information
Table 1.
Ordering information
Type number
Package
Version
Name
Description
P89V52X2FN
DIP40
plastic dual in-line package; 40 leads (600 mil) SOT129-1
P89V52X2FBD
LQFP44
plastic low profile quad flat package; 44 leads; SOT389-1
body 10 × 10 × 1.4 mm
P89V52X2FA
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
4. Block diagram
P89V52X2
8 kB
CODE FLASH
HIGH PERFORMANCE 80C51 CPU
TXD
RXD
UART
internal
bus
256 B
DATA RAM
TIMER 0
TIMER 1
T0
T1
P3[7:0]
PORT 3
TIMER 2
T2
T2EX
P2[7:0]
PORT 2
PORT 1
P1[7:0]
OSCILLATOR
PORT 0
P0[7:0]
CRYSTAL
OR
RESONATOR
X1
X2
002aac565
Fig 1. Block diagram
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
2 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
5. Pinning information
5.1 Pinning
P1.0/T2
1
40 VCC
P1.1/T2EX
2
39 P0.0/AD0
P1.2
3
38 P0.1/AD1
P1.3
4
37 P0.2/AD2
P1.4
5
36 P0.3/AD3
P1.5
6
35 P0.4/AD4
P1.6
7
34 P0.5/AD5
P1.7
8
33 P0.6/AD6
RST
9
32 P0.7/AD7
P3.0/RXD 10
P3.1/TXD 11
P89V52X2
31 EA
30 ALE
P3.2/INT0 12
29 PSEN
P3.3/INT1 13
28 P2.7/A15
P3.4/T0 14
27 P2.6/A14
P3.5/T1 15
26 P2.5/A13
P3.6/WR 16
25 P2.4/A12
P3.7/RD 17
24 P2.3/A11
XTAL2 18
23 P2.2/A10
XTAL1 19
22 P2.1/A9
VSS 20
21 P2.0/A8
002aac564
Fig 2. DIP40 pin configuration
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
3 of 56
P89V52X2
NXP Semiconductors
n.c.
1
40 P0.3/AD3
P1.0/T2
2
41 P0.2/AD2
P1.1/T2EX
3
42 P0.1/AD1
P1.2
4
43 P0.0/AD0
P1.3
5
44 VDD
P1.4
6
80C51 with 256 B RAM, 192 B data EEPROM
P1.5
7
39 P0.4/AD4
P1.6
8
38 P0.5/AD5
P1.7
9
37 P0.6/AD6
RST 10
36 P0.7/AD7
P3.0/RXD 11
35 EA
P89V52X2
n.c. 12
34 n.c.
P2.1/A9 25
P2.2/A10 26
P2.3/A11 27
P2.4/A12 28
35 P0.2/AD2
34 P0.3/AD3
P2.0/A8 24
38 VDD
36 P0.1/AD1
n.c. 23
39 n.c.
37 P0.0/AD0
VSS 22
40 P1.0/T2
XTAL1 21
29 P2.5/A13
41 P1.1/T2EX
30 P2.6/A14
P3.5/T1 17
XTAL2 20
31 P2.7/A15
P3.4/T0 16
42 P1.2
32 PSEN
P3.3/INT1 15
P3.7/RD 19
33 ALE
P3.2/INT0 14
P3.6/WR 18
P3.1/TXD 13
002aac563
43 P1.3
44 P1.4
Fig 3. PLCC44 pin configuration
P1.5
1
33 P0.4/AD4
P1.6
2
32 P0.5/AD5
P1.7
3
31 P0.6/AD6
RST
4
30 P0.7/AD7
P3.0/RXD
5
n.c.
6
P3.1/TXD
7
27 ALE
P3.2/INT0
8
26 PSEN
P3.3/INT1
9
25 P2.7/A15
P3.4/T0 10
24 P2.6/A14
P3.5/T1 11
23 P2.5/A13
29 EA
P2.4/A12 22
P2.3/A11 21
P2.1/A9 19
28 n.c.
P2.2/A10 20
P2.0/A8 18
n.c. 17
VSS 16
XTAL1 15
XTAL2 14
P3.7/RD 13
P3.6/WR 12
P89V52X2
002aac562
Fig 4. LQFP44 pin configuration
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
4 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
DIP40
LQFP44
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
39
38
37
36
35
34
33
32
37
36
35
34
33
32
31
30
43
42
41
40
39
38
37
36
P1.0 to P1.7
P1.0/T2
P1.1/T2EX
1
2
40
41
Description
I/O
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have ‘1’s written to them float, and in this
state can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during
accesses to external code and data memory. In this
application, it uses strong internal pull-ups when
transitioning to ‘1’s. External pull-ups are required as a
general purpose I/O port.
I/O
P0.0 — Port 0 bit 0.
I/O
AD0 — Address/data bit 0.
I/O
P0.1 — Port 0 bit 1.
I/O
AD1 — Address/data bit 1.
I/O
P0.2 — Port 0 bit 2.
I/O
AD2 — Address/data bit 2.
I/O
P0.3 — Port 0 bit 3.
I/O
AD3 — Address/data bit 3.
I/O
P0.4 — Port 0 bit 4.
I/O
AD4 — Address/data bit 4.
I/O
P0.5 — Port 0 bit 5.
I/O
AD5 — Address/data bit 5.
I/O
P0.6 — Port 0 bit 6.
I/O
AD6 — Address/data bit 6.
I/O
P0.7 — Port 0 bit 7.
I/O
AD7 — Address/data bit 7.
I/O with
internal
pull-up
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. The Port 1 pins are pulled high by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 1 pins that are
externally pulled LOW will source current (IIL) because of
the internal pull-ups. P1.5, P1.6, P1.7 have high current
drive of 16 mA.
I/O
P1.0 — Port 1 bit 0.
I
T2 — External count input to Timer/Counter 2 or Clock-out
from Timer/Counter 2
I/O
P1.1 — Port 1 bit 1.
I
T2EX: Timer/Counter 2 capture/reload trigger and
direction control
PLCC44
P0.0 to P0.7
P0.0/AD0
Type
2
3
P1.2
3
42
4
I/O
P1.2 — Port 1 bit 2.
P1.3
4
43
5
I/O
P1.3 — Port 1 bit 3.
P1.4
5
44
6
I/O
P1.4 — Port 1 bit 4.
P1.5
6
1
7
I/O
P1.5 — Port 1 bit 5.
P1.6
7
2
8
I/O
P1.6 — Port 1 bit 6.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
5 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 2.
Pin description …continued
Symbol
P1.7
Pin
DIP40
LQFP44
PLCC44
8
3
9
P2.0 to P2.7
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
21
22
23
24
25
26
27
28
18
19
20
21
22
23
24
25
24
25
26
27
28
29
30
31
P3.0 to P3.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
10
11
12
13
14
5
7
8
9
10
11
13
14
15
16
Type
Description
I/O
P1.7 — Port 1 bit 7.
I/O
with
internal
pull-up
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins are pulled HIGH by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 2 pins that are
externally pulled LOW will source current (IIL) because of
the internal pull-ups. Port 2 sends the high-order address
byte during fetches from external program memory and
during accesses to external Data Memory that use 16-bit
address (MOVX@DPTR). In this application, it uses strong
internal pull-ups when transitioning to ‘1’s.
I/O
P2.0 — Port 2 bit 0.
O
A8 — Address bit 8.
I/O
P2.1 — Port 2 bit 1.
O
A9 — Address bit 9.
I/O
P2.2 — Port 2 bit 2.
O
A10 — Address bit 10.
I/O
P2.3 — Port 2 bit 3.
O
A11 — Address bit 11.
I/O
P2.4 — Port 2 bit 4.
O
A12 — Address bit 12.
I/O
P2.5 — Port 2 bit 5.
O
A13 — Address bit 13.
I/O
P2.6 — Port 2 bit 6.
O
A14 — Address bit 14.
I/O
P2.7 — Port 2 bit 7.
O
A15 — Address bit 15.
I/O
with
internal
pull-up
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins are pulled HIGH by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 3 pins that are
externally pulled LOW will source current (IIL) because of
the internal pull-ups.
I
P3.0 — Port 3 bit 0.
I
RXD — Serial input port.
O
P3.1 — Port 3 bit 1.
O
TXD — Serial output port.
I
P3.2 — Port 3 bit 2.
I
INT0 — External interrupt 0 input.
I
P3.3 — Port 3 bit 3.
I
INT1 — External interrupt 1 input
I/O
P3.4 — Port 3 bit 4.
I
T0 — External count input to Timer/Counter 0.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
6 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 2.
Symbol
Pin description …continued
Pin
DIP40
Type
Description
P3.5 — Port 3 bit 5.
LQFP44
PLCC44
P3.5/T1/CEX4 15
11
17
I/O
I
T1 — External count input to Timer/Counter 1
16
12
18
O
P3.6 — Port 3 bit 6.
O
WR — External data memory write strobe
O
P3.7 — Port 3 bit 7.
P3.6/WR
P3.7/RD
17
13
19
O
RD — External data memory read strobe.
PSEN
29
26
32
I/O
Program Store Enable: PSEN is the read strobe for
external program memory. When the device is executing
from internal program memory, PSEN is inactive (HIGH).
When the device is executing code from external program
memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each
access to external data memory.
RST
9
4
10
I
Reset: While the oscillator is running, a HIGH logic state
on this pin for two machine cycles will reset the device.
EA
31
29
35
I
External Access Enable: EA must be connected to VSS in
order to enable the device to fetch code from the external
program memory. EA must be strapped to VDD for internal
program execution.
ALE
30
27
33
I/O
Address Latch Enable: ALE is the output signal for
latching the low byte of the address during an access to
external memory. Normally the ALE[1] is emitted at a
constant rate of 1⁄6 the crystal frequency[2] and can be
used for external timing and clocking. One ALE pulse is
skipped during each access to external data memory.
However, if AO is set to ‘1’, ALE is disabled.
XTAL1
19
15
21
I
Crystal 1: Input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
XTAL2
18
14
20
O
Crystal 2: Output from the inverting oscillator amplifier.
VDD
40
38
44
I
Power supply
VSS
20
16
22
I
Ground
[1]
ALE loading issue: When ALE pin experiences higher loading (>30 pF) during the reset, the microcontroller may accidentally enter into
modes other than normal working mode. The solution is to add a pull-up resistor of 3 kΩ to 50 kΩ to VDD, e.g., for ALE pin.
[2]
For 6-clock mode, ALE is emitted at 1⁄3 of crystal frequency.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
7 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
6. Functional description
6.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.
– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
8 of 56
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
P89V52X2_1
Preliminary data sheet
Table 3.
Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit address
Bit functions and addresses
MSB
LSB
E7
E6
E5
E4
-
ACC*
Accumulator
E0H
AUXR
Auxiliary function register
8EH
-
-
-
AUXR1
Auxiliary function register 1
A2H
-
-
-
F7
F6
F5
-
-
Bit address
B*
B register
F0H
CKCON
B register
8FH
DPTR
Data Pointer (2 B)
DPH
Data Pointer HIGH
83H
DPL
Data Pointer LOW
82H
Interrupt Enable 0
A8H
Bit address
IP*
Interrupt Priority 0
IPH
Interrupt Priority 0 HIGH
B8H
B7H
Bit address
P0*
Port 0
80H
Bit address
P1*
Port 1
90H
Bit address
P2*
Port 2
A0H
Bit address
E2
E1
E0
-
-
-
AO
GF2
0
-
DPS
F4
F3
F2
F1
F0
-
-
-
-
-
X2
AF
AE
AD
AC
AB
AA
A9
A8
EA
-
ET2
ES
ET1
EX1
ET0
EX0
BF
BE
BD
BC
BB
BA
B9
B8
-
-
PT2
PS
PT1
PX1
PT0
PX0
-
-
PT2H
PS0H
PT1H
PX1H
PT0H
PX0H
87
86
85
84
83
82
81
80
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
97
96
95
94
93
92
91
90
-
-
-
-
-
-
T2EX
T2
A7
A6
A5
A4
A3
A2
A1
A0
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
B7
B6
B5
B4
B3
B2
B1
B0
Port 3
B0H
RD
WR
T1
T0
INT1
INT0
TXD
RXD
PCON
Power Control Register
87H
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
D7
D6
D5
D4
D3
D2
D1
D0
CY
AC
F0
RS1
RS0
OV
-
P
9F
9E
9D
9C
9B
9A
99
98
Bit address
PSW*
Program Status Word
D0H
RCAP2H
Timer2 Capture HIGH
CBH
RCAP2L
Timer2 Capture LOW
CAH
Bit address
P89V52X2
9 of 56
© NXP B.V. 2007. All rights reserved.
P3*
80C51 with 256 B RAM, 192 B data EEPROM
Rev. 01 — 7 June 2007
Bit address
IE*
E3
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR
addr.
SCON*
Serial Port Control
98H
SBUF
Serial Port Data Buffer Register
99H
SADDR
Serial Port Address Register
A9H
SADEN
Serial Port Address Enable
B9H
SP
Stack Pointer
Timer Control Register
Bit functions and addresses
MSB
LSB
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
CF
CE
CD
CC
CB
CA
C9
C8
81H
Bit address
TCON*
88H
Bit address
Timer2 Control Register
C8H
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
T2MOD
Timer2 mode Control
C9H
-
-
-
-
-
-
T2OE
DCEN
TH0
Timer 0 HIGH
8CH
TH1
Timer 1 HIGH
8DH
TH2
Timer 2 HIGH
CDH
TL0
Timer 0 LOW
8AH
TL1
Timer 1 LOW
8BH
TL2
Timer 2 LOW
CCH
TMOD
Timer 0 and 1 mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
Unimplemented bits in SFRs (labeled ‘-’) are ‘X’s (unknown) at all times. Unless otherwise specified, ‘1’s should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.
P89V52X2
10 of 56
© NXP B.V. 2007. All rights reserved.
80C51 with 256 B RAM, 192 B data EEPROM
Rev. 01 — 7 June 2007
T2CON*
[1]
NXP Semiconductors
P89V52X2_1
Preliminary data sheet
Table 3.
Special function registers …continued
* indicates SFRs that are bit addressable.
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
6.2 Memory organization
The various P89V52X2 memory spaces are as follows:
• DATA
128 B of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
• IDATA
Indirect Data. 256 B of internal data memory space (00H:FFH) accessed via indirect
addressing using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area. This area includes the DATA area and the 128 B immediately
above it.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89V52X2 has 8 kB of on-chip Code memory.
6.3 System clock and clock options
6.3.1 Clock input options and recommended capacitor values for the oscillator
Shown in Figure 5 and Figure 6 are the input and output of an internal inverting amplifier
(XTAL1, XTAL2), which can be configured for use as an on-chip oscillator.
When driving the device from an external clock source, XTAL2 should be left
disconnected and XTAL1 should be driven. Power consumption can be further reduced by
programming the EXTCLK bit (UCFG.0).
At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to
interaction between the amplifier and its feedback capacitance. However, the capacitance
will not exceed 15 pF once the external signal meets the VIL and VIH specifications.
Resonator manufacturer, supply voltage, and other factors may cause circuit performance
to differ from one application to another. C1 and C2 should be adjusted appropriately for
each design. Table 4 shows the typical values for C1 and C2 vs. resonator type for various
frequencies
Table 4.
Recommended values for C1 and C2 by crystal type
Resonator
C1 = C2
Quartz
20 pF to 30 pF
Ceramic
40 pF to 50 pF
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
11 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
C2
XTAL2
XTAL1
C1
VSS
002aaa545
Fig 5. Oscillator characteristics (using the on-chip oscillator)
n.c.
XTAL2
external
oscillator
signal
XTAL1
VSS
002aaa546
Fig 6. Oscillator characteristics (external clock drive)
6.3.2 Clock control register (CKCON)
By default, the device runs at twelve clocks per machine cycle. The device may be run in
6 clock per machine cycle mode by programming of either a non-volatile bit (FX2) or an
SFR bit (Table 5 “Clock modes”). If the FX2 non-volatile bit is programmed the device will
run in 6-clock mode and the X2 SFR bit has no effect. If the FX2 bit is erased, then the
clock mode is controlled by the X2 SFR bit.
Table 5.
Clock modes
FX2 clock mode bit (UCFG.1) X2 bit (CLKCON.0)
CPU clock mode
erased
0
12-clock mode (default)
erased
1
6-clock mode
programmed
x
6-clock mode
6.4 ALE control
Table 6.
AUXR - Auxiliary register (address 8EH) bit allocation
Not bit addressable; Reset value 00H
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
-
-
AO
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
12 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 7.
AUXR - Auxiliary register (address 8EH) bit description
Bit
Symbol
Description
7 to 1
-
Reserved for future use. Should be set to ‘0’ by user programs.
0
AO
ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of 1⁄2 the oscillator frequency. In case of AO = 1, ALE is
active only during a MOVX or MOVC.
FFFFH
FFH
80H
7FH
00H
FFH
(INDIRECT
ADDRESSING)
UPPER 128 B
INTERNAL RAM
80H
(INDIRECT
ADDRESSING)
EXTERNAL
DATA
MEMORY
(DIRECT
ADDRESSING)
SPECIAL
FUNCTION
REGISTERS (SFRs)
LOWER 128 B
INTERNAL RAM
(INDIRECT AND
DIRECT
ADDRESSING)
0000H
002aac567
Fig 7. Internal and external data memory structure
6.5 Dual data pointers
The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1
determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is
selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data
pointers can be accomplished by a single INC instruction on AUXR1 (see Figure 8).
AUXR1 / bit0
DPS
DPTR1
DPTR0
DPS = 0 → DPTR0
DPS = 1 → DPTR1
DPL
82H
DPH
83H
external data memory
002aaa518
Fig 8. Dual data pointer organization
Table 8.
AUXR1 - Auxiliary register 1 (address A2H) bit allocation
Not bit addressable; Reset value 00H
Bit
Symbol
7
-
6
-
5
-
4
-
P89V52X2_1
Preliminary data sheet
3
GF2
2
0
1
-
0
DPS
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
13 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 9.
AUXR1 - Auxiliary register 1 (address A2H) bit description
Bit
Symbol
Description
7 to 4
-
Reserved for future use. Should be set to ‘0’ by user programs.
3
GF2
General purpose user-defined flag.
2
0
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
1
-
Reserved for future use. Should be set to ‘0’ by user programs.
0
DPS
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
6.6 Reset
At initial power-up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins high. Powering up the device
without a valid reset could cause the device to start executing instructions from an
indeterminate location. Such undefined states may inadvertently corrupt the code in the
flash. A system reset will not affect the on-chip RAM while the device is running, however,
the contents of the on-chip RAM during power-up are indeterminate.
When power is applied to the device, the RST pin must be held high long enough for the
oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An example of a method to extend the
RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 µF
capacitor and to VSS through an 8.2 kΩ resistor as shown in Figure 9.
During initial power the POF flag in the PCON register is set to indicate an initial power-up
condition. The POF flag will remain active until cleared by software.
Following a reset condition, under normal conditions, the device will start executing code
from address 0000H in the user’s code memory. However if the requirements are met for
ICP entry, the device will enter ICP mode.
VDD
10 µF
VDD
RST
8.2 kΩ
C2
XTAL2
XTAL1
C1
002aaa543
Fig 9. Power-on reset circuit
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
14 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
6.7 Flash memory
6.7.1 Flash organization
The P89V52X2 program memory consists of an 8 kB block of user code. The flash can be
read or written in bytes but may only be erased as an entire block. A chip erase function
will erase the entire user code memory and its associated security bits. This flash memory
can be erased or programmed using a programmer tool that supports ICP.
6.7.2 Features
•
•
•
•
•
Flash internal program memory
Programming and erase over the full operating voltage range.
Programming with industry-standard commercial programmers.
10000 typical erase/program cycles for each byte.
100 year minimum data retention.
6.8 Timers/counters 0 and 1
The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to operate
either as timers or event counters (see Table 10 and Table 11).
In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can
think of it as counting machine cycles. Since a machine cycle consists of six oscillator
periods, the count rate is 1⁄6 of the oscillator frequency.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once every machine cycle.
When the samples show a high in one cycle and a low in the next cycle, the count is
incremented. The new count value appears in the register in the machine cycle following
the one in which the transition was detected. Since it takes two machine cycles (12
oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 1⁄12 of
the oscillator frequency. There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once before it changes, it
should be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’
selection, Timer 0 and Timer 1 have four operating modes from which to select.
The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the Special Function
Register TMOD. These two Timer/Counters have four operating modes, which are
selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both
Timers/Counters. Mode 3 is different. The four operating modes are described in the
following text.
Table 10. TMOD - Timer/Counter mode control register (address 89H) bit allocation
Not bit addressable; Reset value: 0000 0000B; Reset source(s): any source
Bit
Symbol
7
6
5
4
3
2
1
0
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
15 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 11.
TMOD - Timer/Counter mode control register (address 89H) bit description
Bit
Symbol
Description
7
T1GATE
Gating control for Timer 1. When set, Timer/Counter is enabled only
while the INT1 pin is high and the TR1 control pin is set. When
cleared, Timer 1 is enabled when the TR1 control bit is set.
6
T1C/T
Timer or Counter select for Timer 1. Cleared for Timer operation (input
from CCLK). Set for Counter operation (input from T1 input pin).
5
T1M1
Mode select for Timer 1.
4
T1M0
3
T0GATE
Gating control for Timer 0. When set, Timer/Counter is enabled only
while the INT0 pin is high and the TR0 control pin is set. When
cleared, Timer 0 is enabled when the TR0 control bit is set.
2
T0C/T
Timer or Counter select for Timer 0. Cleared for Timer operation (input
from CCLK). Set for Counter operation (input from T0 input pin).
1
T0M1
Mode Select for Timer 0.
0
T0M0
Table 12.
TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating
mode
M1
M0
Operating mode
0
0
0
8048 timer ‘TLx’ serves as 5-bit prescaler
0
1
1
16-bit Timer/Counter ‘THx’ and ‘TLx' are cascaded;
there is no prescaler.
1
0
2
8-bit auto-reload Timer/Counter ‘THx’ holds a value
which is to be reloaded into ‘TLx’ each time it
overflows.
1
1
3
(Timer 0) TL0 is an 8-bit Timer/Counter controlled
by the standard Timer 0 control bits. TH0 is an 8-bit
timer only controlled by Timer 1 control bits.
1
1
3
(Timer 1) Timer/Counter 1 stopped.
Table 13. TCON - Timer/Counter control register (address 88H) bit allocation
Bit addressable; Reset value: 0000 0000B; Reset source(s): any reset
Bit
Symbol
Table 14.
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON - Timer/Counter control register (address 88H) bit description
Bit
Symbol
Description
7
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when the processor vectors to Timer 1 Interrupt
routine, or by software.
6
TR1
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter
1 on/off.
5
TF0
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when the processor vectors to Timer 0 Interrupt
routine, or by software.
4
TR0
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter
0 on/off.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
16 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 14.
TCON - Timer/Counter control register (address 88H) bit description …continued
Bit
Symbol
Description
3
IE1
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/LOW-level is detected. Cleared by hardware when the interrupt
is processed, or by software.
2
IT1
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/LOW-level that triggers external interrupt 1.
1
IE0
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/LOW-level is detected. Cleared by hardware when the interrupt
is processed, or by software.
0
IT0
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/LOW-level that triggers external interrupt 0.
6.8.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a fixed divide-by-32 prescaler. Figure 10 shows Mode 0 operation.
overflow
osc/6
Tn pin
C/T = 0
C/T = 1
control
TLn
(5-bits)
THn
(8-bits)
TFn
interrupt
TRn
TnGate
INTn pin
002aaa519
Fig 10. Timer/Counter 0 or 1 in Mode 0 (13-bit counter)
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the Special Function Register TCON (Figure 8). The GATE bit is in the TMOD
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 10). There are two
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
6.8.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See Figure 11.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
17 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
overflow
C/T = 0
osc/6
Tn pin
C/T = 1
control
TLn
(8-bits)
THn
(8-bits)
TFn
interrupt
TRn
TnGate
INTn pin
002aaa520
Fig 11. Timer/Counter 0 or 1 in Mode 1 (16-bit counter)
6.8.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as
shown in Figure 12. Overflow from TLn not only sets TFn, but also reloads TLn with the
contents of THn, which must be preset by software. The reload leaves THn unchanged.
Mode 2 operation is the same for Timer 0 and Timer 1.
C/T = 0
osc/6
Tn pin
C/T = 1
control
TLn
(8-bits)
overflow
TFn
interrupt
reload
TRn
TnGate
THn
(8-bits)
INTn pin
002aaa521
Fig 12. Timer/Counter 0 or 1 in Mode 2 (8-bit auto-reload)
6.8.4 Mode 3
When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting
TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for
Mode 3 and Timer 0 is shown in Figure 13. TL0 uses the Timer 0 control bits: T0C/T,
T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the
‘Timer 1’ interrupt.
Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in
Mode 3, the P89V52X2 can look like it has an additional Timer.
Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into
and out of its own Mode 3. It can still be used by the serial port as a baud rate generator,
or in any application not requiring an interrupt.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
18 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
C/T = 0
osc/6
T0 pin
control
C/T = 1
TL0
(8-bits)
overflow
TH0
(8-bits)
overflow
TF0
interrupt
TF1
interrupt
TR0
TnGate
INT0 pin
osc/2
control
TR1
002aaa522
Fig 13. Timer/Counter 0 Mode 3 (two 8-bit counters)
6.9 Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event
counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four
operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate
Generator which are selected according to Table 15 using T2CON (Table 16 and
Table 17) and T2MOD (Table 18 and Table 19).
Table 15.
Timer 2 operating mode
RCLK+TCLK
CP/RL2
TR2
T2OE
Mode
0
0
1
0
16-bit auto reload
0
1
1
0
16-bit capture
0
0
1
1
Programmable Clock-Out
1
X
1
0
Baud rate generator
X
X
0
X
off
Table 16. T2CON - Timer/Counter 2 control register (address C8H) bit allocation
Bit addressable; Reset value: 00H
Bit
Symbol
Table 17.
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
T2CON - Timer/Counter 2 control register (address C8H) bit description
Bit
Symbol
Description
7
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by
software. TF2 will not be set when either RCLK or TCLK = 1 or when
Timer 2 is in Clock-out mode.
6
EXF2
Timer 2 external flag is set when Timer 2 is in capture, reload or baud
rate mode, EXEN2 = 1 and a negative transition on T2EX occurs. If
Timer 2 interrupt is enabled EXF2 = 1 causes the CPU to vector to the
Timer 2 interrupt routine. EXF2 must be cleared by software.
5
RCLK
Receive clock flag. When set, causes the UART to use Timer 2
overflow pulses for its receive clock in modes 1 and 3. RCLK = 0
causes Timer 1 overflow to be used for the receive clock.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
19 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 17.
T2CON - Timer/Counter 2 control register (address C8H) bit description …continued
Bit
Symbol
Description
4
TCLK
Transmit clock flag. When set, causes the UART to use Timer 2
overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0
causes Timer 1 overflows to be used for the transmit clock.
3
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to
occur as a result of a negative transition on T2EX if Timer 2 is not
being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
2
TR2
Start/stop control for Timer 2. A logic ‘1’ enables the timer to run.
1
C/T2
Timer or counter select. (Timer 2)
0 = internal timer (fosc/6)
1 = External event counter (falling edge triggered; external clock’s
maximum rate = fosc/12
0
CP/RL2
Capture/Reload flag. When set, captures will occur on negative
transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will
occur either with Timer 2 overflows or negative transitions at T2EX
when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to auto-reload on Timer 2 overflow.
Table 18. T2MOD - Timer 2 mode control register (address C9H) bit allocation
Not bit addressable; Reset value: XX00 0000B
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
-
T2OE
DCEN
Table 19.
T2MOD - Timer 2 mode control register (address C9H) bit description
Bit
Symbol
Description
7 to 2
-
Reserved for future use. Should be set to ‘0’ by user programs.
1
T2OE
Timer 2 Output Enable bit. Used in programmable clock-out mode
only.
0
DCEN
Down Count Enable bit. When set, this allows Timer 2 to be configured
as an up/down-counter.
6.9.1 Capture mode
In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which
upon overflowing sets bit TF2, the Timer 2 overflow bit.
The capture mode is illustrated in Figure 14.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
20 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
÷6
OSC
C/T2 = 0
TL2
(8-bits)
TF2
control
C/T2 = 1
T2 pin
TH2
(8-bits)
TR2
capture
transition
detector
timer 2
interrupt
RCAP2L RCAP2H
T2EX pin
EXF2
control
EXEN2
002aaa523
Fig 14. Timer 2 in Capture mode
This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the
IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added
feature that a 1- to -0 transition at external input T2EX causes the current value in the
Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H,
respectively.
In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like
TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow
interrupt). The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to
determine which event caused the interrupt.
There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs
from T2EX, the counter keeps on counting T2 pin transitions or fosc/6 pulses. Since once
loaded contents of RCAP2L and RCAP2H registers are not protected, once Timer2
interrupt is signalled it has to be serviced before new capture event on T2EX pin occurs.
Otherwise, the next falling edge on T2EX pin will initiate reload of the current value from
TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to
previously reported interrupt.
6.9.2 Auto-reload mode (up or down-counter)
In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (via
C/T2 in T2CON), then programmed to count up or down. The counting direction is
determined by bit DCEN (Down-counter Enable) which is located in the T2MOD register
(see Table 18 and Table 19). When reset is applied, DCEN = 0 and Timer 2 will default to
counting up. If the DCEN bit is set, Timer 2 can count up or down depending on the value
of the T2EX pin.
Figure 15 shows Timer 2 counting up automatically (DCEN = 0).
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
21 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
÷6
OSC
C/T2 = 0
TL2
(8-bits)
TF2
control
C/T2 = 1
T2 pin
TH2
(8-bits)
TR2
reload
transition
detector
timer 2
interrupt
RCAP2L RCAP2H
T2EX pin
EXF2
control
EXEN2
002aaa524
Fig 15. Timer 2 in auto-reload mode (DCEN = 0)
In this mode, there are two options selected by bit EXEN2 in T2CON register. If
EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon
overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in
RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software
means.
Auto reload frequency when Timer 2 is counting up can be determined from this formula:
SupplyFrequency
------------------------------------------------------------------------------( 65536 ∠( RCAP2H, RCAP2L ) )
(1)
Where SupplyFrequency is either fosc (C/T2 = 0) or frequency of signal on T2 pin
(C/T2 = 1).
If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0
transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if
enabled, can be generated when either TF2 or EXF2 is ‘1’.
Microcontroller’s hardware will need three consecutive machine cycles in order to
recognize falling edge on T2EX and set EXF2 = 1: in the first machine cycle pin T2EX has
to be sampled as ‘1’; in the second machine cycle it has to be sampled as ‘0’, and in the
third machine cycle EXF2 will be set to ‘1’.
In Figure 16, DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin
T2EX to control the direction of count. When a logic ‘1’ is applied at pin T2EX Timer 2 will
count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in
RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
22 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
toggle
(down-counting reload value)
÷6
OSC
T2 pin
FFH
FFH
TL2
(8-bits)
TH2
(8-bits)
EXF2
C/T2 = 0
control
C/T2 = 1
underflow
timer 2
interrupt
TF2
overflow
TR2
RCAP2L RCAP2H
count direction
1 = up
0 = down
(up-counting reload value)
T2EX pin
002aaa525
Fig 16. Timer 2 in Auto Reload mode (DCEN = 1)
When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will
underflow when TL2 and TH2 become equal to the value stored in RCAP2L and
RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the
timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if needed.
6.9.3 Programmable clock-out
A 50 % duty cycle clock can be programmed to come out on pin T2 (P1.0). This pin,
besides being a regular I/O pin, has two additional functions. It can be programmed:
1. To input the external clock for Timer/Counter 2, or
2. To output a 50 % duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz
operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be
cleared and bit T2OE in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start
the timer.
The Clock-Out frequency depends on the oscillator frequency and the reload value of
Timer 2 capture registers (RCAP2H, RCAP2L) as shown in Equation 2:
OscillatorFrequency
----------------------------------------------------------------------------------------2 × ( 65536 ∠( RCAP2H, RCAP2L ) )
(2)
Where (RCAP2H, RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer.
In the Clock-Out mode Timer 2 rollovers will not generate an interrupt. This is similar to
when it is used as a baud rate generator.
6.9.4 Baud rate generator mode
Bits TCLK and/or RCLK in T2CON allow the UART transmit and receive baud rates to be
derived from either Timer 1 or Timer 2 (See Section 6.10 for details). When TCLK = 0,
Timer 1 is used as the UART transmit baud rate generator. When TCLK = 1, Timer 2 is
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
23 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
used as the UART transmit baud rate generator. RCLK has the same effect for the UART
receive baud rate. With these two bits, the serial port can have different receive and
transmit baud rates – Timer 1 or Timer 2.
Figure 17 shows Timer 2 in baud rate generator mode:
OSC
÷2
C/T2 = 0
TL2
(8-bits)
TX/RX baud rate
control
C/T2 = 1
T2 pin
TH2
(8-bits)
reload
TR2
transition
detector
RCAP2L RCAP2H
T2EX pin
EXF2
timer 2
interrupt
control
EXEN2
002aaa526
Fig 17. Timer 2 in Baud Rate Generator mode
The baud rate generation mode is like the auto-reload mode, when a rollover in TH2
causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and
RCAP2L, which are preset by software.
The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below:
Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate/16
The timer can be configured for either ‘timer’ or ‘counter’ operation. In many applications,
it is configured for ‘timer' operation (C/T2 = 0). Timer operation is different for Timer 2
when it is being used as a baud rate generator.
Usually, as a timer it would increment every machine cycle (i.e., 1⁄6 the oscillator
frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the
baud rate formula is as follows:
Modes 1 and 3 Baud Rates =
OscillatorFrequency
----------------------------------------------------------------------------------------------( 16 × ( 65536 – ( RCAP2H, RCAP2L ) ) )
(3)
Where: (RCAP2H, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer.
The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK = 1 in
T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an
interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the
baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0
transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will
not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in
use as a baud rate generator, T2EX can be used as an additional external interrupt, if
needed.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
24 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2
and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The
RCAP2 registers may be read, but should not be written to, because a write might overlap
a reload and cause write and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers. Table 20 shows commonly used baud
rates and how they can be obtained from Timer 2.
6.9.5 Summary of baud rate equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2 (P1.0)
the baud rate is:
Baud rate = Timer 2 overflow rate / 16
If Timer 2 is being clocked internally, the baud rate is:
Baud rate = fosc / (16 × (65536 − (RCAP2H, RCAP2L)))
Where fosc = oscillator frequency
To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten
as:
RCAP2H, RCAP2L = 65536 − fosc / (16 × baud rate)
Table 20.
Rate
Timer 2 generated commonly used baud rates
Oscillator frequency
Timer 2
RCAP2H
RCAP2L
750 kBd
12 MHz
FF
FF
19.2 kBd
12 MHz
FF
D9
9.6 kBd
12 MHz
FF
B2
4.8 kBd
12 MHz
FF
64
2.4 kBd
12 MHz
FE
C8
600 Bd
12 MHz
FB
1E
220 Bd
12 MHz
F2
AF
600 Bd
6 MHz
FD
8F
220 Bd
6 MHz
F9
57
6.10 UART
The UART operates in all standard modes. Enhancements over the standard 80C51
UART include Framing Error detection, and automatic address recognition.
6.10.1 Mode 0
Serial data enters and exits through RXD and TXD outputs the shift clock. Only 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 1⁄6 of the CPU clock frequency.
UART configured to operate in this mode outputs serial clock on TXD line no matter
whether it sends or receives data on RXD line.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
25 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
6.10.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1⁄2 overflow rate.
6.10.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the
parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data
bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The
baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock frequency, as determined
by the SMOD1 bit in PCON.
6.10.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3
is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is
variable and is determined by the Timer 1⁄2 overflow rate.
Table 21. SCON - Serial port control register (address 98H) bit allocation
Bit addressable; Reset value: 00H
Bit
Symbol
Table 22.
7
SM0/FE
6
5
4
SM1
SM2
REN
TB8
2
RB8
1
TI
0
RI
SCON - Serial port control register (address 98H) bit description
Bit
Symbol
Description
7
SM0/FE
The usage of this bit is determined by SMOD0 in the PCON register. If
SMOD0 = 0, this bit is SM0, which with SM1, defines the serial port
mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot
be cleared by valid frames but can only be cleared by software. (Note:
It is recommended to set up UART mode bits SM0 and SM1 before
setting SMOD0 to ‘1’.)
6
SM1
With SM0, defines the serial port mode (see Table 23 below).
5
SM2
Enables the multiprocessor communication feature in Modes 2 and 3.
In Mode 2 or 3, if SM2 is set to ‘1’, then RI will not be activated if the
received 9th data bit (RB8) is ‘0’. In Mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not received. In Mode 0, SM2
should be ‘0’.
4
REN
Enables serial reception. Set by software to enable reception. Clear by
software to disable reception.
3
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear
by software as desired.
P89V52X2_1
Preliminary data sheet
3
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
26 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 22.
SCON - Serial port control register (address 98H) bit description …continued
Bit
Symbol
Description
2
RB8
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it
SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is
undefined.
1
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in
Mode 0, or at the stop bit in the other modes, in any serial
transmission. Must be cleared by software.
0
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in
Mode 0, or approximately halfway through the stop bit time in all other
modes. (See SM2 for exceptions). Must be cleared by software.
Table 23.
SCON - Serial port control register (address 98H) SM0/SM1 mode definition
SM0, SM1
UART mode
Baud rate
00
0: shift register
CPU clock/6
01
1: 8-bit UART
variable
10
2: 9-bit UART
CPU clock/32 or CPU clock/16
11
3: 9-bit UART
variable
6.10.5 Framing error
Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0,
SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before
SMOD0 is set to ‘1’.
6.10.6 More about UART mode 1
Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is
sampled at a rate of 16 times whatever baud rate has been established. When a transition
is detected, the divide-by-16 counter is immediately reset to align its rollovers with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th
counter states of each bit time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise
rejection. If the value accepted during the first bit time is not 0, the receive circuits are
reset and the unit goes back to looking for another 1-to-0 transition. This is to provide
rejection of false start bits. If the start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and
(b) Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received frame is irretrievably lost. If both
conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is
activated.
6.10.7 More about UART modes 2 and 3
Reception is performed in the same manner as in mode 1.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
27 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and
(b) Either SM2 = 0, or the received 9th data bit = 1.
If either of these conditions is not met, the received frame is irretrievably lost, and RI is not
set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data
bits go into SBUF.
6.10.8 Multiprocessor communications
UART modes 2 and 3 have a special provision for multiprocessor communications. In
these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is
stored in RB8. The UART can be programmed so that when the stop bit is received, the
serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit
SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:
When the master processor wants to transmit a block of data to one of several slaves, it
first sends out an address byte which identifies the target slave. An address byte differs
from a data byte in a way that the 9th bit is ‘1’ in an address byte and ‘0’ in the data byte.
With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is ‘0’.
However, an address byte having the 9th bit set to ‘1’ will interrupt all slaves, so that each
slave can examine the received byte and see if it is being addressed or not. The
addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that
follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about
their business, ignoring the subsequent data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop
bit, although this is better done with the Framing Error flag. When UART receives data in
mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is
received.
6.10.9 Automatic address recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain
addresses in the serial bit stream by using hardware to make the comparisons. This
feature saves a great deal of software overhead by eliminating the need for the software
to examine every serial address which passes by the serial port. This feature is enabled
for the UART by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode
3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains
either the ‘Given’ address or the ‘Broadcast' address. The 9 bit mode requires that the 9th
information bit is a ‘1’ to indicate that the received information is an address and not data.
Using the Automatic Address Recognition feature allows a master to selectively
communicate with one or more slaves by invoking the Given slave address or addresses.
All of the slaves may be contacted by using the Broadcast address. Two Special Function
Registers are used to define the slave’s address, SADDR, and the address mask,
SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits
are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the
‘Given’ address which the master will use for addressing each of the slaves. Use of the
Given address allows multiple slaves to be recognized while excluding others.
This device uses the methods presented in Figure 18 to determine if a ‘Given’ or
‘Broadcast’ address has been received or not.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
28 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
rx_byte(7)
saddr(7)
saden(7)
.
.
.
rx_byte(0)
saddr(0)
given_address_match
saden(0)
logic used by UART to detect 'given address' in received data
saddr(7)
saden(7)
rx_byte(7)
.
.
.
saddr(0)
saden(0)
broadcast_address_match
rx_byte(0)
logic used by UART to detect 'given address' in received data
002aaa527
Fig 18. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when
multiprocessor communications is enabled
The following examples will help to show the versatility of this scheme.
Example 1, slave 0:
SADDR = 1100 0000
SADEN = 1111 1101
---------------------------------------------------Given = 1100 00X0
(4)
Example 2, slave 1:
SADDR = 1100 0000
SADEN = 1111 1110
---------------------------------------------------Given = 1100 000X
(5)
In the above example SADDR is the same and the SADEN data is used to differentiate
between the two slaves. Slave 0 requires a ‘0’ in bit 0 and it ignores bit 1. Slave 1 requires
a ‘0’ in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a ‘0’ in bit 1. A unique address for slave 1 would be 1100 0001 since a ‘1’
in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address
which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
In a more complex system the following could be used to select slaves 1 and 2 while
excluding slave 0:
Example 1, slave 0:
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
29 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
SADDR = 1100 0000
SADEN = 1111 1001
---------------------------------------------------Given = 1100 0XX0
(6)
Example 2, slave 1:
SADDR = 1110 0000
SADEN = 1111 1010
---------------------------------------------------Given = 1110 0X0X
(7)
Example 2, slave 2:
SADDR = 1100 0000
SADEN = 1111 1100
---------------------------------------------------Given = 1100 00XX
(8)
In the above example the differentiation among the 3 slaves is in the lower 3 address bits.
Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1
requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude
Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and
SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the
don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR
and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well
as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic
Addressing mode and allows the microcontroller to use standard UART drivers which do
not make use of this feature.
6.11 Interrupt priority and polling sequence
The device supports six interrupt sources under a four level priority scheme. Table 24
summarizes the polling sequence of the supported interrupts. (See Figure 19).
Table 24.
Interrupt polling sequence
Description
Interrupt flag
Vector address Interrupt
enable
Interrupt
priority
Service
priority
Wake-up
Power-down
External
Interrupt 0
IE0
0003H
EX0
PX0/H
1 (highest)
yes
T0
TF0
000BH
ET0
PT0/H
2
no
External
Interrupt 1
IE1
0013H
EX1
PX1/H
3
yes
T1
TF1
001BH
ET1
PT1/H
4
no
UART
TI/RI
0023H
ES0
PS0/H
5
no
T2
TF2, EXF2
003BH
ET2
PT2/H
6
no
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
30 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
highest
priority
interrupt
IP/IPH/IPA/IPAH
registers
IE and IEA
registers
0
INT0#
IT0
IE0
1
TF0
interrupt
polling
sequence
0
INT1#
IT1
IE1
1
TF1
RI
TI
TF2
EXF2
lowest
priority
interrupt
global
disable
individual
enables
002aac568
Fig 19. Interrupt structure
Table 25. IE - Interrupt enable register (address A8H) bit allocation
Bit addressable; Reset value: 00H
Bit
Symbol
Table 26.
7
6
5
4
3
2
1
0
EA
-
ET2
ES
ET1
EX1
ET0
EX0
IE - Interrupt enable register (address A8H) bit description
Bit
Symbol
Description
7
EA
Interrupt Enable Bit: EA = 1 interrupt(s) can be serviced, EA = 0
interrupt servicing disabled.
6
-
Reserved
5
ET2
Timer 2 Overflow Interrupt Enable
4
ES
Serial Port Interrupt Enable
3
ET1
Timer 1 Overflow Interrupt Enable.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
31 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 26.
IE - Interrupt enable register (address A8H) bit description …continued
Bit
Symbol
Description
2
EX1
External Interrupt 1 Enable.
1
ET0
Timer 0 Overflow Interrupt Enable.
0
EX0
External Interrupt 0 Enable.
Table 27. IP - Interrupt priority low register (address B8H) bit allocation
Bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
PT2
PS
PT1
PX1
PT0
PX0
Table 28.
IP - Interrupt priority low register (address B8H) bit description
Bit
Symbol
Description
7:6
-
Reserved
5
PT2
Timer 2 Interrupt Priority Low Bit
4
PS
Serial Port Interrupt Priority Low Bit.
3
PT1
Timer 1 Interrupt Priority Low Bit.
2
PX1
External Interrupt 1 Priority Low Bit.
1
PT0
Timer 0 Interrupt Priority Low Bit.
0
PX0
External Interrupt 0 Priority Low Bit.
Table 29. IPH - Interrupt priority high register (address B7H) bit allocation
Not bit addressable; Reset value: 00H
Bit
7
6
Symbol
Table 30.
5
4
3
2
1
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
IPH - Interrupt priority high register (address B7H) bit description
Bit
Symbol
Description
7:6
-
Reserved
5
PT2H
Timer 2 Interrupt Priority High Bit.
4
PSH
Serial Port Interrupt Priority High Bit.
3
PT1H
Timer 1 Interrupt Priority High Bit.
2
PX1H
External Interrupt 1 Priority High Bit.
1
PT0H
Timer 0 Interrupt Priority High Bit.
0
PX0H
External Interrupt 0 Priority High Bit.
6.12 Power-saving modes
The device provides two power saving modes of operation for applications where power
consumption is critical. The two modes are idle and Power-down, see Table 31.
6.12.1 Idle mode
Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the program
counter is stopped. The system clock continues to run and all interrupts and peripherals
remain active. The on-chip RAM and the special function registers hold their data during
this mode.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
32 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
The device exits Idle mode through either a system interrupt or a hardware reset. Exiting
Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle
mode. After exit the Interrupt Service Routine, the interrupted program resumes execution
beginning at the instruction immediately following the instruction which invoked the Idle
mode. A hardware reset starts the device similar to a power-on reset.
6.12.2 Power-down mode
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for level
sensitive interrupts only. SRAM contents are retained during Power-down, the minimum
VDD level is 2.0 V.
The device exits Power-down mode through either an enabled external level sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
Power-down. Holding the external interrupt pin low restarts the oscillator, the signal must
hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon
interrupt signal restored to logic VIH, the interrupt service routine program execution
resumes beginning at the instruction immediately following the instruction which invoked
Power-down mode. A hardware reset starts the device similar to power-on reset.
To exit properly out of Power-down, the reset or external interrupt should not be executed
before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage
long enough at its normal operating level for the oscillator to restart and stabilize (normally
less than 10 ms).
Table 31.
Power-saving modes
Mode
Initiated by
State of device
Exited by
Idle mode
Software
(Set IDL bit in PCON)
MOV PCON, #01H;
CLK is running.
Interrupts, serial port and
timers/counters are active.
Program Counter is stopped.
ALE and PSEN signals at a
HIGH-level during Idle. All
registers remain unchanged.
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits Idle mode,
after the ISR RETI instruction, program
resumes execution beginning at the
instruction following the one that invoked
Idle mode. A hardware reset restarts the
device similar to a power-on reset.
Power-down
mode
Software
(Set PD bit in PCON)
MOV PCON, #02H;
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and PSEN signals at a
LOW-level during power-down.
External Interrupts are only
active for level sensitive
interrupts, if enabled.
Enabled external level sensitive interrupt or
hardware reset. Start of interrupt clears PD
bit and exits Power-down mode, after the
ISR RETI instruction program resumes
execution beginning at the instruction
following the one that invoked Power-down
mode. A hardware reset restarts the device
similar to a power-on reset.
6.13 Data EEPROM
The P89V52X2 contains 192 B of data EEPROM organized into three pages of 64 B each.
This memory can be erased in 64 byte pages (using a Page Erase command) or erased
and written as bytes. The P89V52X2 flash reliably stores memory contents even after
100000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. P89V52X2 uses VDD as the supply voltage to perform the
Program/Erase algorithms.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
33 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
The data EEPROM must be mapped into the code memory address space in order to
read, erase, or program the data EEPROM. The memory is read using the MOVC
instruction.
6.13.1 Features
• ICP with industry-standard commercial programmers
• IAP-Lite allows individual and multiple bytes of data EEPROM to be programmed
under control of the end application.
•
•
•
•
•
•
Programming and erase over the full operating voltage range
Programming/Erase using ICP or IAP-Lite
Program or erases requires 2 ms, 4 ms, or 6 ms, depending on the operation
Programmable security for the data in each page
> 100000 typical erase/program cycles for each byte
Data EEPROM mapped into code space for quick MOVC reading
6.13.2 Register interface
Erasing, programming, and mapping operations are performed in the application under
the control of the microcontroller’s firmware using four SFRs and an internal 64-byte ‘page
register’. These SFRs are:
• FMCON (Flash Control Register). When read, this is the status register. When written,
this is a command register. Note that the status bits are cleared to logic 0s when the
command is written.
• FMADRL, FMADRH (Flash memory address low, Flash memory address high). Used
to specify the byte address within the page register or specify the page within user
code memory (for programming, erase, and reading the data EEPROM is mapped
into the user address space (see Table 32).
• FMDATA (Flash Data Register). Accepts data to be loaded into the page register.
Data is read by mapping the data EEPROM into the code memory space and using the
MOVC instruction.
6.13.3 Mapping the data EEPROM into code space
In order to read, erase, or program the data EEPROM must be mapped into the code
memory address space. This is accomplished by writing the MAP command (09H) to
FMCON. The data EEPROM may be unmapped by writing the UNMAP command (0AH)
to FMCON. The mapping of the data EEPROM pages into code memory space is shown
in Table 32.
Table 32.
Data EEPROM page addresses
Data EEPROM page
Start address End address
0
FF00H
FF3FH
1
FF40H
FF7FH
2
FF80H
FFBFH
6.13.4 Reading the data EEPROM
Reading the data EEPROM can be achieved by performing the following sequence:
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
34 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
• Map the data EEPROM into code memory space if not already mapped.
• Write the data EEPROM byte address into the DPTR.
• Use the MOVC instruction to read the data EEPROM.
6.13.5 Erasing a complete page (64 B)
A complete page can be erased by performing the following sequence:
• Map the data EEPROM into code memory space if not already mapped.
• Write the lower 8-bits of the data EEPROM page’s start address into FMADRL.
• Write the ERS_DP command (33H) to FMCON.
Once the ERS_DP command is written to FMCON, code execution will stall until the
operation is completed, approximately 6 ms.
6.13.6 Data EEPROM programming and erasing using the page register
In addition to page erase, a 64 B page register is included which allows from 1 B to 64 B
of a given page to be programmed or erase/programmed at the same time, substantially
reducing overall programming time. Two programming operations are provided:
• Program only operation. This operation used the PROG (48H) command and
programs the contents of the page register into the data EEPROM page. This
operation requires that the bytes being programmed have been previously erased.
This operation requires approximately 2 ms to complete.
• Erase and Program operation. This operation uses the EP (68H) command to both
erase and program the bytes previously loaded into the page register. This command
is often useful to erase and reprogram a single byte of data. This operation requires
approximately 4 ms to complete.
The page register consists of 64 B and an update flag for each byte. When a LOAD
command is issued to FMCON the page register contents and all of the update flags will
be cleared. When FMDATA is written, the value written to FMDATA will be stored in the
page register at the location specified by the lower 6 bits of FMADRL. In addition, the
update flag for that location will be set. FMADRL will auto-increment to the next location.
Auto-increment after writing to the last byte in the page register will ‘wrap-around’ to the
first byte in the page register, but will not affect FMADRL[7:6]. Bytes loaded into the page
register do not have to be continuous. Any byte location can be loaded into the page
register by changing the contents of FMADRL prior to writing to FMDATA. However, each
location in the page register can only be written once following each LOAD command.
Attempts to write to a page register location more than once should be avoided.
FMADRH and FMADRL[7:6] are used to specify a page in the code memory space. When
the PROG command is written to FMCON, the locations within the data EEPROM page
that correspond to updated locations in the page register will have their contents
programmed with the contents of their corresponding locations in the page register. Only
the bytes that were loaded into the page register will be programmed in the data EEPROM
array. Other bytes within the data EEPROM array will not be affected. The EP command
works similarly except that If the EP command is written, the corresponding bytes in the
data EEPROM will be erased prior to being programmed. This is often useful for erasing
and programming a small number of bytes or even a single byte.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
35 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Writing either the PROG or EP command to FMCON will start the program or
erase-program process and place the CPU in a program-idle state. The CPU will remain
in this idle state until the program or erase-program cycle is completed. Interrupts will
NOT be serviced until the cycle is completed.
Erase-program or programming of a single byte (or multiple bytes) in the data EEPROM
array is accomplished using the following steps:
• Write the LOAD command (00H) to FMCON. The LOAD command will clear all
locations in the page register and their corresponding update flags.
• Write the address within the page register to FMADRL. Since the loading the page
register uses FMADRL[5:0], and since the erase-program or program command uses
FMADRH and FMADRL[7:6], the user can write the byte location within the page
register (FMADRL[5:0]) and the code memory page address (FMADRH and
FMADRL[7:6]) at this time.
• Write the data to be programmed to FMDATA. This will increment FMADRL pointing to
the next byte in the page register.
• Write the address of the next byte to be programmed to FMADRL, if desired. (This is
not needed for contiguous bytes since FMADRL is auto-incremented). All bytes to be
programmed must be within the same page.
• Write the data for the next byte to be programmed to FMDATA.
• Repeat writing of FMADRL and/or FMDATA until all desired bytes have been loaded
into the page register.
• Write the page address mapped into user code memory to FMADRH and
FMADRL[7:6], if not previously included when writing the page register address to
FMADRL[5:0].
• Write the EP (68H) or PROG (48H) command to FMCON, starting the erase-program
or program cycle.
• Read FMCON to check status. If aborted, repeat starting with the LOAD command.
Table 33.
Bit
Flash Memory Control register (FMCON - address E4H) bit allocation
7
6
5
4
3
2
1
0
Symbol (R) BUSY
WE
-
DAP
-
-
SV
ERR
Symbol (W) FMCMD.7
FMCMD.6
FMCMD.5
FMCMD.4
FMCMD.3
FMCMD.2
FMCMD.1
FMCMD.0
Reset
0
0
0
0
0
0
0
0
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
36 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 34.
Flash Memory Control register (FMCON - address E4H) bit description
Bit
Symbol
Access
Description
0
ERR
R
Set when either of the following conditions occur:
•
•
•
1
3
4
5
6
7
Attempt made to access data EEPROM while Data Access Protect (DAP) is set.
An error occurs in the device’s internal high voltage circuits.
FMCMD.0
W
Command byte bit 0.
SV
R
Security violation. Set when an attempt is made to program, erase, or CRC a secured page.
The specific cause of the security violation depends on the operation:
•
•
•
•
2
Device was reset before the operation was completed.
PROG or EP: CSEC.0 = 1 or DPxSEC.1 = 1 for the page addressed by FMADRH/L.
ERS_G: Any DPxSEC.0 = 1.
ERS_DP: DPxSEC.2 = 1 for addressed page while in execution mode.
CRC_DP: DPxCSEC.0 = 1 and DPxSEC.1 = 0
FMCMD.1
W
Command byte bit 1
-
R
Reserved
FMCMD.2
W
Command byte bit 2.
-
R
Reserved
FMCMD.3
W
Command byte bit 3.
DAP
R
Data Access Protect. When set, access to the data EEPROM is unmapped and thus
prohibited. Set by the MAP command. Cleared by the UNMAP command.
FMCMD.4
W
Command byte bit 4.
-
R
Reserved
FMCMD.5
W
Command byte bit 5.
WE
R
When set, indicates that data EEPROM writes during program execution are enabled.
FMCMD.6
W
Command byte bit 6.
BUSY
R
Indicates that a program, erase, CRC calculation or similar operation is in progress. Note that
this bit is usable only in ICP mode since the CPU is stalled whenever this bit is set in execution
mode.
FMCMD.7
W
Command byte bit 7.
An assembly language routine to load the page register and perform an erase/program
operation is shown below. This code assumes the data EEPROM has been mapped into
user code space.
;**************************************************
;*
pgm user code
*
;**************************************************
;*
*
;* Inputs:
;* R3 = number of bytes to program (byte)
*
;* R4 = page address MSB(byte)
*
;* R5 = page address LSB(byte)
*
;* R7 = pointer to data buffer in RAM(byte)
*
;* Outputs:
;* R7 = status (byte)
*
;* C = clear on no error, set on error
*
P89V52X2_1
Preliminary data sheet
*
*
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
37 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
;**************************************************
LOAD
EP
EQU
EQU
00H
68H
PGM_USER:
MOV
MOV
MOV
MOV
MOV
LOAD_PAGE:
MOV
INC
DJNZ
MOV
FMCON,#LOAD
FMADRH,R4
FMADRL,R5
A,R7
R0,A
;load command, clears page register
;get high address
;get low address
;
;get pointer into R0
FMDAT,@R0
R0
R3,LOAD_PAGE
FMCON,#EP
;write data to page register
;point to next byte
;do until count is zero
;else erase & program the page
MOV
MOV
ANL
JNZ
CLR
RET
R7,FMCON
A,R7
A,#0FH
BAD
C
;copy status for return
;read status
;save only four lower bits
;
;clear error flag if good
;and return
SETB
RET
C
;set error flag
;and return
BAD:
A C-language routine to load the page register and perform an erase/program operation is
shown below. This code assumes the data EEPROM has been mapped into user code
space.
#include <REGV52.H>
unsigned char idata dbytes[64]; // data buffer
unsigned char Fm_stat; // status result
bit PGM_USER (unsigned char, unsigned char);
bit prog_fail;
void main ()
{
prog_fail=PGM_USER(0x1F,0xC0);
}
bit PGM_USER (unsigned char page_hi, unsigned char page_lo)
{
#define LOAD 0x00 // clear page register, enable loading
#define EP 0x68 // erase & program page
unsigned char i; // loop count
FMCON = LOAD; //load command, clears page reg
FMADRH = page_hi; //
FMADRL = page_lo; //write my page address to addr regs
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
38 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
for (i=0;i<64;i=i+1)
{
FMDATA = dbytes[i];
}
FMCON = EP; //erase & prog page command
Fm_stat = FMCON; //read the result status
if ((Fm_stat & 0x0F)!=0) prog_fail=1; else prog_fail=0;
return(prog_fail);
}
6.13.7 Data EEPROM write enable
The data EEPROM has a Write Enable mechanism to help prevent against inadvertent
writes. If the WE bit (FMCON.6) is set writes to the data EEPROM are enabled. When
cleared, writes are disabled. This bit only affects execution mode. The WE bit is set when:
• The disable write enable bit, DISWE (UCFG.2) = 1
• In ICP mode
• The SET_WE (08H) command is written to FMCON followed by the key value (96H)
being written to FMDATA
The WE bit is cleared following any reset. The WE bit may also be cleared by writing the
CLR_WE (0BH) command to FMCON.
6.13.8 Data EEPROM security bits
The data EEPROM security bits protects each data EEPROM page. The data EEPROM
page security bits and their effects are shown in Table 35.
Table 35.
DPxSEC - Data page X security register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
XERSx
PWRx
MOVCx
Table 36.
DPxSEC - Data page X security register bit description
Bit
Symbol
Description
7 to 3
-
Reserved
2
XERSx
Execution Erase Protect x. When programmed = 1, cannot be erased
with ERS_DP command in execution mode. ERS_DP can be used in
ICP mode.
1
PWRx
Page Write Protect x. When programmed = 1, data EEPROM cannot
be erased or programmed using PROG or EP commands.
0
MOVCx
When programmed = 1, prevents instructions fetched from off-chip
from reading the contents of the data EEPROM and returns FFH.
CRC_DP are disabled if the corresponding Page Write Protect is
disabled.
6.13.9 Summary of data EEPROM commands
is a summary of the FMCON commands related to the data EEPROM.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
39 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 37.
Summary of data EEPROM commands
Mnemonic
Value (hex)
Description
CLR_WE
0B
Clear the WE bit
CRC_DP
1D
Calculate CRC on selected data EEPROM page
EP
68
Erase and Program data EEPROM page
ERS_DP
33
Erase data EEPROM page
LOAD
00
Reset and clear page register
MAP
09
Map data EEPROM into upper end of user code space
PROG
48
Program data EEPROM page
SET_WE
08
Set the WE bit if followed by writing key value to FMDATA
UNMAP
0A
Unmap data EEPROM from user code space
6.14 User configuration bytes
This device contains some non-volatile bytes which allow the user to configure the device.
These bytes are programmed or read using the configuration read or write command
(CONF) with a programmer that supports ICP. The user configuration bytes, their CONF
address are shown in Table 38.
Table 38.
User configuration bytes
Configuration byte
CONF
address
Function
UCFG
00H
6x/12x selection, ext clk select, disable WE
CSEC
01H
Code security
DP0SEC
02H
Data EEPROM, page 0, security
DP1SEC
03H
Data EEPROM, page 1, security
DP2SEC
04H
Data EEPROM, page 2, security
MFG_ID
10H
Manufacturer signature byte
DEVIC_ID
11H
Device id signature byte
DERIV_ID
12H
Derivative id signature byte
6.15 UCFG
The user configuration bits in the UCFG register allow the user to configure some of the
operating characteristics of the device and are shown in Table 39.
Table 39.
UCFG - User configuration register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
ENW
FX2
EXTCLK
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
40 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 40.
UCFG - User configuration register bit description
Bit
Symbol
Description
7 to 3
-
Reserved
2
ENW
Enable Write. When programmed = 1, forces the WE bit to be set.
1
FX2
Force X2. When programmed = 1, the device is in 6-clock mode.
When erased = 0, the mode depends on the state of the X2 bit in
CKCON.
0
EXTCLK
External Clock. When programmed = 1, disables the XTAL block when
using an external digital clock source.
6.16 Code security (CSEC) bits
The code security bits protects against software piracy and prevents the contents of the
flash from being read by unauthorized parties. The code security bits and their effects are
shown in Table 41.
Table 41.
CSEC - Code security register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
-
INTEXEC
PROT
Table 42.
CSEC - Code security register bit description
Bit
Symbol
Description
7 to 2
-
Reserved
1
INTEXEC
Internal execution only. When programmed, if the internal address
space is exceeded, the address will rollover into internal space (upper
address bits are ignored) for MOVC and instruction fetches. MOVC
will access the data EEPROM when the address >= FF00H.
0
PROT
Protect. When programmed, prohibits further erasing or programming
of code memory. MOVC instructions executed from external
code memory are disabled from fetching code bytes from
internal code memory.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
41 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
7. Limiting values
Table 43. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS
unless otherwise noted.
Symbol
Parameter
Tamb(bias)
Conditions
Min
Max
Unit
bias ambient temperature
−55
+125
°C
Tstg
storage temperature
−65
+150
°C
Vn
voltage on any other pin
−0.5
VDD + 0.5
V
IOL(I/O)
LOW-level output current per
input/output pin
-
15
mA
Ptot(pack)
total power dissipation (per package)
-
1.5
W
except VSS, with respect to
VDD
based on package heat
transfer, not device power
consumption
8. Static characteristics
Table 44. Static characteristics
Ta = −40 °C to +85 °C; VDD = 2.7 V to 5.5 V; VSS = 0 V
Symbol
Parameter
Conditions
Min
Max
Unit
nendu(fl)
endurance of flash memory
JEDEC Standard A117
[1]
10000
cycles
tret(fl)
flash memory retention time
JEDEC Standard A103
[1]
100
years
Ilatch
I/O latch-up current
JEDEC Standard 78
[1]
100 + IDD
mA
Vth(HL)
HIGH-LOW threshold voltage
−0.5
0.2VDD − 0.1
V
Vth(LH)
LOW-HIGH threshold voltage except XTAL1, RST
0.2VDD + 0.9
VDD + 0.5
V
VIH
HIGH-level input voltage
XTAL1, RST
0.7VDD
6.0
V
VOL
LOW-level output voltage
VDD = 4.5 V
-
0.4
V
VDD − 0.7
-
V
VDD − 0.7
-
V
VDD − 0.7
-
V
−1
−50
µA
[2][3][4]
IOL = 3.2 mA
VOH
HIGH-level output voltage
VDD = 2.7 V, ports 1, 2, 3
[5]
IOH = −20 µA
VDD = 4.5 V, ports 1, 2, 3
[5]
IOH = −30 µA
VDD = 4.5 V, Port 0 in External
Bus mode, ALE, PSEN
IOH = −3.2 mA
IIL
LOW-level input current
VI = 0.4 V, ports 1, 2, 3
-
−650
µA
-
±10
µA
40
225
kΩ
-
15
pF
fosc = 12 MHz
-
3
mA
fosc = 33 MHz
-
7
mA
ITHL
HIGH-LOW transition current VI = 2 V, ports 1, 2, 3
ILI
input leakage current
0.45 V < VI < VDD − 0.3 V,
port 0
Rpd
pull-down resistance
on pin RST
Ciss
input capacitance
@ 1 MHz, Ta = 25 °C,
VI = 0 V
IDD(oper)
operating supply current
P89V52X2_1
Preliminary data sheet
[6]
[7]
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
42 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 44. Static characteristics …continued
Ta = −40 °C to +85 °C; VDD = 2.7 V to 5.5 V; VSS = 0 V
Symbol
Parameter
Conditions
Min
Max
Unit
IDD(idle)
Idle mode supply current
fosc = 12 MHz
-
1.7
mA
fosc = 33 MHz
-
3
mA
IDD(pd)
Power-down mode supply
current
minimum VDD = 2 V
-
15
µA
[1]
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
[2]
Under steady state (non-transient) conditions, IOL must be externally limited as follows:
a) Maximum IOL per 8-bit port: 26 mA
b) Maximum IOL total for all outputs: 71 mA
c) If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
[3]
Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports 1 and 3. The noise due
to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to
qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input.
[4]
Load capacitance for Port 0, ALE and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
[5]
Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VDD − 0.7 specification when
the address bits are stabilizing.
[6]
Pins of Ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VI is approximately 2 V.
[7]
Pin capacitance is characterized but not tested. EA = 25 pF (max).
002aaa813
50
(1)
IDD
(mA)
40
(2)
30
20
(3)
10
(4)
0
0
10
20
30
40
internal clock frequency (MHz)
(1) Maximum active IDD
(2) Maximum idle IDD
(3) Typical active IDD
(4) Typical idle IDD
Fig 20. IDD vs. frequency
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
43 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
9. Dynamic characteristics
Table 45. Dynamic characteristics
Over operating conditions: load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF
Ta = −40 °C to +85 °C; VDD = 2.7 V to 5.5 V; VSS = 0 V[1]
Symbol
Parameter
Conditions
Min
Max
Unit
fosc
oscillator frequency
12-clock mode
0
40
MHz
6-clock mode
0
20
MHz
ICP
0.25
40
MHz
2Tcy(clk) − 15
-
ns
tLHLL
ALE pulse width
tAVLL
address valid to ALE LOW time
Tcy(clk) − 15
-
ns
tLLAX
address hold after ALE LOW time
Tcy(clk) − 15
-
ns
tLLIV
ALE LOW to valid instruction in time
-
4Tcy(clk) − 45
ns
tLLPL
ALE LOW to PSEN LOW time
Tcy(clk) − 15
-
ns
tPLPH
PSEN pulse width
3Tcy(clk) − 15
-
ns
tPLIV
PSEN LOW to valid instruction in time
-
3Tcy(clk) − 50
ns
tPXIX
input instruction hold after PSEN time
0
-
ns
tPXIZ
input instruction float after PSEN time
-
Tcy(clk) − 15
ns
tPXAV
PSEN to address valid time
Tcy(clk) − 8
-
ns
tAVIV
address to valid instruction in time
-
5Tcy(clk) − 60
ns
tPLAZ
PSEN LOW to address float time
-
10
ns
tRLRH
RD LOW pulse width
6Tcy(clk) − 30
-
ns
tWLWH
WR LOW pulse width
6Tcy(clk) − 30
-
ns
tRLDV
RD LOW to valid data in time
-
5Tcy(clk) − 50
ns
tRHDX
data hold after RD time
0
-
ns
tRHDZ
data float after RD time
-
2Tcy(clk) − 12
ns
tLLDV
ALE LOW to valid data in time
-
8Tcy(clk) − 50
ns
tAVDV
address to valid data in time
-
9Tcy(clk) − 75
ns
tLLWL
ALE LOW to RD or WR LOW time
3Tcy(clk) − 15
3Tcy(clk) + 15
ns
tAVWL
address to RD or WR LOW time
4Tcy(clk) − 30
-
ns
tWHQX
data hold after WR time
Tcy(clk) − 20
-
ns
tQVWH
data output valid to WR HIGH time
7Tcy(clk) − 50
-
ns
tRLAZ
RD LOW to address float time
-
0
ns
tWHLH
RD or WR HIGH to ALE HIGH time
Tcy(clk) − 15
Tcy(clk) + 15
ns
[1]
Tcy(clk) = 1/fosc.
[2]
Calculated values are for 6-clock mode only.
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
44 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
9.1 Explanation of symbols
Each timing symbol has 5 characters. The first character is always a ‘t’ (stands for time).
The other characters, depending on their positions, stand for the name of a signal or the
logical status of that signal. The following is a list of all the characters and what they stand
for.
A — Address
C — Clock
D — Input data
H — Logic level HIGH
I — Instruction (program memory contents)
L — Logic level LOW or ALE
P — PSEN
Q — Output data
R — RD signal
T — Time
V — Valid
W — WR signal
X — No longer a valid logic level
Z — High impedance (Float)
Example:
tAVLL = Address valid to ALE LOW time
tLLPL = ALE LOW to PSEN LOW time
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tLLPL
tPLIV
PSEN
tPXAV
tPLAZ
tLLAX
port 0
tPXIZ
tPXIX
A0 to A7
INSTR IN
A0 to A7
tAVIV
port 2
A8 to A15
A8 to A15
002aaa548
Fig 21. External program memory read cycle
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
45 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
ALE
tWHLH
PSEN
tLLDV
tLLWL
RD
tAVLL
tRLRH
tLLAX
tRHDZ
tRLAZ
tRHDX
tRLDV
A0 to A7
from RI to DPL
port 0
DATA IN
A0 to A7 from PCL
INSTR IN
tAVWL
tAVDV
P2[0] to P2[7] or A8 to A15 from DPF
port 2
A0 to A15 from PCH
002aaa549
Fig 22. External data memory read cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tLLAX
tWHQX
tAVLL
tQVWH
port 0
A0 to A7 from RI or DPL
DATA OUT
A0 to A7 from PCL
INSTR IN
tAVWL
port 2
P2[7:0] or A8 to A15 from DPH
A8 to A15 from PCH
002aaa550
Fig 23. External data memory write cycle
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
46 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
Table 46.
External clock drive
Symbol
Parameter
Oscillator
Unit
40 MHz
Variable
Min
Max
Min
Max
fosc
oscillator frequency
-
-
0
40
MHz
Tcy(clk)
clock cycle time
25
-
-
-
ns
tCHCX
clock HIGH time
8.75
-
0.35Tcy(clk)
0.65Tcy(clk)
ns
tCLCX
clock LOW time
8.75
-
0.35Tcy(clk)
0.65Tcy(clk)
ns
tCLCH
clock rise time
-
10
-
-
ns
tCHCL
clock fall time
-
10
-
-
ns
VDD − 0.5 V
0.45 V
0.2VDD + 0.9 V
0.2VDD − 0.1 V
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 24. External clock drive waveform
Table 47.
Symbol
Serial port timing
Parameter
Oscillator
Unit
40 MHz
Variable
Min
Max
Min
Max
tXLXL
serial port clock cycle time
0.3
-
12Tcy(clk)
-
µs
tQVXH
output data set-up to clock rising
edge time
117
-
10Tcy(clk) − 133
-
ns
tXHQX
output data hold after clock rising
edge time
0
-
2Tcy(clk) − 50
-
ns
tXHDX
input data hold after clock rising edge 0
time
-
0
-
ns
tXHDV
input data valid to clock rising edge
time
117
-
10Tcy(clk) − 133
ns
-
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
47 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
instruction
0
1
2
3
4
5
6
7
8
ALE
tXLXL
clock
tXHQX
tQVXH
output data
0
write to SBUF
input data
1
2
3
4
5
6
7
tXHDX
set TI
tXHDV
valid
valid
valid
valid
valid
valid
valid
valid
clear RI
set RI
002aaa552
Fig 25. Shift register mode timing waveforms
to tester
to DUT
CL
002aaa555
Fig 26. Test load example
VDD
P0
clock
signal
VDD
RST
(n.c.)
XTAL2
XTAL1
VSS
VDD
IDD
VDD
8
EA
002aaa556
All other pins disconnected
Fig 27. IDD test condition, active mode
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
48 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
VDD
IDD
VDD
8
P0
RST
clock
signal
VDD
EA
XTAL2
XTAL1
VSS
(n.c.)
002aaa557
All other pins disconnected
Fig 28. IDD test condition, Idle mode
VDD = 2 V
VDD
P0
RST
(n.c.)
VDD
IDD
8
VDD
EA
XTAL2
XTAL1
VSS
002aaa558
All other pins disconnected
Fig 29. IDD test condition, Power-down mode
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
49 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
10. Package outline
seating plane
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
21
40
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.7
0.51
4
1.70
1.14
0.53
0.38
0.36
0.23
52.5
51.5
inches
0.19
0.02
0.16
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
D
e
e1
L
ME
MH
w
Z (1)
max.
14.1
13.7
2.54
15.24
3.60
3.05
15.80
15.24
17.42
15.90
0.254
2.25
0.56
0.54
0.1
0.6
0.14
0.12
0.62
0.60
0.69
0.63
0.01
0.089
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT129-1
051G08
MO-015
SC-511-40
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 30. Package outline SOT129-1 (DIP40)
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
50 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm
SOT389-1
c
y
X
A
33
23
34
22
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
44
Lp
12
L
detail X
11
1
w M
bp
e
ZD
v M A
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.45
0.30
0.20
0.12
10.1
9.9
10.1
9.9
0.8
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.2
0.1
Z D (1) Z E (1)
1.14
0.85
1.14
0.85
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT389-1
136E08
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
02-06-07
Fig 31. Package outline SOT389-1 (LQFP44)
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
51 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
eD
eE
y
X
39
A
29
28
40
bp
ZE
b1
w M
44
1
E
HE
pin 1 index
A
A4 A1
e
(A 3)
6
β
18
Lp
k
7
detail X
17
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A4
A1
e
UNIT A
A3
D(1) E(1)
eD
eE
HD
bp b1
max.
min.
4.57
4.19
mm
inches
0.81
0.66
HE
k
16.66 16.66
16.00 16.00 17.65 17.65 1.22
1.27
16.51 16.51
14.99 14.99 17.40 17.40 1.07
0.51
0.25
3.05
0.53
0.33
0.180
0.02
0.165
0.01
0.12
0.021 0.032 0.656 0.656
0.05
0.013 0.026 0.650 0.650
0.63
0.59
0.63
0.59
Lp
v
w
y
1.44
1.02
0.18
0.18
0.1
ZD(1) ZE(1)
max. max.
2.16
β
2.16
45 o
0.695 0.695 0.048 0.057
0.007 0.007 0.004 0.085 0.085
0.685 0.685 0.042 0.040
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT187-2
112E10
MS-018
EDR-7319
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
01-11-14
Fig 32. Package outline SOT187-2 (PLCC44)
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
52 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
11. Abbreviations
Table 48.
Acronym list
Acronym
Description
EEPROM
Electrically Erasable Programmable Read-Only Memory
EMI
Electro-Magnetic Interference
LSB
Least Significant Bit
MSB
Most Significant Bit
PWM
Pulse Width Modulator
RC
Resistance-Capacitance
SFR
Special Function Register
UART
Universal Asynchronous Receiver/Transmitter
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
53 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
12. Revision history
Table 49.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
P89V52X2_1
<tbd>
Preliminary data sheet
-
-
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
54 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
13. Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
13.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
14. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
P89V52X2_1
Preliminary data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 7 June 2007
55 of 56
P89V52X2
NXP Semiconductors
80C51 with 256 B RAM, 192 B data EEPROM
15. Contents
1
2
2.1
2.2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
6.3.1
6.3.2
6.4
6.5
6.6
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.8.3
6.8.4
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.10
6.10.1
6.10.2
6.10.3
6.10.4
6.10.5
6.10.6
6.10.7
6.10.8
6.10.9
6.11
6.12
6.12.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
Additional features . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 8
Special function registers . . . . . . . . . . . . . . . . . 8
Memory organization . . . . . . . . . . . . . . . . . . . 11
System clock and clock options . . . . . . . . . . . 11
Clock input options and recommended capacitor
values for the oscillator . . . . . . . . . . . . . . . . . . 11
Clock control register (CKCON) . . . . . . . . . . . 12
ALE control . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Dual data pointers. . . . . . . . . . . . . . . . . . . . . . 13
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 15
Flash organization . . . . . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 15
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . 20
Auto-reload mode (up or down-counter). . . . . 21
Programmable clock-out. . . . . . . . . . . . . . . . . 23
Baud rate generator mode . . . . . . . . . . . . . . . 23
Summary of baud rate equations . . . . . . . . . . 25
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 27
More about UART mode 1 . . . . . . . . . . . . . . . 27
More about UART modes 2 and 3 . . . . . . . . . 27
Multiprocessor communications . . . . . . . . . . . 28
Automatic address recognition . . . . . . . . . . . . 28
Interrupt priority and polling sequence . . . . . . 30
Power-saving modes . . . . . . . . . . . . . . . . . . . 32
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.12.2
6.13
6.13.1
6.13.2
6.13.3
6.13.4
6.13.5
6.13.6
Power-down mode . . . . . . . . . . . . . . . . . . . . . 33
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 33
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Register interface. . . . . . . . . . . . . . . . . . . . . . 34
Mapping the data EEPROM into code space. 34
Reading the data EEPROM . . . . . . . . . . . . . . 34
Erasing a complete page (64 B) . . . . . . . . . . 35
Data EEPROM programming and erasing using
the page register . . . . . . . . . . . . . . . . . . . . . . 35
6.13.7
Data EEPROM write enable . . . . . . . . . . . . . 39
6.13.8
Data EEPROM security bits . . . . . . . . . . . . . . 39
6.13.9
Summary of data EEPROM commands . . . . 39
6.14
User configuration bytes . . . . . . . . . . . . . . . . 40
6.15
UCFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.16
Code security (CSEC) bits . . . . . . . . . . . . . . . 41
7
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42
8
Static characteristics . . . . . . . . . . . . . . . . . . . 42
9
Dynamic characteristics. . . . . . . . . . . . . . . . . 44
9.1
Explanation of symbols . . . . . . . . . . . . . . . . . 45
10
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 50
11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . 54
13
Legal information . . . . . . . . . . . . . . . . . . . . . . 55
13.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 55
13.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14
Contact information . . . . . . . . . . . . . . . . . . . . 55
15
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 7 June 2007
Document identifier: P89V52X2_1