PHILIPS 74AUP2G86DC

74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
Rev. 7 — 14 June 2012
Product data sheet
1. General description
The 74AUP2G86 provides the dual 2-input EXCLUSIVE-OR function.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 Complies with JEDEC standards:
 JESD8-12 (0.8 V to 1.3 V)
 JESD8-11 (0.9 V to 1.65 V)
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8-B (2.7 V to 3.6 V)
 ESD protection:
 HBM JESD22-A114F Class 3A exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Low static power consumption; ICC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial Power-down mode operation
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AUP2G86DC
40 C to +125 C
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
74AUP2G86GT
40 C to +125 C
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1  1.95  0.5 mm
74AUP2G86GF
40 C to +125 C
XSON8
extremely thin small outline package; no leads;
8 terminals; body 1.35  1  0.5 mm
74AUP2G86GD
40 C to +125 C
XSON8U
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3  2  0.5 mm
74AUP2G86GM
40 C to +125 C
XQFN8
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6  1.6  0.5 mm
SOT902-2
74AUP2G86GN
40 C to +125 C
XSON8
extremely thin small outline package; no leads;
8 terminals; body 1.2  1.0  0.35 mm
SOT1116
74AUP2G86GS
40 C to +125 C
XSON8
extremely thin small outline package; no leads;
8 terminals; body 1.35  1.0  0.35 mm
SOT1203
SOT1089
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74AUP2G86DC
p86
74AUP2G86GT
p86
74AUP2G86GF
pH
74AUP2G86GT
p86
74AUP2G86GM
p86
74AUP2G86GN
pH
74AUP2G86GS
pH
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
=1
1A
1B
1Y
2A
2B
2Y
=1
001aah760
Fig 1.
Logic symbol
74AUP2G86
Product data sheet
001aah761
Fig 2.
IEC logic symbol
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Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
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74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
B
Y
A
Fig 3.
mna040
Logic diagram (one gate)
6. Pinning information
6.1 Pinning
74AUP2G86
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
74AUP2G86
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
001aaf174
Transparent top view
001aaf173
Fig 4.
Pin configuration SOT765-1
Fig 5.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP2G86
74AUP2G86
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
1
2B
2A
8
1Y
7
1A
2
6
1B
3
5
2Y
GND
4
1A
VCC
terminal 1
index area
001aaj918
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2
74AUP2G86
Product data sheet
001aaf175
Fig 7.
Pin configuration SOT902-2
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Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
3 of 21
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
SOT902-2
1A, 2A
1, 5
7, 3
data input
1B, 2B
2, 6
6, 2
data input
GND
4
4
ground (0 V)
1Y, 2Y
7, 3
1, 5
data output
VCC
8
8
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
nA
nB
nY
L
L
L
L
H
H
H
L
H
H
H
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO < 0 V
[1]
Min
Max
Unit
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
VO
output voltage
Active mode and Power-down mode
IO
output current
VO = 0 V to VCC
-
20
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
[1]
[2]
Tamb = 40 C to +125 C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
74AUP2G86
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
4 of 21
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
0.8
3.6
V
VI
input voltage
0
3.6
V
VO
output voltage
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
40
+125
C
0
200
ns/V
Tamb
ambient temperature
t/V
input transition rise and fall rate
VCC = 0.8 V to 3.6 V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
VCC = 0.8 V
Typ
Max
Unit
0.70  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.65  VCC -
-
V
Tamb = 25 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
74AUP2G86
Product data sheet
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.30  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.75  VCC -
-
V
IO = 1.7 mA; VCC = 1.4 V
1.11
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.32
-
-
V
IO = 2.3 mA; VCC = 2.3 V
2.05
-
-
V
VI = VIH or VIL
IO = 3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.6
-
-
V
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3  VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.31
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.31
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
5 of 21
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.1
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.2
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.2
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
40
A
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.6
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
1.3
-
pF
VCC = 0.8 V
0.70  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.65  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.6
-
V
V
[1]
Tamb = 40 C to +85 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
-
VCC = 3.0 V to 3.6 V
2.0
-
-
VCC = 0.8 V
-
-
0.30  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.7  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
1.03
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.30
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.55
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3  VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.37
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.35
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
-
-
0.5
A
VI = VIH or VIL
VI = VIH or VIL
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.5
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.6
A
74AUP2G86
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
6 of 21
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.9
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
50
A
[1]
Tamb = 40 C to +125 C
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
VOH
HIGH-level output voltage
LOW-level output voltage
VOL
VCC = 0.8 V
0.75  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.70  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.25  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.30  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.11 -
-
V
IO = 1.1 mA; VCC = 1.1 V
0.6  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
0.93
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.17
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.30
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.11
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.33  VCC V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.41
V
VI = VIH or VIL
IO = 1.9 mA; VCC = 1.65 V
-
-
0.39
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.75
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.75
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.75
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
1.4
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
75
A
[1]
[1]
One input at VCC  0.6 V, other input at VCC or GND.
74AUP2G86
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
7 of 21
74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Max
(125 C)
-
21.2
-
-
-
-
CL = 5 pF
tpd
propagation delay nA or nB to nY; see Figure 8
[2]
VCC = 0.8 V
ns
VCC = 1.1 V to 1.3 V
2.3
5.9
13.1
2.1
14.3
15.8
ns
VCC = 1.4 V to 1.6 V
1.8
4.1
7.7
1.6
8.8
9.7
ns
VCC = 1.65 V to 1.95 V
1.5
3.3
5.9
1.4
6.9
7.6
ns
VCC = 2.3 V to 2.7 V
1.2
2.6
4.4
1.1
5.3
5.9
ns
VCC = 3.0 V to 3.6 V
1.0
2.3
4.0
0.9
4.7
5.2
ns
-
24.7
-
-
-
-
ns
CL = 10 pF
tpd
propagation delay nA or nB to nY; see Figure 8
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
2.6
6.8
14.8
2.4
16.2
17.9
ns
VCC = 1.4 V to 1.6 V
2.2
4.8
8.7
1.9
10.0
11.0
ns
VCC = 1.65 V to 1.95 V
1.8
3.9
6.7
1.7
8.0
8.8
ns
VCC = 2.3 V to 2.7 V
1.5
3.1
5.2
1.4
6.2
6.9
ns
VCC = 3.0 V to 3.6 V
1.3
2.9
4.8
1.3
5.6
6.2
ns
-
28.2
-
-
-
-
ns
CL = 15 pF
tpd
propagation delay nA or nB to nY; see Figure 8
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
3.0
7.6
16.5
2.7
18.1
20.0
ns
VCC = 1.4 V to 1.6 V
2.4
5.3
9.6
2.2
11.3
12.5
ns
VCC = 1.65 V to 1.95 V
2.1
4.4
7.5
1.9
9.0
9.9
ns
VCC = 2.3 V to 2.7 V
1.8
3.6
5.9
1.6
7.0
7.7
ns
VCC = 3.0 V to 3.6 V
1.6
3.3
5.4
1.5
6.4
7.1
ns
VCC = 0.8 V
-
38.5
-
-
-
-
ns
CL = 30 pF
tpd
propagation delay nA or nB to nY; see Figure 8
74AUP2G86
Product data sheet
[2]
VCC = 1.1 V to 1.3 V
3.9
9.9
21.5
3.5
24.1
26.6
ns
VCC = 1.4 V to 1.6 V
3.2
6.9
12.5
2.8
14.8
16.3
ns
VCC = 1.65 V to 1.95 V
2.8
5.7
9.8
2.5
11.7
12.9
ns
VCC = 2.3 V to 2.7 V
2.4
4.7
7.6
2.2
9.1
10.1
ns
VCC = 3.0 V to 3.6 V
2.2
4.4
7.1
2.1
8.3
9.2
ns
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
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74AUP2G86
NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Max
(125 C)
VCC = 0.8 V
-
2.7
-
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
2.9
-
-
-
-
pF
CL = 5 pF, 10 pF, 15 pF and 30 pF
power dissipation
capacitance
CPD
VCC = 1.4 V to 1.6 V
-
3.0
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
3.1
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
3.6
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
4.2
-
-
-
-
pF
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
[3]
f = 1 MHz; VI = GND to VCC
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
12. Waveforms
VI
VM
nA, nB input
GND
t PHL
t PLH
VOH
VM
nY output
VOL
mna224
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
Table 9.
The data input (nA or nB) to output (nY) propagation delays
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
0.8 V to 3.6 V
0.5  VCC
0.5  VCC
VCC
 3.0 ns
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VCC
VEXT
5 kΩ
G
VI
VO
DUT
CL
RT
RL
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9.
Table 10.
Test circuit for measuring switching times
Test data
Supply voltage
Load
VEXT
[1]
VCC
CL
RL
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 k or 1 M
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2  VCC
For measuring enable and disable times RL = 5 k.
For measuring propagation delays, set-up and hold times and pulse width RL = 1 M.
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13. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Fig 10. Package outline SOT765-1 (VSSOP8)
74AUP2G86
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74AUP2G86
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Low-power dual 2-input EXCLUSIVE-OR gate
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 11. Package outline SOT833-1 (XSON8)
74AUP2G86
Product data sheet
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Rev. 7 — 14 June 2012
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74AUP2G86
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Low-power dual 2-input EXCLUSIVE-OR gate
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
E
terminal 1
index area
D
A
A1
detail X
(4×)(2)
e
L
(8×)(2)
b 4
5
e1
1
terminal 1
index area
8
L1
X
0
0.5
scale
Dimensions
Unit
mm
max
nom
min
1 mm
A(1)
0.5
A1
b
D
E
e
e1
L
L1
0.35 0.40
0.04 0.20 1.40 1.05
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.27 0.32
0.12 1.30 0.95
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
SOT1089
sot1089_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-09
10-04-12
MO-252
Fig 12. Package outline SOT1089 (XSON8)
74AUP2G86
Product data sheet
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Rev. 7 — 14 June 2012
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Low-power dual 2-input EXCLUSIVE-OR gate
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
E
A
A1
detail X
terminal 1
index area
e1
v
w
b
e
L1
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 13. Package outline SOT996-2 (XSON8U)
74AUP2G86
Product data sheet
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XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-2
X
A
B
D
terminal 1
index area
E
A
A1
detail X
e
v
w
b
4
3
C
C A B
C
y
y1 C
5
e1
2
6
1
7
terminal 1
index area
8
L
metal area
not for soldering
L1
0
1
Dimensions
Unit(1)
mm
max
nom
min
2 mm
scale
A
0.5
A1
b
D
E
e
e1
0.05 0.25 1.65 1.65
0.20 1.60 1.60 0.55
0.00 0.15 1.55 1.55
0.5
L
L1
v
0.35 0.15
0.30 0.10
0.25 0.05
0.1
w
y
y1
0.05 0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT902-2
---
MO-255
---
sot902-2_po
European
projection
Issue date
10-11-02
11-03-31
Fig 14. Package outline SOT902-2 (XQFN8)
74AUP2G86
Product data sheet
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Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
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Low-power dual 2-input EXCLUSIVE-OR gate
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
1
2
SOT1116
b
4
3
(4×)(2)
L
L1
e
8
7
e1
6
e1
5
e1
(8×)(2)
A1
A
D
E
terminal 1
index area
0
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
b
D
E
e
e1
max 0.35 0.04 0.20 1.25 1.05
nom
0.15 1.20 1.00 0.55
min
0.12 1.15 0.95
0.3
L
L1
0.35 0.40
0.30 0.35
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1116_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-07
SOT1116
Fig 15. Package outline SOT1116 (XSON8)
74AUP2G86
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NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
b
2
1
3
(4×)(2)
4
L
L1
e
8
7
6
e1
e1
5
e1
(8×)(2)
A1
A
D
E
terminal 1
index area
0
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
b
D
E
e
e1
L
L1
max 0.35 0.04 0.20 1.40 1.05
0.35 0.40
nom
0.15 1.35 1.00 0.55 0.35 0.30 0.35
min
0.12 1.30 0.95
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1203_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-06
SOT1203
Fig 16. Package outline SOT1203 (XSON8)
74AUP2G86
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14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP2G86 v.7
20120614
Product data sheet
-
74AUP2G86 v.6
Modifications:
74AUP2G86 v.6
Modifications:
•
For type number 74AUP2G86GM the SOT code has changed to SOT902-2.
20111208
•
Product data sheet
-
74AUP2G86 v.5
Legal pages updated.
74AUP2G86 v.5
20100727
Product data sheet
-
74AUP2G86 v.4
74AUP2G86 v.4
20090629
Product data sheet
-
74AUP2G86 v.3
74AUP2G86 v.3
20090504
Product data sheet
-
74AUP2G86 v.2
74AUP2G86 v.2
20080319
Product data sheet
-
74AUP2G86 v.1
74AUP2G86 v.1
20061009
Product data sheet
-
-
74AUP2G86
Product data sheet
All information provided in this document is subject to legal disclaimers.
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Low-power dual 2-input EXCLUSIVE-OR gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AUP2G86
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2012
© NXP B.V. 2012. All rights reserved.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
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20 of 21
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NXP Semiconductors
Low-power dual 2-input EXCLUSIVE-OR gate
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 June 2012
Document identifier: 74AUP2G86