INTEGRATED CIRCUITS 74F598 8-bit shift register with input storage registers (3-State) Product specification IC15 Data Handbook 1991 Oct 21 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) FEATURES 74F598 The shift register load function has been modified to load when both SHLD and SHCP are Low. When SHCP is High the shift register load operation is not performed. Data will be properly shifted on the rising edge of SHCP when SHLD is High. • High impedance PNP base input for reduced loading (20µA in High and Low states) • 8–bit parallel storage register • Shift register has asynchronous direct overriding reset • Shift load SHLD is functional when SHCP is Low and locked out when SHCP is High. • Guaranteed shift frequency DC to 105MHz • Parallel 3–State I/O storage register inputs and shift register parallel outputs TYPE TYPICAL SHCP fmax TYPICAL SUPPLY CURRENT (TOTAL) 100MHz 75mA 74F598 ORDERING INFORMATION ORDER CODE DESCRIPTION The 74F598 consists of an 8–bit storage register feeding a parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both the storage register and shift register have positive edge–triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous load. DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 20–pin plastic DIP N74F598N SOT146-1 20–pin plastic SOL N74F598D SOT163-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) High/ Low LOAD VALUE High/Low I/On Parallel data input 1.0/0.033 20µA/20µA Ds0, Ds1 Serial data inputs 1.0/0.033 20µA/20µA SHCP Shift register clock pulse input 1.0/0.033 20µA/20µA STCP Storage register clock pulse input 1.0/0.033 20µA/20µA Shift register clock pulse enable input 1.0/0.033 20µA/20µA SHLD Shift register load input (active Low) 1.0/0.033 20µA/20µA SHRST Shift register reset input (active Low) 1.0/0.033 20µA/20µA SHCPEN Serial data select input 1.0/0.033 20µA/20µA OE S Output enable input 1.0/0.033 20µA/20µA Qs Serial data output 50/33 1.0mA/20mA 150/40 3.0mA/24mA I/On Parallel data outputs Note to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. PIN CONFIGURATION LOGIC SYMBOL 18 I/O0 1 20 VCC I/O1 2 19 S I/O2 3 18 DS0 S 17 DS1 16 OE I/O4 5 16 OE 15 STCP I/O5 6 15 STCP 14 SHCPEN 13 SHCP I/O6 7 14 SHCPEN 12 SHRST I/O7 8 13 SHCP GND 10 1 2 3 4 5 6 7 8 Ds0 Ds1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 19 I/O3 4 SHLD 9 9 SHLD Qs 12 SHRST 11 Qs VCC = Pin 20 GND = Pin 10 SF00375 1991 Oct 21 17 2 11 SF00376 853–1583 04407 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 IEC/IEEE SYMBOL SRG8 16 EN14 12 R 14 G4 13 4C5/4→ 9 C2 15 C1 19 G1 18 1, 5D 17 1, 5D 1 Z6 2D 6, 14 2 2D 3D 3D Z7 3D Z13 7, 14 3 4 5 6 7 8 2D 13, 14 11 SF00377 FUNCTION TABLE INPUTS INPUTS/OUTPUTS OPERATING MODE SHRST STCP SHCP SHLD S OE* I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7 L X L H X L L L L L L L L L L L X L L X L Clear shift register Invalid, state of shift register indeterminate when signal is removed X ↑ X X X H I0 I1 I2 I3 I4 I5 I6 I7 O7 Load data to storage register H X ↑ H L L Ds0 O0 O1 O2 O3 O4 O5 O6 O6 Shift right H X ↑ H H L Ds1 O0 O1 O2 O3 O4 O5 O6 O6 H ↑ L L X H I0 I1 I2 I3 I4 I5 I6 I7 O7 Load data directly to shift register H ↑ L L X X O0 O1 O2 O3 O4 O5 O6 O7 O7 Data transferred from storage register to shift register X X X X X H Z Z Z Z Z Z Z Z NC 3–State H ↑ X H X X NC NC NC NC NC NC NC NC NC Hold H ↑ H X X X NC NC NC NC NC NC NC NC NC Hold (no storage or shift register load Notes to function table D0 – D7 = The level of the steady state inputs to the serial multiplexer. H = High voltage level I0 – I7 = The level of the steady state input at the respective I/O terminal is loaded into the flip–flop while the flip–flop outputs ( except Q7) are isolated from the I/O terminal. L = Low voltage level NC= No change O0 – O7 = The level of the respective Qn flip–flop prior to the last clock Low–to–High transition X = Don’t care Z = High impedance ”off” state * = When the OE input is High, all I/O terminals are at the High impedance state, sequential operation or cleaning of the register is not affected. ↑ = Low–to–High clock transition ↑ = Not Low–to–High clock transition 1991 Oct 21 3 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 LOGIC DIAGRAM 16 OE 12 SHRST SHCPEN SHCP SHLD S Ds0 Ds1 STCP I/O0 14 13 9 19 18 17 15 1 C2 1D 2D S C1 I/O1 2 R C2 3S 1D S C1 I/O2 3 R C2 3S 1D S C1 I/O3 4 C2 3S 1D C1 5 C2 3S 1D C1 6 C2 3S 1D C1 3R R 7 C2 3S 1D S C1 I/O7 3R R S I/O6 3R R S I/O5 3R R S I/O4 3R 3R R 8 C2 3S 1D S 3R 9 Qs C1 R VCC = Pin 20 GND = Pin 10 1991 Oct 21 SF00378 4 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA –0.5 to VCC V Qs 40 mA I/O0 – I/O7 48 mA 0 to +70 °C –65 to +150 °C VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free air temperature range Tstg Storage temperature range RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX VCC Supply voltage 4.5 5.0 5.5 VIH High–level input voltage 2.0 VIL Low–level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current IOL Tamb 1991 Oct 21 Low–level output current Operating free air temperature range V Qs –1 mA I/O0 – I/O7 –3 mA Qs 20 mA I/O0 – I/O7 24 mA +70 °C 0 5 V Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) PARAMETER SYMBOL TEST LIMITS CONDITIONS1 Qs VOH High-level output voltage I/On VOL Low-level output voltage VIK Input clamp voltage II Input current at maximum input voltage VCC = MIN, VIL = MAX, VIL = MAX, IOH = –1mA VIH = MIN, VIL = MAX, IOH = –3mA MIN ±10%VCC 2.5 ±5%VCC 2.7 ±10%VCC 2.4 ±5%VCC 2.7 VCC = MIN, VIL = MAX, ±10%VCC VIH = MIN, IOL = MAX ±5%VCC VCC = MIN, II = IIK TYP2 UNIT MAX V 3.4 V V 3.3 V 0.30 0.50 V 0.30 0.50 V –0.73 -1.2 V others VCC = MAX, VI = 7.0V 100 µA I/On VCC = MAX, VI = 5.5V 1 mA IIH High–level input current VCC = MAX, VI = 2.7V 20 µA IIL Low–level input current VCC = MAX, VI = 0.5V –20 µA IOZH + IIH Off–state output current, High–level voltage applied I/On VCC = MAX, VO = 2.7V 70 µA IOZL + IIL Off–state output current, Low–level voltage applied only VCC = MAX, VO = 0.5V –70 µA -150 mA 100 mA 80 110 mA 73 105 IOS Short–circuit output current3 VCC = MAX ICCH ICC Supply current (total) ICCL -60 68 VCC = MAX ICCZ mA Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of High-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1991 Oct 21 6 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C SYMBOL PARAMETER fmax Maximum clock frequency tPLH tPHL Propagation delay SHCP to Qs tPLH tPHL TEST CONDITION SHCP Waveform 1 STCP Tamb = 0°C to +70°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN TYP 85 100 MAX VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX 70 MHz 140 160 Waveform 1 9.5 6.5 11.5 8.5 14.0 11.5 8.5 6.0 16.0 12.0 ns Propagation delay STCP to Qs (SHLD = Low) Waveform 1 10.0 7.0 11.5 8.5 14.5 11.5 9.0 6.5 16.0 12.5 ns tPLH tPHL Propagation delay SHLD to Qs Waveform 1 9.0 6.0 11.0 8.0 13.5 10.5 8.0 5.5 15.5 11.5 ns tPLH tPHL Propagation delay SHCP to I/On Waveform 1 8.5 5.0 10.5 7.0 13.5 9.5 7.0 4.5 15.5 10.5 ns tPLH tPHL Propagation delay SHLD to I/On Waveform 1 7.5 6.0 9.5 8.0 12.5 11.0 6.5 6.0 14.5 11.5 ns tPHL Propagation delay, SHRST to I/On Waveform 2 6.5 9.0 12.0 6.0 12.5 ns tPHL Propagation delay, SHRST to Qs Waveform 2 6.0 7.5 10.5 5.0 11.0 ns tPZH tPZL Output enable time to High or Low Waveform 5 Waveform 6 3.5 3.0 5.5 5.0 8.5 7.5 3.0 2.5 9.5 8.5 ns tPHZ tPLZ Output disable time to High or Low Waveform 5 Waveform 6 1.5 4.0 3.5 6.0 6.5 9.0 1.5 4.0 7.5 9.5 ns 1991 Oct 21 7 130 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL= 50pF, RL = 500Ω MIN UNIT MAX ts (H) ts (L) Setup time, High or Low Dsn to SHCP Waveform 3 0.0 3.5 1.5 4.5 ns th (H) th (L) Hold time, High or Low DSn to SHCP Waveform 3 0.0 2.5 0.0 3.0 ns ts (H) ts (L) Setup time, High or Low I/On to STCP Waveform 3 2.5 2.5 2.5 3.0 ns th (H) th (L) Hold time, High or Low I/On to STCP Waveform 3 0.0 0.0 1.5 2.0 ns ts (H) ts (L) Setup time, High or Low S to SHCP Waveform 3 3.5 3.0 4.0 3.5 ns th (H) th (L) Hold time, High or Low S to SHCP Waveform 3 2.5 3.0 3.0 3.0 ns ts (H) Setup time, High, STCP to SHLD Waveform 4 7.0 8.0 ns th (L) Hold time, Low, STCP to SHLD (hold mode) Waveform 4 0.0 0.0 ns 0.0 2.0 ns ts (H) ts (L) Setup time, High or Low, SHCPEN to SHCP Waveform 3 0.0 2.0 th (H) th (L) Hold time, High or Low, SHCPEN to SHCP Waveform 3 0.0 4.5 0.0 5.5 ns ts (H) Setup time, High, SHLD to SHCP↑ Waveform 3 7.5 8.5 ns tw (H) tw (L) SHCP Pulse width, High or Low Waveform 1 5.5 4.0 6.5 4.0 ns tw (H) tw (L) STCP Pulse width, High or Low Waveform 1 4.5 4.0 5.5 4.0 ns tw (L) SHRST Pulse width, Low Waveform 1 4.0 4.0 ns tw (L) SHLD Pulse width, Low Waveform 1 4.0 5.0 ns Recovery time, SHRST to SHCP Waveform 2 0.0 0.0 ns trec 1991 Oct 21 8 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 TYPICAL TIMING DIAGRAM OE SHRST SHLD SHCP SHCPEN STCP S Don’t care Ds0 Don’t care Ds1 Don’t care Don’t care Don’t care Don’t care I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Qs output Hi–Z input Hi–Z shift and output SF00379 1991 Oct 21 9 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 AC WAVEFORMS STCP, SHCP, SHLD, SHRST VM 1/fmax VM VM STCP VM VM tw(H) th(L) ts(H) tPHL tw(L) tPLH VM SHLD I/On, Qs VM VM SF00383 SF00380 Waveform 4. Setup time and hold time Waveform 1. Propagation delay for clock input to output, clock pulse widths, and maximum clock frequency, shift register reset and load inputs to serial data output SHRST VM OE VM VM tPZH tPHZ I/On VM 10% 90% VM 0V trec SHCP SF00384 VM Waveform 5. 3-State output enable time to High level, output disable time from High level and transition time to High level tPHL I/On, Qs VOH -0.3V VM OE SF00381 VM VM tPZL Waveform 2. Propagation delay for shift register reset to serial data output, shift register reset to shift register, shift register input recovery time I/On 90% tPLZ 3.5V VM 10% VOL +0.3V Dsn, I/On, SHCP, SHLD, SHCPEN SF00385 VM ts(H) SHCP, STCP SHLD VM th(H) VM VM ts(L) VM Waveform 6. 3-State output enable time to Low level, output disable time from Low level and transition time to Low level th(L) VM SF00382 Waveform 3. Setup time and hold times Notes to AC waveforms 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance. 1991 Oct 21 10 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for Open Collector Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00128 1991 Oct 21 11 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) DIP20: plastic dual in-line package; 20 leads (300 mil) 1991 Oct 21 12 74F598 SOT146-1 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1991 Oct 21 13 74F598 SOT163-1 Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 14 Date of release: 10-98 9397-750-05145