99443 rev 4.0. USB3, P26, FAB2, MAGNACHIP.pdf

Cypress Semiconductor
Product Qualification Report
QTP# 99443 VERSION 4.0
August 2006
USB3 Device Family
P26 Technology, Fab2 - Magnachip
CY7C64013
Full-Speed USB (12-Mbps) Function
CY7C64113
CY7C65113
USB Hub with Microcontroller
CY7C66013
CY7C66113
Full-Speed USB (12 Mbps) Peripheral
Controller with Integrated Hub
CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:
Fredrick Whitwer
Principal Reliability Engineer
(408) 943-2722
Mira Ben-Tzur
Quality Engineering Director
(408) 943-2675
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 2 of 13
August 2006
QUALIFICATION HISTORY
Qual
Report
Description of Qualification Purpose
Date
Comp
99443
P26 Transfer from CTI to Magnachip, Technology Qual
Apr 00
053801
Qualify 7C66021AU USB3 Device at Magnachip on P26 Technology
Oct 05
054604
Verify Qualification of P26 Technology at Magnachip
Feb 06
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 3 of 13
August 2006
PRODUCT DESCRIPTION (for qualification)
Qualification Purpose: Qualify 7C66021AU USB3 Device Family at Magnachip using P26 Technology
Marketing Part #:
CY7C64013, CY7C64113, CY7C65113, CY7C66013, CY7C66113
Device Description:
Full Speed USB (12Mbps) Peripheral Controller with Integrated Hub
Cypress Division:
Cypress Semiconductor Corporation –Consumer and Computation Division (CCD)
Overall Die (or Mask) REV Level (pre-requisite for qualification):
Rev. G
What ID markings on Die: 7C6602A
TECHNOLOGY/FAB PROCESS DESCRIPTION - P26
Number of Metal Layers:
2
Metal
Composition:
Metal 1: 1500Å TiW / 4000Å Al / 750Å TiW
Metal 2: 1500Å TiW / 8000Å Al / 750Å TiW
Passivation Type and Materials:
Oxynitride
Generic Process Technology/Design Rule (µ-drawn):
CMOS, Double Metal/0.65µm
Gate Oxide Material/Thickness (MOS):
SiO2, 165Å
Name/Location of Die Fab (prime) Facility:
Magnachip/Cheong-Ju-Korea
Die Fab Line ID/Wafer Process ID:
Fab2/P26
PACKAGE AVAILABILITY
PACKAGE
ASSEMBLY SITE FACILITY
28-Lead SOIC
CML-R, INDNS-O, MMT-X
48/56-Lead SSOP
CML-R
28-Pin PDIP
INDNS-O
48-Pin PDIP
INDNS-O, MMT-X
56-QFN
CML-RA, OSE-T, SEOL-L
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 4 of 13
August 2006
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation:
Package Outline, Type, or Name:
Mold Compound Name/Manufacturer:
Mold Compound Flammability Rating:
SZ28
28-Lead 300mil SOIC Package
NittoMP8500
V-0
Oxygen Rating Index:
N/A
Lead Frame Material:
Copper
Lead Finish, Composition / Thickness:
NiPdAu (Ni: 20~80uinch, Pd: 0.8~1.2uinch, Au: 0.12~0.5uinch)
Die Backside Preparation Method/Metallization:
Grinding
Die Separation Method:
Blade Sawing
Die Attach Supplier:
Dexter
Die Attach Material:
QMI 509
Die Attach Method:
Dispensing
Bond Diagram Designation:
10-06322
Wire Bond Method:
Thermosonic
Wire Material/Size:
Au. 1.0 mil
Thermal Resistance Theta JA °C/W:
67.6°C/W
Package Cross Section Yes/No:
N/A
Assembly Process Flow:
11-20049
Name/Location of Assembly (prime) facility:
Cypress Philippines (CML-R)
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location:
CML-R
Fault Coverage:
100%
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 5 of 13
August 2006
RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT
Stress/Test
Test Condition
(Temp/Bias)
Result
P/F
Dynamic Operating Condition, Vcc Max = 5.75V, 150°C
P
Dynamic Operating Condition, Vcc Max = 5.75V, 150°C
P
High Temperature Steady State Life
Static Operating Condition, Vcc Max = 5.75V, 150°C
P
Long Life Verification
Dynamic Operating Condition, Vcc Max = 5.75V, 150°C
P
Low Temperature Operating Life
-30C, 6.5V, 8MHZ
P
High Accelerated Saturation Test
(HAST)
130°C, 5.5V, 85%RH
Precondition: JESD22 Moisture Sensitivity MSL 1
168 Hrs, 85C/85%RH+3IR-Reflow, 220°C+0, -5°C
P
Temperature Cycle
MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C
Precondition: JESD22 Moisture Sensitivity MSL 1
P
High Temperature Operating Life
Early Failure Rate
High Temperature Operating Life
Latent Failure Rate
Pressure Cooker
168 Hrs, 85C/85%RH+3IR-Reflow, 220°C+0, -5°C
121°C, 100%RH, 15 Psig
Precondition: JESD22 Moisture Sensitivity MSL 1
P
168 Hrs, 85C/85%RH+3IR-Reflow, 220°C+0, -5°C
Aged Bond Strength
MIL-STD-883, Method 2011
P
Bond Pull
Cypress Spec. 12-00292
P
Data Retention (Hermetic)
250C, non-biased
P
Data Retention (Plastic)
150C/165C, non-biased
P
Electrostatic Discharge
Human Body Model (ESD-HBM)
2,200V
JESD22, Method A114-B
P
Electrostatic Discharge
Human Body Model (ESD-HBM)
2,200V
MIL-STD-883, Method 3015.7
P
Electrostatic Discharge
Charge Device Model (ESD-CDM)
500V
Cypress Spec. 25-00020
P
Acoustic Microscopy
Cypress Spec. 25-00104
P
Dynamic Latch-up
125C, 8.5V
P
Static Latch-up
125C, ± 200mA/± 300mA
P
Cypress Spec. 01-00081
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 6 of 13
August 2006
RELIABILITY FAILURE RATE SUMMARY
Stress/Test
Device Tested/
Device Hours
#
Fails
Activation
Energy
Thermal
AF4
Failure Rate
High Temperature Operating Life
Early Failure Rate
4,197 Devices
0
N/A
N/A
0 PPM
High Temperature Operating Life1,2
Long Term Failure Rate
446,980 DHRs
0
0 .7
170
12 FITs
1
2
3
Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C.
Chi-squared 60% estimations used to calculate the failure rate.
Thermal Acceleration Factor is calculated from the Arrhenius equation
E  1 1  
AF = exp  A  -  
 k  T 2 T1  
where:
EA =The Activation Energy of the defect mechanism.
k = Boltzmann's constant = 8.62x10-5 eV/Kelvin.
T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device
at use conditions.
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 7 of 13
August 2006
Reliability Test Data
QTP #:
Device
STRESS:
Fab Lot #
Assy Lot #
99443
Assy Loc Duration
Samp
Rej
Failure Mechanism
ACOUSTIC, MSL1
CY7C64113-PVC
2948678
619938213
CSPI-R
COMP
15
0
CY7C64113-PVC
2001294
610002661
CSPI-R
COMP
15
0
CY7C64113-PVC
2004702
610004994
CSPI-R
COMP
15
0
INDNS-O
COMP
5
0
STRESS: BOND PULL
CY7C65113-SC
STRESS:
2948678
519919718
DATA RETENTION, HERMETIC, 250C
CY7C66113-PVC
2001294
610002660
CSPI-R
96
78
0
CY7C66113-PVC
2001294
610002660
CSPI-R
168
78
0
CY7C64013-*DC
2004702
USA-C
96
78
0
CY7C64013-*DC
2004702
USA-C
168
78
0
CY7C64013-*DC
2004741
USA-C
96
78
0
STRESS: DATA RETENTION, PLASTIC, 150C
CY7C64113-PVC
2948678
619938213
CSPI-R
500
82
0
CY7C64113-PVC
2948678
619938213
CSPI-R
1000
82
0
CY7C64113-PVC
2001294
610002661
CSPI-R
500
82
0
CY7C64113-PVC
2001294
610002661
CSPI-R
1000
82
0
STRESS: DATA RETENTION, PLASTIC, 165C
CY7C64113-PVC
2004702
610004994
CSPI-R
168
83
0
CY7C64113-PVC
2004702
610004994
CSPI-R
552
83
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 5.75V, Vcc Max)
CY7C65113-SC
2001294
510000813
INDNS-O
48
351
0
CY7C65113-SC
2004702
510001508
INDNS-O
48
378
0
CY7C65113-SC
2948678
519919718
INDNS-O
48
348
0
STRESS: LONG LIFE VERIFICATION, 150C, 5.75V
CY7C65113-SC
2948678
519919718
INDNS-O
1000
120
0
CY7C65113-SC
2948678
519919718
INDNS-O
2000
120
0
STRESS: LOW TEMPERATURE OPERATING LIFE (-30C, 6. 5V, 8MHZ)
CY7C64113-PVC
2948678
619938213
CSPI-R
500
48
0
CY7C64113-PVC
2948678
619938213
CSPI-R
1000
47
0
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 8 of 13
August 2006
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot #
99443
Assy Loc Duration
Samp
Rej
Failure Mechanism
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 5.75V, Vcc Max)
CY7C65113-SC
2001294
510000813
INDNS-O
80
351
0
CY7C65113-SC
2001294
510000813
INDNS-O
500
120
0
CY7C65113-SC
2004702
510001508
INDNS-O
80
120
0
CY7C65113-SC
2004702
510001508
INDNS-O
500
120
0
CY7C64113-PVC
2004702
610004994
CSPI-R
80
120
0
CY7C64113-PVC
2004702
610004994
CSPI-R
500
120
0
CY7C65113-SC
2948678
519919718
INDNS-O
80
120
0
CY7C65113-SC
2948678
519919718
INDNS-O
500
120
0
STRESS: HI-ACCEL SATURATION TEST (130C, 85%RH, 5.75V), PRE COND 168 HRS 85C/85%RH, MSL1
CY7C66113-PVC
2001294
610002660
CSPI-R
128
50
0
CY7C64113-PVC
2004702
610004994
CSPI-R
128
45
0
CY7C64113-PVC
2948678
619938213
CSPI-R
128
50
0
STRESS: PRESSURE COOKER TEST (121C, 100%RH), 15 Psig, PRE COND 168 HRS 85C/85%RH, MSL1
CY7C65113-SC
2001294
510000813
INDNS-O
168
50
0
CY7C64113-PVC
2001294
610002661
CSPI-R
168
50
0
CY7C64113-PVC
2004702
610004994
CSPI-R
168
49
0
CY7C66113-PVC
2948678
619938214
CSPI-R
168
50
0
STRESS: ESD-CHARGE DEVICE MODEL (1,000V)
CY7C66113-PVC
2001294
610002660
CSPI-R
COMP
3
0
CY7C64113-PVC
2004702
610004994
CSPI-R
COMP
3
0
CY7C65013-PVC
2948678
619938212
CSPI-R
COMP
3
0
CY7C64113-PVC
2948678
619938213
CSPI-R
COMP
3
0
CY7C66113-PVC
2948678
619938214
CSPI-R
COMP
3
0
STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015 (2,200V)
CY7C66113-PVC
2001294
610002660
CSPI-R
COMP
3
0
CY7C64113-PVC
2004702
610004994
CSPI-R
COMP
3
0
CY7C65013-PVC
2948678
619938212
CSPI-R
COMP
3
0
CY7C64113-PVC
2948678
619938213
CSPI-R
COMP
3
0
CY7C66113-PVC
2948678
619938214
CSPI-R
COMP
4
0
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 9 of 13
August 2006
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot #
99443
Assy Loc Duration
Samp
Rej
STRESS: STATIC LATCH-UP TESTING (125C, 10V, +/-300mA)
CY7C64113-PVC
2948678
619938213
CSPI-R
COMP
3
0
STRESS: TC COND. C -65C TO 150C, PRE COND 168 HRS 85C/85%RH, MSL1
CY7C65113-SC
2001294
510000813
INDNS-O
300
49
0
CY7C65113-SC
2001294
510000813
INDNS-O
500
49
0
CY7C64113-PVC
2001294
610002661
CSPI-R
300
49
0
CY7C64113-PVC
2001294
610002661
CSPI-R
500
49
0
CY7C64113-PVC
2001294
610002661
CSPI-R
1000
48
0
CY7C64113-PVC
2004702
610004994
CSPI-R
300
48
0
CY7C64113-PVC
2004702
610004994
CSPI-R
500
48
0
CY7C64113-PVC
2004702
610004994
CSPI-R
1000
48
0
CY7C64113-PVC
2948678
619938213
CSPI-R
300
50
0
CY7C64113-PVC
2948678
619938213
CSPI-R
500
50
0
CY7C64113-PVC
2948678
619938213
CSPI-R
1000
48
0
Note: PV is an index of Cypress Module Package.
Failure Mechanism
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 10 of 13
August 2006
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot #
Assy Loc
053801
Duration Samp
Rej
STRESS: ESD-CHARGE DEVICE MODEL, (500V)
CY7C64013 (7C64013G)
2535026
610539904
CML-R
COMP
9
0
9
0
COMP
3
0
COMP
3
0
STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, (2,200V)
CY7C64013 (7C64013G)
2535026
610539904
CML-R
COMP
STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, (2,200V)
CY7C64013 (7C64013G)
2535026
610539904
CML-R
STRESS: STATIC LATCH-UP TESTING (125C, 10V, +/-300mA)
CY7C64013 (7C64013G)
2535026
610539904
CML-R
Failure Mechanism
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 11 of 13
August 2006
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot#
054604
Assy Loc
Duration
Samp
Rej
Failure Mechanism
STRESS: ACOUSTIC-MSL3
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
COMP
15
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
COMP
15
0
STRESS: AGE BOND STRENGTH
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
COMP
10
0
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
COMP
10
0
STRESS: DATA RETENTION, 150C, no bias
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
500
80
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
1000
80
0
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
500
80
0
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
1000
80
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
500
80
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
1000
80
0
STRESS: ESD-CHARGE DEVICE MODEL, (500V)
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
COMP
9
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
COMP
9
0
CY7C63413C (7C634131CU)
2544313
INDNS-O
COMP
9
0
510505323
STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, (2,200V)
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
COMP
9
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
COMP
9
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
COMP
9
1
STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
COMP
3
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
COMP
3
0
STRESS: STATIC LATCH-UP TESTING (125C, 8.5V, +/-200mA)
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
COMP
3
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
COMP
3
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
3
0
COMP
Contact Damage
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 12 of 13
August 2006
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot#
054604
Assy Loc
Duration
CML-R
COMP
Samp
Rej
Failure Mechanism
STRESS: DYNAMIC LATCH-UP, 8.5V
CY7C65113C (7C651131GU)
2543258
610550662
3
0
STRESS: HI-ACCEL SATURATION TEST (130C, 85%RH, 5.75V), PRE COND 192 HRS 30C/60%RH, MSL3
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
128
50
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
128
49
0
128
48
0
STRESS: HI-ACCEL SATURATION TEST (130C, 85%RH, 5.75V)
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 5.75V), Vcc Max)
CY7C65113C (7C651131GU)
2544369
610552933
CML-R
48
816
0
CY7C65113C (7C651131GU)
2544348
610552934
CML-R
48
1006
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
48
1224
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
48
1151
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 5.75V), Vcc Max)
CY7C65113C (7C651131GU)
2544369
610552933
CML-R
80
130
0
CY7C65113C (7C651131GU)
2544369
610552933
CML-R
500
130
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
80
130
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
500
130
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
80
117
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
500
117
0
STRESS: LONG LIFE VERIFICATION- (150C, 5.75V, Vcc Max)
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
1000
130
0
STRESS: HIGH TEMPERATURE STEADY STATE LIFE- (150C, 5.75V, Vcc Max)
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
80
80
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
168
80
0
STRESS: PRESSURE COOKER TEST (121C, 100%RH), 15 Psig, PRE COND 192 HRS 30C/60%RH, MSL3
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
168
50
0
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
168
50
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
168
50
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
288
50
0
Cypress Semiconductor
USB3 Device Family, P26 Technology, Fab2-Magnachip
Device: CY7C64x13/CY7C65x13/7C66x13
QTP # 99443 V, 4.0
Page 13 of 13
August 2006
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot#
Assy Loc
054604
Duration
Samp
Rej
STRESS: HIGH TEMPERATURE STORAGE, 150C, no bias
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
500
50
0
CY7C64013C (7C640131GU)
2535026
610539904
CML-R
1000
50
0
STRESS: TC COND. C -65C TO 150C
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
300
50
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
500
50
0
CY7C63413C (7C634131CU)
2544313
510505323
INDNS-O
1000
50
0
STRESS: LOW TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, -30C, 6.5V, Vcc
CY7C65113C (7C651131GU)
2543258
610550662
CML-R
500
51
0
Failure Mechanism
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