005105 rev 5.0 R52FFD.3.CY7C65640.pdf

Cypress Semiconductor
Product Qualification Report
QTP# 005105 VERSION 5.0
June 2005
CY7C65640A TetraHub High Speed USB
Hub Controller
R52FFD-3 Technology, Fab 4
CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:
Sabbas Daniel
Quality Engineering Director
(408) 943-2685
Fredrick Whitwer
Stafff Reliability Engineer
(408) 943-2722
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 2 of 13
TECHNOLOGY QUALIFICATION HISTORY
Qual
Report
Description of Qualification Purpose
Date
Comp
99311
New R52D-3 Technology /New 2Meg,CY7C1329 SRAM device
Aug 99
011205
New Technology derivative R52FFD-3, Fab 4 / New 1Meg, GB/s Quad Port Switch
CY7C04312BV/ CY7C04314BV
June 01
005105
New TetraHub High Speed USB Hub Controller CY7C65640
Oct 02
040601
HX2 Rev D CY7C65640/4 Mask change (CTM1, MM1, V1M, MM2) Fix TT
Mar 04
044401
HX2 Rev E CY7C65640A Mask change (CTM1, MM1, V1M, MM2)
Nov 04
Cypress products are manufactured using qualified processes. The technology qualification for this product is referenced
above and must be considered to get a complete and thorough evaluation of the reliability of the product.
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 3 of 13
PRODUCT DESCRIPTION (for qualification)
Qualification Purpose: Qualify New TetraHub High Speed USB Hub Controller CY7C65640A in R52FFD-3 technology, Fab 4
Marketing Part #:
CY7C65640A
Device Description:
3.3V, Commercial , available in 56-Lead QFN package
Cypress Division:
Cypress Semiconductor Corporation -Personal Communication Division (PCD)
Overall Die (or Mask) REV:
What ID markings on Die:
Rev. C/D/E
7C65640C/7C65641D/7C65642E
TECHNOLOGY/FAB PROCESS DESCRIPTION R52FFD-3
Number of Metal Layers:
2
Metal Composition:
Metal 1: 500Å TiW/6,000Å Al-0.5%Cu/300Å TiW
Metal 2: 300Å Ti/8,000Å Al-0.5%Cu/300Å TiW
Passivation Type and Materials:
1,000Å Oxide / 9,000 Å Nitride
Free Phosphorus contents in top glass layer(%):
0%
Die Coating(s), if used:
N/A
Number of Transistors:
500,000
Number of Gates:
100,000
Generic Process Technology/Design Rule (µ-drawn):
CMOS, Double Metal, 0.25 µm
Gate Oxide Material/Thickness (MOS):
SiO2 55Å
Name/Location of Die Fab (prime) Facility:
Cypress Semiconductor – Bloomington, MN
Die Fab Line ID/Wafer Process ID:
Fab4/R52FFD-3
PACKAGE AVAILABILITY
PACKAGE
56-Lead QFN
ASSEMBLY FACILITY SITE
Amkor Seoul Korea (KOREA-L)
Note: Package Qualification details upon request.
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 4 of 13
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation:
Package Outline, Type, or Name:
Mold Compound Name/Manufacturer:
Mold Compound Flammability Rating:
LF56
56-Lead Quad Flat no Lead (QFN)
Sumitomo EME G700
V-O per UL94
Oxygen Rating Index:
>28%
Lead Frame Material:
Copper
Lead Finish, Composition / Thickness:
Tin-Lead, 85%Sn, 15%Pb (300~800 uinch)
Die Backside Preparation Method/Metallization:
N/A
Die Separation Method:
Wafer Saw
Die Attach Supplier:
Ablebond
Die Attach Material:
Ablebond 8290
Die Attach Method:
Dispensing
Bond Diagram Designation
10-04394
Wire Bond Method:
Thermosonic
Wire Material/Size:
Gold, 1.0mil
Thermal Resistance Theta JA °C/W:
23.27°C/W
Package Cross Section Yes/No:
N/A
Assembly Process Flow:
49-10045
Name/Location of Assembly (prime) facility:
Amkor Korea (SEOL_L)
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location:
Cypress Philippines (CML-R)
Fault Coverage:
98%
Note: Please contact a Cypress Representative for other packages availability
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 5 of 13
RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS
Stress/Test
Test Condition
(Temp/Bias)
Result
P/F
High Temperature Operating Life
Dynamic Operating Condition, Vcc = 3.8V, 125°C
P
Early Failure
Dynamic Operating Condition, Vcc = 4.5V, 150°C
High Temperature Operating Life
Dynamic Operating Condition, Vcc = 3.8V, 125°C
Latent Failure Rate
Dynamic Operating Condition, Vcc = 3.8V, 150°C
High Temperature Steady State Life
Dynamic Operating Condition, Vcc = 3.63V, 150°C
P
High Temperature
165°C, no bias
P
Temperature Cycle
MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C
Precondition: JESD22 Moisture Sensitivity MSL 3
P
P
192 Hrs., 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C
Pressure Cooker
121°C, 100%RH
Precondition: JESD22 Moisture Sensitivity MSL 3
P
192 Hrs., 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C
High Accelerated Saturation Test (HAST)
130°C, 3.63V, 85%RH
Precondition: JESD22 Moisture Sensitivity MSL 3
P
192 Hrs., 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C
Electrostatic Discharge
Human Body Model (ESD-HBM)
2,200V
P
Electrostatic Discharge
Human Body Model (ESD-HBM)
2,200V
Electrostatic Discharge
Charge Device Model (ESD-CDM)
500V
Low Temperature Operating Life
-30°C, 4.3V
P
Alpha Particle Sensitivity
Cypress Spec. 25-00055
P
Age Bond Pull
MIL-STD-883, Method 2011
P
Current Density
Cypress Spec. 22-00029
P
Acoustic Microscopy, MSL 3
Cypress Spec. 25-00104
P
SEM X-Section
MIL-STD-883C, Method 2018.2
P
Static Latchup Sensitivity
125ºC, ± 300mA
P
MIL-STD-883, Method 3015
JESD22, Method A114-B
P
P
Cypress Spec. 25-00020
In accordance with JEDEC 17. Cypress Spec. 01-00081
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 6 of 13
RELIABILITY FAILURE RATE SUMMARY
Stress/Test
Device Tested/
Device Hours
#
Fails
Activation
Energy
Acceleration
Factor4
Failure Rate
High Temperature Operating Life
Early Failure Rate @ 125C
2,198 Devices
0
N/A
N/A
0 PPM
High Temperature Operating Life
Early Failure Rate @ 150C
8,317 Devices
1
N/A
N/A
120 PPM
High Temperature Operating Life
Long Term Failure Rate1,,2
2,096,955 HRs
3
0.7
170
8 FIT
.
1
Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C.
Chi-squared 60% estimations used to calculate the failure rate.
3
Thermal Acceleration Factor is calculated from the Arrhenius equation
2
E  1 1  
AF = exp  A  -  
 k  T 2 T1  
where:
EA =The Activation Energy of the defect mechanism.
k = Boltzmann's constant = 8.62x10-5 eV/Kelvin.
T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device
at use conditions.
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 7 of 13
Reliability Test Data
QTP#: 99311
Device
Ass Loc
Fab lot#
Assy lot#
Duration
Samp
Rej
Failure Mechanism
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY7C1329-AC (7C1329D)
CSPI-R
4853292
619902690
COMP
3
0
CY7C1329-AC (7C1329D)
CSPI-R
4901357
619903817
COMP
3
0
STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V
CY7C1329-AC (7C1329D)
CSPI-R
4853292
619902690
COMP
3
0
CY7C1329-AC (7C1329D)
CSPI-R
4901357
619903817
COMP
3
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 4.5V
CY7C1329-AC (7C1329D)
CSPI-R
4905886
619909761
48
2988
0
CY7C1329-AC (7C1329D)
CSPI-R
4905886
619909761
48
1205
0
CY7C1329-AC (7C1329D)
CSPI-R
4905886
619909776
48
871
0
CY7C1329-AC (7C1329D)
CSPI-R
4909345
619911324
48
1584
1
CY7C1329-AC (7C1329D)
CSPI-R
4909345
619911327
48
1669
0
3
0
STRESS: STATIC LATCH-UP TESTING, 125C, 10V, +/-200mA
CY7C1329-AC (7C1329D)
CSPI-R
4853292
619902690
COMP
STRESS: HI-ACCEL SATURATION TEST (130C/85%RH/3.63V), PRECOND. 192 HRS 30C/60%RH, MSL3
CY7C1329-AC (7C1329D)
CSPI-R
4853292
619902690
128
48
0
CY7C1329-AC (7C1329D)
CSPI-R
4853292
619902690
256
48
0
CY7C1329-AC (7C1329D)
CSPI-R
4901357
619903817
128
48
0
STRESS: HIGH TEMPERATURE STORAGE, 165C, NO BIAS
CY7C1329-AC (7C1329D)
CSPI-R
4842121
619815465
336
48
0
CY7C1329-AC (7C1329D)
CSPI-R
4843204
619815797
336
48
0
STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 3.63V
CY7C1329-AC (7C1329D)
CSPI-R
4842121
619815465
80
80
0
CY7C1329-AC (7C1329D)
CSPI-R
4842121
619815465
168
80
0
CY7C1329-AC (7C1329D)
CSPI-R
4843204
619815797
80
80
0
CY7C1329-AC (7C1329D)
CSPI-R
4843204
619815797
168
80
0
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRECOND. 192 HRS 30C/60%RH, MSL3
CY7C1329-AC (7C1329D)
CSPI-R
4853292
619902690
168
48
0
CY7C1329-AC (7C1329D)
CSPI-R
4901357
619903817
168
46
0
PARTICLE DEFECT
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 8 of 13
Reliability Test Data
QTP#: 99311
Device
Ass Loc
Fab lot#
Assy lot#
Duration
Samp
Rej
Failure Mechanism
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 3.8V
CY7C1329-AC (7C1329D)
CSPI-R
4905886
619909761
80
1196
0
CY7C1329-AC (7C1329D)
CSPI-R
4905886
619909761
500
799
0
CY7C1329-AC (7C1329D)
CSPI-R
4909345
619911324
80
1491
1
UNKNOWN CAUSE
CY7C1329-AC (7C1329D)
CSPI-R
4909345
619911324
500
1199
1
UNKNOWN CAUSE
CY7C1329-AC (7C1329D)
CSPI-R
4909345
619911327
80
1640
0
CY7C1329-AC (7C1329D)
CSPI-R
4909345
619911327
500
1451
1
STRESS: STATIC LATCH-UP TESTING, 9.98V +/-200 mA
CY7C1329-AC (7C1329D)
CSPI-R
4853292
619902690
COMP
3
0
CY7C1329-AC (7C1329D)
CSPI-R
4901357
619903817
COMP
3
0
STRESS: TC COND. C, -65 TO 150C, PRECOND. 192 HRS 30C/60%RH, MSL 3
CY7C1329-AC (7C1329D)
CSPI-R
4842121
619815465
300
48
0
CY7C1329-AC (7C1329D)
CSPI-R
4842121
619815465
1000
48
0
CY7C1329-AC (7C1329D)
CSPI-R
4843204
619815797
300
45
0
CY7C1329-AC (7C1329D)
CSPI-R
4843204
619815797
1000
45
0
UNKNOWN CAUSE
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 9 of 13
Reliability Test Data
QTP #:
Device
Fab Lot #
011205
Assy Lot #
Ass Loc
Duration
Samp
Rej Failure Mechanism
STRESS: ACOUSTIC, MSL3
CY7C0430BV-BGI (7C04301A)
4044731
610051943
TAIWN-G
COMP
15
0
CY7C0430BV-BGI (7C04301A)
4045135
610101405
TAIWN-G
COMP
15
0
CY7C0430BV-BGI (7C04301A)
4047508
610103357
TAIWN-G
COMP
15
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 3.8V, Vcc Max
CY7C0430BV-BGI (7C04301A)
4049157
610108702
TAIWN-G
96
700
0
CY7C0430BV-BGI (7C04301A)
4101120
610110033
TAIWN-G
96
504
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, 3.8V, Vcc Max
CY7C0430BV-BGI (7C04301A)
4049157
610108702
TAIWN-G
168
410
0
CY7C0430BV-BGI (7C04301A)
4049157
610108702
TAIWN-G
500
409
0
CY7C0430BV-BGI (7C04301A)
4049157
610108702
TAIWN-G
1000
408
0
CY7C0430BV-BGI (7C04301A)
4101120
610110033
TAIWN-G
168
410
0
CY7C0430BV-BGI (7C04301A)
4101120
610110033
TAIWN-G
500
409
0
CY7C0430BV-BGI (7C04301A)
4101120
610110033
TAIWN-G
1000
407
0
TAIWN-G
COMP
9
0
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY7C0430BV-BGI (7C04301A)
4101120
610110033
STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V
CY7C0430BV-BGI (7C04301A)
4101120
610110033
TAIWN-G
COMP
9
0
TAIWN-G
COMP
3
0
TAIWN-G
500
48
0
STRESS: STATIC LATCH-UP TESTING, 125C, 10V, +/300mA
CY7C0430BV-BGI (7C04301A)
4101120
610110033
STRESS: LOW TEMPERATURE OPERATING LIFE, -30C, 4.3V
CY7C0430BV-BGI (7C04301A)
4025035
610044436
STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3.63V, PRE COND 192 HR 30C/60%RH, MSL3
CY7C0430BV-BGI (7C04301A)
4044731
610051943
TAIWN-G
128
46
0
CY7C0430BV-BGI (7C04301A)
4045135
610101405
TAIWN-G
128
57
0
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 192 HR 30C/60%RH, MSL3
CY7C0430BV-BGI (7C04301A)
4044731
610051943
TAIWN-G
168
48
0
CY7C0430BV-BGI (7C04301A)
4045135
610101405
TAIWN-G
168
50
0
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 10 of 13
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot #
Ass Loc
011205
Duration Samp Rej Failure Mechanism
STRESS: TC COND. C -65C TO 150C, PRECONDITION 192 HRS 30C/60%RH, MSL3
CY7C0430BV-BGI (7C04301A)
4044731
610051943
TAIWN-G
300
48
0
CY7C0430BV-BGI (7C04301A)
4044731
610051943
TAIWN-G
500
48
0
CY7C0430BV-BGI (7C04301A)
4044731
610051943
TAIWN-G
1000
470
CY7C0430BV-BGI (7C04301A)
4045135
610101405
TAIWN-G
300
50
0
CY7C0430BV-BGI (7C04301A)
4045135
610101405
TAIWN-G
500
50
0
CY7C0430BV-BGI (7C04301A)
4045135
610101405
TAIWN-G
1000
50
0
STRESS: TC COND. C -65C TO 150C*
CY7C0430BV-BGI (7C04301A
4049157
610108702
TAIWN-G
300
48
0
CY7C0430BV-BGI (7C04301A)
4049157
610108702
TAIWN-G
500
48
0
CY7C0430BV-BGI (7C04301A)
4049157
610108702
TAIWN-G
1000
47
0
CY7C0430BV-BGI (7C04301A)
4101120
610110033
TAIWN-G
300
48
0
CY7C0430BV-BGI (7C04301A)
4101120
610110033
TAIWN-G
500
48
0
CY7C0430BV-BGI (7C04301A)
4101120
610110033
TAIWN-G
1000
47
0
*Note: No precondition performed.
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 11 of 13
Reliability Test Data
QTP #:
Device
STRESS:
Fab Lot #
Assy Lot #
005105
Ass Loc
Duration
Samp
Rej Failure Mechanism
ACOUSTIC, MSL3
CY7C65640-LFC (7C65640A)
4133340
610138258
SEOL-L
COMP
15
0
CY7C65640-LFC (7C65640A)
4133340
610138259
SEOL-L
COMP
15
0
CY7C65640-LFC (7C65640A)
4133340
610138260
SEOL-L
COMP
15
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 3.8V, Vcc Max
CY7C65640-LFC (7C65640C)
4217056
421705225
SEOL-L
96
994
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, 3.8V, Vcc Max
CY7C65640-LFC (7C65640C)
4217056
421705225
SEOL-L
168
120
0
CY7C65640-LFC (7C65640C)
4217056
421705225
SEOL-L
1000
120
0
STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3. 3V, PRE COND 192 HR 30C/60%RH, MSL3
CY7C65640-LFC (7C65640A)
4144354
421705225
SEOL-L
128
50
0
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 192 HR 30C/60%RH, MSL3
CY7C65640-LFC (7C65640A)
4133340
610138258
SEOL-L
168
50
0
CY7C65640-LFC (7C65640A)
4133340
610138259
SEOL-L
168
50
0
SEOL-L
COMP
9
0
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY7C65640-LFC (7C65640C)
4206970
610213221
STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V
CY7C65640-LFC (7C65640C)
4206970
610213221
SEOL-L
COMP
9
0
SEOL-L
COMP
3
0
STRESS: STATIC LATCH-UP TESTING, 125C, 10V, +/300mA
CY7C65640-LFC (7C65640C)
4206970
610213221
STRESS: TC COND. C -65C TO 150C, PRECONDITION 192 HRS 30C/60%RH, MSL3
CY7C65640-LFC (7C65640A)
4133340
610138258
SEOL-L
300
49
0
CY7C65640-LFC (7C65640A)
4133340
610138258
SEOL-L
500
49
0
CY7C65640-LFC (7C65640A)
4133340
610138258
SEOL-L
1000
49
0
CY7C65640-LFC (7C65640A)
4133340
610138259
SEOL-L
300
50
0
CY7C65640-LFC (7C65640A)
4133340
610138259
SEOL-L
500
50
0
CY7C65640-LFC (7C65640A)
4133340
610138259
SEOL-L
1000
50
0
CY7C65640-LFC (7C65640A)
4133340
610138260
SEOL-L
300
49
0
CY7C65640-LFC (7C65640A)
4133340
610138260
SEOL-L
500
49
0
CY7C65640-LFC (7C65640A)
4133340
610138260
SEOL-L
1000
49
0
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 12 of 13
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot #
040601
Ass Loc
Duration
Samp
Rej Failure Mechanism
SEOL-L
COMP
9
0
3
0
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY7C65640-LFC (7C65641D)
4345354
610403328
STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V
CY7C65640-LFC (7C65641D)
4345354
610403328
SEOL-L
COMP
STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 2,200V
CY7C65640-LFC (7C65641D)
4345354
610403328
SEOL-L
COMP
9
0
SEOL-L
COMP
3
0
STRESS: STATIC LATCH-UP TESTING, 125C, 6.8V, +/300mA
CY7C65640-LFC (7C65641D)
4345354
610403328
Cypress Semiconductor
TetraHub High Speed USB, R52FFD-3 Technology, Fab 4
Device: CY7C65640A
QTP# 005105, V. 5.0
June 2005
Page 13 of 13
Reliability Test Data
QTP #:
Device
Fab Lot #
Assy Lot #
044401
Ass Loc
Duration
Samp
Rej Failure Mechanism
SEOL-L
COMP
9
0
3
0
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY7C65640A-LFC (7C65642E)
4437247
610454474
STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V
CY7C65640A-LFC (7C65642E)
4437247
610454474
SEOL-L
COMP
STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 2,200V
CY7C65640A-LFC (7C65642E)
4437247
610454474
SEOL-L
COMP
9
0
SEOL-L
COMP
3
0
STRESS: STATIC LATCH-UP TESTING, 125C, 7.5V, +/300mA
CY7C65640A-LFC (7C65642E)
4437247
610454474
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