1 2 3 4 5 Lite5200B Evaluation Board A A Table of Contents Page B Description 1 Table of Contents / Revision Control 2 ATA Connectors 3 ATA Level Shifters 4 High Speed Can Transceivers 5 E2Prom & I2C Connectors 6 Ethernet 10/100 Base-T 7 Flash and Boot ROM 8 GPIO-Page 1 & LEDs 9 GPIO-Page 2 10 GPIO-Page3 11 HW Reset Config Word 12 Core: Functional Signals 13 Core: Power Pins 14 Core: Reset & Clocks, PCI Bus Arbitor 15 PCI-1 16 PCI-2 17 Power Supply Revision History: 18 Reset & Supervisory Circuitry Comment Rev. 19 SDRAM Memory on CS0 First Release X01 02/06/2005 J.H. 20 SDRAM Memory on CS1 Second Release X02 02/28/2005 J.H. 21 SDRAM Termination Third Release X03 03/01/2005 J.H. 22 Switches Pilot Release A 06/20/2005 J.H. 23 MONITOR Uart Post Pilot Update B 07/27/2005 J.H. 24 USB B C Date Owner Freescale Semiconductor General Notes: D C Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA If property Mounted Part Number and Mounted Vendor is shown the part indicated by these properties is mounted on the board and not the one shown in the schematics. The symbols shown in these schematics is used for maximum footprint compatibility only. Lite5200B Evaluation Board Titlepage Author Size J. Hartvigsen 2 3 Rev B A3 Friday, September 02, 2005 1 D 4 Scale 20860 Sheet 5 1 of 24 1 2 3 4 5 A A ATA_5V_DD[0:15] 3 1 5 V LS R177 1.0kohm 2 3 ATA_5V_DMA_Req 3 ATA_5V_IOW 3 ATA_5V_IOR 3 ATA_5V_IOCHDRY 3 ATA_5V_DACK 3 ATA_5V_INT_Req DA0 DA1 DA2 R190 R192 R191 R194 R193 R196 R195 R197 R187 R188 R185 R186 R183 R184 R181 R182 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 17 15 13 11 9 7 5 3 4 6 8 10 12 14 16 18 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 R178 R165 R166 R176 R168 R174 1 1 1 1 1 1 2 2 2 2 2 2 22ohm 22ohm 22ohm 22ohm 22ohm 22ohm 21 23 25 27 29 31 DMARQ DIOW/STOP DIOR/HDMARDY/HSTROBE IORDY/DDMARDY/DSTROBE DMACK GND INTRQ GND GND CS0 GND CS1 GND GND RESET GND ATA_5V_CS0 ATA_5V_CS1 R163 1 R164 1 2 22ohm 2 22ohm 37 38 3 ATA_5V_RESET R206 1 2 22ohm 1 1 3 3 1 35 33 36 R173 1.0kohm 2 DASP PDIAG/CBLID IOCS16 CSEL 39 34 32 28 KEY 20 hfe=100 U30 BSR15_16 @ Ic=10mA B R210 130 D51 Green ATA Vf=2 V @ I=10mA 40-Pin Connector 1 GND GND 2 R179 5.62K C 2 R175 10.0kohm 2.2K 40 30 26 24 22 19 2 R198 10.0kohm C 1 R202 3 ATA_5V_DD7 ATA_5V_DD8 ATA_5V_DD9 ATA_5V_DD10 ATA_5V_DD11 ATA_5V_DD12 ATA_5V_DD13 ATA_5V_DD14 ATA_5V_DD15 2 22ohm 2 22ohm 2 22ohm A B J33 R169 1 R170 1 R167 1 C ATA_5V_DD0 ATA_5V_DD1 ATA_5V_DD2 ATA_5V_DD3 ATA_5V_DD4 ATA_5V_DD5 ATA_5V_DD6 3.3 V 2 ATA_5V_DA0 ATA_5V_DA1 ATA_5V_DA2 ATA Connector 3 3 3 5 V LS ATA GND Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D D Lite5200B Evaluation Board ATA Connector Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 2 of 24 1 2 3 4 5 1 5 V LS 1 3.3 V R154 0ohm ATA Level Shifters R162 0ohm C100 100nF C102 100nF C98 100nF C99 100nF C103 100nF C97 100nF 3.3 V 5 V LS 1 1 C101 100nF R211 0ohm 2 A R205 0ohm GND A 2 C96 100nF 2 2 Place each 0.1uF close to power pin GND C134 100nF 1 R199 1.0kohm 1 2 A7 A6 A5 A4 A3 A2 A1 A0 U35 VCCA 2 22 T/R OE 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 11 12 GND GND VCCB 24 1 ATA_5V_DD[0:15] B0 B1 B2 B3 B4 B5 B6 B7 21 20 19 18 17 16 15 14 GND NC 13 23 2 GND RP7 ATA_5V_DD7 ATA_5V_DD6 ATA_5V_DD5 ATA_5V_DD4 ATA_5V_DD3 ATA_5V_DD2 ATA_5V_DD1 ATA_5V_DD0 1 2 3 4 4x5.6K RP8 1 2 3 4 74LVXC3245 R189 1.0kohm 1 2 A8 A9 A10 A11 A12 A13 A14 A15 VCCA 2 22 T/R OE 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 11 12 VCCB 24 B0 B1 B2 B3 B4 B5 B6 B7 21 20 19 18 17 16 15 14 GND NC 13 23 VCCB 24 B0 B1 B2 B3 B4 B5 B6 B7 21 20 19 18 17 16 15 14 GND NC 13 23 3.3V - 5V Levelshifter 1 8 7 6 5 GND GND T/R OE 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 11 12 GND GND VCCB 24 GND B0 B1 B2 B3 B4 B5 B6 B7 21 20 19 18 17 16 15 14 GND NC 13 23 ATA_5V_RESET 2 74LVXC3245 4x5.6K U24 B 8 7 6 5 VCCA 2 22 3.3V - 5V Levelshifter U25 ATA_Isolation 3.3V - 5V Levelshifter 12 A[0:23] 7,10,12,15,16 C133 100nF GND GND Direction of Level Shifter: TX =================>>>>>>> B GND ATA_5V_DD8 ATA_5V_DD9 ATA_5V_DD10 ATA_5V_DD11 ATA_5V_DD12 ATA_5V_DD13 ATA_5V_DD14 ATA_5V_DD15 18 ATA_3V_RESET 74LVXC3245 U22 1 C 2 A16 A17 A18 11,12 11,12 11,12 11,12 11,12 ATA_DACK_CFG_0 ATA_IOW_CFG_2 ATA_IOR_CFG_1 ATA_CS0 ATA_CS1 VCCA 2 22 T/R OE 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 11 12 3.3V - 5V Levelshifter 1 R171 1.0kohm GND GND ATA_5V_DA0 ATA_5V_DA1 ATA_5V_DA2 ATA_5V_DACK ATA_5V_IOW ATA_5V_IOR ATA_5V_CS0 ATA_5V_CS1 2 2 2 2 2 2 2 2 C 74LVXC3245 Direction of Level Shifter: TX =================>>>>>>> U23 1 2 12 ATA_DMA_Req 12 ATA_IOCHDRY 12 ATA_INT_Req D VCCA 2 22 T/R OE 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 11 12 GND GND VCCB 24 B0 B1 B2 B3 B4 B5 B6 B7 21 20 19 18 17 16 15 14 ATA_5V_DMA_Req 2 ATA_5V_IOCHDRY 2 ATA_5V_INT_Req 2 GND NC 13 23 R172 100.0kohm 3.3V - 5V Levelshifter 1 R180 1.0kohm 1 RP9 1 2 3 4 2 8 7 6 5 Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA 4x100K D GND 74LVXC3245 Direction of Level Shifter: RX <<<<<<================= GND GND GND ATA Level Shifters Author Icc 1.5mA x device EPC: 3mA @ 3.3V Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 3 of 24 1 2 3 3.3 V 4 5 5V C15 100nF C14 100nF CAN1 A GND 5 12 CAN1_HS_RXD 4 RxD 8 INH 1 2 R4 1.0kohm 3 CANH 7 CANL 6 GND 2 4 1 5 9 4 8 3 7 2 6 1 C7 4700pF ZJYS51R5-2P R6 60.4 2 TLE6250 GND TP6 GND GND 11 10 DSUB9M 1 TP5 A J2 L4 VCC TxD GND 1 V33v U5 12 CAN1_HS_TXD C6 100pF R5 60.4 3 GND TP7 TP8 L3 BLM21A C5 1nF 2 C8 100pF B B GND 3.3 V GND GND GND Yosemite uses muRata BLM21AG601SN1 5V C13 100nF C12 100nF CAN2 5 TxD 12 CAN2_HS_RXD 4 RxD 2 1.0kohm 8 INH L2 CANH 7 CANL 6 3 1 C3 4700pF ZJYS51R5-2P TP2 5 9 4 8 3 7 2 6 1 R3 60.4 GND GND GND 11 C 10 DSUB9M 1 TP1 J1 GND 2 4 TLE6250 C C2 100pF R2 60.4 2 1 R1 VCC 1 V33v 12 CAN2_HS_TXD GND U4 GND 3 GND TP3 TP4 L1 BLM21A C1 1nF GND GND 2 C4 100pF GND GND Yosemite uses muRata BLM21AG601SN1 Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D D Lite5200B Evaluation Board High Speed CAN transceivers Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 4 of 24 1 2 3 4 5 A A E2PROM & I2C Connector 3.3 V 1 3.3 V 2 R200 0ohm B Address: 1010000x C117 100nF R203 8.25K R204 8.25K U31 1 2 3 4 A0 A1 A2 VSS E2PROM E2PROM used to save configuration info of the Board as UART Baud Rate, Ethernet MAC Address, IP Address, etc. VDD PTC SCL SDA 8 7 6 5 GND I2C_CLK I2C_IO 12 12 B PCF8582C GND Power Down: 4uA EPC: 600uA @ 3.3V 3.3 V I2C 1 J31 1 2 3 4 CON4-1 GND 3.3 V J29 I2C 2 C 1 2 3 4 CON4-1 C GND Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D D Lite5200B Evaluation Board E2PROM & I2C Connectors Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 5 of 24 2 3 2 3.3 V 1 0ohm C143 10nF Place each 100nF//10nF close to its Power Pin. C146 100nF C141 10nF GND GND GND 27 28 29 30 31 TDI TDO TMS TCK TRST 41 18 GND GND 1 1 2 2 1 R51 0ohm DNP 1 1 2 R24 0ohm DNP CON5 R224 10.0kohm TXSLEW0 TXSLEW1 RESET LXT971 5 6 4 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 12 13 14 15 16 RBIAS PAUSE TEST0 TEST1 17 33 34 35 LED/CFG1 LED/CFG2 LED/CFG3 38 37 36 GND GND 50 61 R28 49.9 GND To notify Pause in 3.3 V Auto Negot. Mode 1 TP14 2 0ohm DNP R25 CFG1 CFG2 CFG3 TP15 G1 G2 22.1kohm 2 R27 1 10.0kohm 2 3.3 V 3.3 V R37 0ohm GND R34 1.0kohm R48 1 1.0kohm 2 GND 25.0000MHz GND 6 RCT YELLOW 4 5 GREEN 7 8 ORANGE 1000pF 2KV 75 OHMRJ-45 PINS SHEILD B R215 0ohm GND R38 0ohm DNP GND GND 3.3 V 3.3 V 3.3 V R7 0ohm R11 130 R36 0ohm R13 130 R223 0ohm R8 0ohm DNP R35 0ohm DNP R49 0ohm DNP C GND GND TP9 R12 0ohm TP13 R31 0ohm TP12 10 D Disabled 100 100 only Enabled Duplex CFG1 CFG2 CFG3 Half Low Low Low Full Low Low High Half Low High Low Full Low High High Half High Low Low Full High Low High Half High High Low High High Half/Full 1 High 2 2 1 2 1 2 C RX R10 0ohm DNP GND GND GND Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D Ethernet 10/100 Base-T Author 10/100 R32 0ohm DNP 2 Speed (Mbps) R9 0ohm DNP 2 CONFIGURATION MODES 1 GND 7,9,14,18 PORRESET 2 The Leds can be reconfigured via SW. Default at boot is: CFG1: Speed CFG2: Link CFG3: Receive D1 Green R26 0ohm Powerdown current 1mA Auto Negot. R50 130 A R212 1.0kohm 1 2 C29 18pF RD- GND 2 C30 18pF 3 C136 10nF 1 GND GND 1CT:1 0810-1X1T-06 R218 10.0kohm 1 2 R33 1 10 9 R30 49.9 2 C R213 1.0kohm 1 2 8 7 TP16 R214 0ohm DNP QZ1 2 2 R217 10.0kohm 2 R219 10.0kohm 1 2 3 4 5 SPEED/TX 10.0kohm 2 LNK REFCLK/XI 3.3 V 1 3.3 V J15 JTAG I/F 3.3 V R52 10.0kohm 2 R220 10.0kohm DNP TP30 1 1 3.3 V TP11 R29 1 5 RD+ 1 N.C.0 N.C.1 N.C.2 TP31 SD/TP 26 6 C19 270pF 2 TD- 2 9 10 44 TP32 24 1 1 MDINT SLEEP PWRDWN ETH_INT TPFIP TPFIN 4 1CT:1 TCT 2 64 32 39 9 3 C20 270pF 23 TD+ 1 MDDIS MDC MDIO COL CRS 1 1 22 ETH_MDC_S 22 ETH_MDIO_S 3 43 42 J6 2 2 62 63 TPFON 20 GND 1 22 ETH_COL_S 22 ETH_CRS_S 19 A C144 100nF 2 RXD0 RXD1 RXD2 RXD3 RX_DV RX_ER RX_CLK TPFOP C145 10nF This Jumper mounts 2010 0 Ohm resistor 1 48 47 46 45 49 53 52 VCCIO VCCIO GND 8 40 7 GND 0ohm GND 2 TXD0 TXD1 TXD2 TXD3 TX_EN TXCLK TX_ER 3.3 V 2 1 ETH_RXD[0]_S ETH_RXD[1]_S ETH_RXD[2]_S ETH_RXD[3]_S ETH_RXDV_S ETH_RXERR_S ETH_RXCLK_S 57 58 59 60 56 55 54 R216 1 22 22 22 22 22 22 9,12 GND GND GND 51 XO ETH_TXD[0]_S ETH_TXD[1]_S ETH_TXD[2]_S ETH_TXD[3]_S ETH_TXEN_S ETH_TXCLK_S ETH_TXERR_S 25 11 VCCD 2 22 22 22 22 22 9,12 22 VCCA VCCA 3.3 V Dual-Speed Fast Ethernet 10-BT / 100-BTX / 100-BFX 21 22 GND 0ohm 1 U7 A C142 100nF 1 C138 10nF 2 C139 10nF ETHERNET 10/100-Base TX C18 100nF 1 C137 100nF L9 0805_Bead 2 C140 100nF 3.3 V 1 C17 10uF R221 2 1 2 + C16 10uF 2 1 + R222 2 L8 0805_Bead 5 1 2 1 B 4 TP10 1 1 3.3 V Size J. Hartvigsen Friday, September 02, 2005 3 Rev A A3 4 Scale 20860 Sheet 5 6 of 24 1 2 3 4 5 3,10,12,15,16 A[0:23] 3.3 V B F2 G2 A5 B4 B5 F7 11,12 CS_0 12 LP_OE 10,11,12 RWB_CFG_3 1 6,9,14,18 PORRESET GND 3.3 V 1 D7 D6 D5 D4 D3 D2 D1 D0 R96 10.0kohm 2 A4 E1 D1 H8 H1 G8 G1 C1 B1 A8 A1 E2 D2 C2 A2 B2 D3 C3 A3 B6 A6 C6 D6 B7 A7 C7 D7 E7 B3 C4 D5 D4 C5 B8 C8 F8 F2 G2 A5 B4 B5 F7 Vcc A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 D8 F1 A0 DQ15/A-1 A1 DQ14 A2 DQ13 A3 DQ12 A4 DQ11 A5 DQ10 A6 DQ9 A7 DQ8 A8 DQ7 A9 DQ6 A10 DQ5 A11 DQ4 A12 DQ3 A13 DQ2 128 M BITS A14 DQ1 (16 M BYTES) A15 DQ0 A16 A17 A18 A19 RY/BY# A20 A21 A22 NC10 (A23exp) NC9 (A24exp) NC8 NC7 CE# NC6 OE# NC5 WE# NC4 WP#/ACC NC3 RESET# NC2 BYTE# NC1 S29GL128N C177 100nF G5 U16 Vio Vio Vcc G5 D8 F1 S29GL128N C35 1uF G7 F6 G6 F5 G4 F4 G3 F3 E6 H6 E5 H5 H4 E4 H3 E3 C158 100nF A C157 1uF GND D7 D6 D5 D4 D3 D2 D1 D0 TP41 A4 E1 D1 H8 H1 G8 G1 C1 B1 A8 A1 B R85 10.0kohm 2 2 R76 10.0kohm G7 F6 G6 F5 G4 F4 G3 F3 E6 H6 E5 H5 H4 E4 H3 E3 C148 100nF 1 Main Flash A0 DQ15/A-1 A1 DQ14 A2 DQ13 A3 DQ12 A4 DQ11 A5 DQ10 A6 DQ9 A7 DQ8 A8 DQ7 A9 DQ6 A10 DQ5 A11 DQ4 A12 DQ3 A13 DQ2 128 M BITS A14 DQ1 (16 M BYTES) A15 DQ0 A16 A17 A18 A19 RY/BY# A20 A21 A22 NC10 (A23exp) NC9 (A24exp) NC8 NC7 CE# NC6 OE# NC5 WE# NC4 WP#/ACC NC3 RESET# NC2 BYTE# NC1 Vss Vss Vss E2 D2 C2 A2 B2 D3 C3 A3 B6 A6 C6 D6 B7 A7 C7 D7 E7 B3 C4 D5 D4 C5 B8 C8 F8 C156 100nF E8 H2 H7 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 Vio Vio U12 Vss Vss Vss A SELECT MAIN FLASH BY SHORTING PINS 2 AND 3 OF J10. 3.3 V A0 E8 H2 H7 A0 GND GND GND CS_1 GND 1 10,11,12 R57 0ohm 3.3 V 2 A0 MAIN 3 FLASH ROM SELECT Jumper 3.3 V GND VCC D CK CLR GND 1 6 PR D VCC GND Q 5 1 Backup Boot Flash 7 F2 G2 A5 2 Q 3 5 B5 F7 3 6 1 NC7SP74 4 7 2 8 U9 U8 8 C36 100nF GND R97 10.0kohm 2 4 NL27WZ08 S29GL032M Vcc D8 F1 G5 Vss B/U 2 A0 DQ15/A-1 A1 DQ14 A2 DQ13 A3 DQ12 A4 DQ11 A5 DQ10 A6 DQ9 A7 DQ8 A8 DQ7 A9 DQ6 A10 DQ5 A11 DQ4 A12 DQ3 A13 DQ2 32 M BITS A14 DQ1 (4 M BYTES) A15 DQ0 A16 A17 RY/BY# A18 A19 A20 NC15 NC14 NC13 NC12 NC11 NC10 CE# NC9 OE# NC8 WE# NC7 NC6 RESET# NC5 BYTE# NC4 NC3 NC2 NC1 Vss J10 1 E2 D2 C2 A2 B2 D3 C3 A3 B6 A6 C6 D6 B7 A7 C7 D7 E7 B3 C4 D5 D4 C GND SELECT BACKUP FLASH BY SHORTING PINS 1 AND 2 OF J10. BACKUP FLASH IS NOT WRITEABLE. D7 D6 D5 D4 D3 D2 D1 D0 A4 FL_RD/BY# H1 G1 E1 D1 C1 B1 A1 B4 C5 H8 G8 F8 C8 B8 A8 Freescale Semiconductor Lite5200B Evaluation Board Author GND 2 D Flash and Boot ROM GND GND 9 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA Size J. Hartvigsen 1 10,12,15,16 C186 100nF G7 F6 G6 F5 G4 F4 G3 F3 E6 H6 E5 H5 H4 E4 H3 E3 H2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 VIO VIO U19 R47 10.0kohm Vss 2 10K E8 1 R58 2 R59 10.0kohm C D[0:7] 3.3 V H7 3.3 V 1 3.3 V 3 Rev A A3 Friday, September 02, 2005 4 Scale 20860 Sheet 5 7 of 24 1 2 3 4 GPIOs Page #1: USB & TIMER PORT A 12 Timer_2 12 Timer_6 12 Timer_4 12 Timer_3 5 3.3 V D55 BAT54S 2 3.3 V 2 D63 BAT54S D13 BAT54S 2 USB1_OE 3 3 1 USB1_TXN 1 Timer_5 3 3.3 V 3.3 V A 1 R68 0ohm 1 2 R67 0ohm DNP 2 1 J17 R66 1 3 5 7 9 11 13 15 17 19 12 Timer_5 12 Timer_7 12,22 USB1_OE 11,12,22 USB1_TXP 12,22 USB1_RXP 12,22 USB1_PORTPWR 12,22 USB1_SUSPEND 2 4 6 8 10 12 14 16 18 20 0ohm DNP 1 2 R65 1 0ohm 2 D15 BAT54S 2 2 D22 BAT54S D57 BAT54S 2 USB1_TXP 3 3 1 USB1_RXD 1 Timer_6 3 1 B2B 20 USB & TIMER Port D54 BAT54S 2 12,22 USB1_OVRCURRENT 12,22 USB1_SPEED 12,22 USB1_RXN 12,22 USB1_RXD 11,12,22 USB1_TXN 2 D23 BAT54S D12 BAT54S 2 USB1_RXP 3 3 1 USB1_RXN 1 Timer_7 3 1 B 3.3 V D14 BAT54S 2 GND 3 C56 100nF HEX Inverter (Tpd max=3.9 ns) A0 A1 A2 A3 A4 A5 GND VCC Y0 Y1 Y2 Y3 Y4 Y5 3 B USB1_SPEED 1 3.3 V GND 10,12 IR_USB_CLK 10,12 IR_RX 10,12 IR_TX 10,12 IRDA_RX USB1_PORTPWR 1 U18 1 3 5 9 11 13 7 D56 BAT54S 2 2 14 2 4 6 8 10 12 D66 BAT54S D53 BAT54S Timer_2 3 1 2 3 USB1_SUSPEND 3 1 74LVT04 GND 2 D11 BAT54S 2 USB1_OVRCURRENT 1 D64 BAT54S Timer_3 3 GND 1 C GND C Ethernet Port Protecting Diodes (ETH1) R243 130 6 LEDs to allow visual 'Help' during SW Debug R242 130 R241 130 R240 130 R22 130 R23 130 LED4 TMR3 GND GND GND GND GND GND D65 BAT54S 3 1 TMR2 C LED3 D3 Green C Red A A D2 Red C LED2 D37 Red C LED1 D38 C Green A D39 Green A A D40 C A 2 Timer_4 Timer Port Protection Diodes GND These Schottky Diodes give ONLY a limited protection against short circuits. Max Contunous Forward Current 200mA Max repetitive peak forward current 300mA Max non-repetitive peak forward current 600mA Max total power dissipation (per package) 230mW MAx diode capacitance 10pF Max. Reverse Current 2uA Vf @ 0.1mA 240mV Vf @ 100mA 800mV 3.3 V ID Single-Wire CHIP R95 3.65K DNP D Gnd 2 Data R94 10,12 1 ID_CHIP Freescale Semiconductor U14 1 2 0ohm DNP NC4 NC3 NC2 NC1 ID DS2401 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA 6 5 4 3 D Lite5200B Evaluation Board DNP GPIO-PAGE1 & LEDs SINGLE WIRE ID CHIP Author Size J. Hartvigsen GND 1 Friday, September 02, 2005 2 3 Rev A A3 4 Scale 20860 Sheet 5 8 of 24 1 2 3 4 5 3.3 V GPIOs Page #2: ETHERNET & CS/IRQ/PSC2 PORT External Int. Req. Protecxting Diodes D82 BAT54S 2 A D79 BAT54S 2 IRQ_1 3 IRQ_2 3 1 Ethernet Port Protecting Diodes (ETH0) 3 1 2 D33 BAT54S 2 IRQ_3 2 1 D68 BAT54S D20 BAT54S D32 BAT54S 3 1 2 B 2 PSC2_2 2 PSC2_3 3 1 D31 BAT54S 3 ETH_RXD[1] 3 3 2 IRQ_0 R55 0ohm DNP 0ohm DNP 2 R232 0ohm 2 R93 1 1 1 R245 10.0kohm 1 2 IRQ_2 12 D69 BAT54S 2 R244 10.0kohm 1 2 ETH_RXDV 3 ETH_TXD[1] 1 0ohm DNP 2 Ethernet Port Protecting Diodes (ETH1) GND C J16 1 3 5 7 9 11 13 15 17 19 ETH_MDIO ETH_RXD[1] ETH_RXD[2] ETH_RXD[3] ETH_RXERR 2 4 6 8 10 12 14 16 18 20 ETH_CRS ETH_TXEN ETH_TXD[0] ETH_RXDV 12,22 11,12,22 11,12,22 12,22 ETH_RXCLK ETH_COL ETH_TXCLK ETH_RXD[0] ETH_TXD[1] 6,12 12,22 6,12 12,22 11,12,22 B2B 20 R46 0ohm 2 R92 1 12 R226 0ohm DNP 2 2 IRQ_1 D5 BAT54S 2 Ethernet Port 1 1 3.3 V R45 0ohm GND 12,22 12,22 12,22 12,22 12,22 FL_RD/BY# 1 3.3 V B ETH_RXD[0] ETH_RXD[3] Ethernet Pins driving capacity is limited by the Schottky Diodes and by the Connector Capcitance. Assuming a Connector pin with 10pF then max freq. on a single line is 50 MHz I pin = 5mA Cpin 10pF Cswitch 10 pF 11,12,22 ETH_TXD[2] C Schottky 10 pF 11,12,22 ETH_TXD[3] 11,12,22 ETH_TXERR 11,12,22 ETH_MDC 3.3 V 7 0ohm DNP 2 3 1 D58 BAT54S GND ETH_INT 12 15,16 PCI_INTB R91 1 ETH_TXD[0] PCI_INTC 6 2 1 R56 0ohm INSTALL OR REMOVE 0 OHM RESISTORS TO SELECT INTERRUPT SOURCES ETH_TXCLK D60 BAT54S 2 1 ETH_RXD[2] 3 15,16 PCI_INTD R225 10.0kohm 1 2 D18 BAT54S 2 PSC2_4 2 R121 0ohm DNP 1 2 3 1 1 3 15,16 3.3 V 10.0kohm 2 ETH_TXEN ETH_MDIO 1 GND ETH_COL D7 BAT54S 2 1 15,16 PCI_INTA R233 1 D70 BAT54S D59 BAT54S 1 C 3 A 1 3 GND 3 ETH_CRS 1 2 D9 BAT54S D61 BAT54S 2 1 D10 BAT54S 3 1 2 ETH_TXD[3] 2 1 1 D19 BAT54S ETH_MDC 3 3 D80 BAT54S 2 PSC2_1 ETH_RXCLK 1 3 1 3 1 2 1 PSC2_0 3 D81 BAT54S 2 2 D41 BAT54S 2 ETH_RXERR 1 ETH_TXERR 3 GND D8 BAT54S 2 ETH_TXD[2] 3 2 D67 BAT54S 3 D21 BAT54S 1 3 1 3.3 V D6 BAT54S 2 3.3 V 3.3 V 3.3 V IRQ_3 12 Freescale Semiconductor J20 CON_IRQ0 CON_IRQ1 D CON_IRQ2 CON_IRQ3 6,7,14,18 PORRESET 14 HRESET 15 PCI_CLK_3 1 3 5 7 9 11 13 15 17 19 3.3 V 2 4 6 8 10 12 14 16 18 20 PSC2_0 PSC2_1 PSC2_2 PSC2_3 PSC2_4 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA 5V 12 12 12 12 12 Lite5200B Evaluation Board GPIO-PAGE 2 Author Size J. Hartvigsen B2B 20 2 3 Rev A A3 Friday, September 02, 2005 1 D 4 Scale 20860 Sheet 5 9 of 24 1 2 3 4 5 GPIOs Page #3: PSC3/IrDA/GPIO PORT & Local PLUS A A 3.3 V 3.3 V PSC3/IrDA & GPIO (all Protected) J21 12 12 12 12 12 12 12 12 12 12 PSC3_0 PSC3_1 PSC3_2 PSC3_3 PSC3_4 PSC3_5 PSC3_6 PSC3_7 PSC3_8 PSC3_9 1 3 5 7 9 11 13 15 17 19 2 2 4 6 8 10 12 14 16 18 20 IR_USB_CLK IR_RX IR_TX IRDA_RX 8,12 8,12 8,12 8,12 ID_CHIP 8,12 IrDA & GPIO Protecting Diodes 3.3 V 2 3 2 B2B 20 D78 BAT54S B 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2 D77 BAT54S A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 1 3 5 7 9 11 13 15 17 19 7,12,15,16 7,12,15,16 7,12,15,16 7,12,15,16 7,12,15,16 7,12,15,16 7,12,15,16 7,12,15,16 7,12,15,16 7,12,15,16 A20 A21 A22 A23 D0 D1 D2 D3 D4 D5 1 3 5 7 9 11 13 15 17 19 7,12,15,16 D6 7,12,15,16 D7 11,12 CS_2 11,12 CS_3 7,11,12 RWB_CFG_3 11,12 ALE_CFG_4 11,12 TS_CFG_5 12 ACK 7,11,12 CS_1 1 3 5 7 9 11 13 15 17 19 PSC3_1 3 B 2 D27 BAT54S D36 BAT54S 2 PSC3_2 D72 BAT54S PSC3_7 3 1 1 ID_CHIP 1 2 D75 BAT54S 2 PSC3_3 3 D28 BAT54S PSC3_8 3 1 GND PSC3_6 3 IR_TX IRDA_RX 3 2 4 6 8 10 12 14 16 18 20 D29 BAT54S 1 3 2 2 1 3 B2B 20 J18 C D76 BAT54S 1 1 B2B 20 J22 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 3,7,12,15,16 7,12,15,16 2 D34 BAT54S 3 Local PLUS & Control Signals J23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PSC3_5 1 IR_USB_CLK IR_RX 2 GND D74 BAT54S 3 1 1 3 1 2 PSC3_0 3 D43 BAT54S 3.3 V D44 BAT54S 1 GND 2 4 6 8 10 12 14 16 18 20 2 D35 BAT54S 2 PSC3_4 3 D71 BAT54S PSC3_9 3 1 C 1 B2B 20 J19 2 4 6 8 10 12 14 16 18 20 PSC3 Port Protecting Diodes (ETH1) GND GND B2B 20 Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA GND D Local Plus Bus signals are NOT Protected with Diodes to allow max frequency switching (66mHz) D Lite5200B Evaluation Board GPIO-PAGE 3 Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 10 of 24 1 Config SW 2 3 4 5200B Package Ball 5200B Pin Name CDM Reset Configuration Register Bit 5200B Configuration Signal from CDM Description Y18 Y17 W17 W16 V14 ATA_DACK ATA_IOR ATA_IOW LP_RW LP_ALE PORCFG[31] PORCFG[30] PORCFG[29] PORCFG[28] PORCFG[27] ppc_pll_cfg_4 ppc_pll_cfg_3 ppc_pll_cfg_2 ppc_pll_cfg_1 ppc_pll_cfg_0 5200B PPC Core PLL Configuration SW1-1 Y13 LP_TS PORCFG[26] xlb_clk_sel bit = 0: XLB_CLK = fsystem/4 bit = 1: XLB_CLK = fsystem/8 SW1-2 H02 USB_1 PORCFG[25] sys_pll_cfg_0 bit =0 : SYS_PLL FVCO = 16x SYS_XTAL_IN Frequency bit =1 : SYS_PLL FVCO = 12x SYS_XTAL_IN Frequency SW1-3 H03 USB_2 PORCFG[24] sys_pll_cfg_1 bit = 0: Fvco = 12x or 16x sys_xtal_in (default) bit = 1: Fvco = 24x or 32x sys_xtal_in SW1-4 K01 ETH_0 PORCFG[23] boot_rom_mg bit = 0: Most Graphics boot not enabled bit = 1: Most Graphics boot enabled. SW1-5 K02 ETH_1 PORCFG[16] boot_rom_lf bit = 0: Large Flash boot not enabled bit = 1: Large Flash boot enabled. SW1-6 K03 ETH_2 PORCFG[21] ppc_msrip PPC Boot Address / Exception Table Location bit = 0: 0000 0100 (hex) bit = 1: FFF0 0100 (hex) SW1-7 J01 ETH_3 PORCFG[20] boot_rom_wait bit = 0: 4 PCI clocks of wait state* bit = 1: 48 PCI clocks of wait state* SW1-8 J02 ETH_4 PORCFG[19] boot_rom_swap bit = 0: no byte lane swap - same endian ROM image bit = 1: byte lane swap - different endian ROM image SW1-9 L03 ETH_5 PORCFG[18] boot_rom_size For non-muxed boot ROMs: bit = 0: 8-bit boot ROM data bus 24-bit max boot ROM address bit = 1: 16-bit boot ROM data bus 16-bit boot ROM address For muxed boot ROMs boot ROM - addr is max 25 significant bits during address tenure. bit = 0: 16-bit ROM data bus bit = 1: 32-bit ROM data bus For "large flash" boot case boot Flash addr is 25 bits. bit = 0: 8-bit Flash data bus bit = 1: 16-bit Flash data bus SW3-1 SW3-2 SW3-3 SW3-4 SW3-5 A B ETH_6 N02 SW1-10 PORCFG[17] boot_rom_type 3.3 V High Low SWITCH LABEL Pull-Ups to insure known state at RESET TP35 TP36 TP37 TP38 RP3 1 2 3 4 8 7 6 5 CS_0 CS_1 CS_2 CS_3 7,12 7,10,12 10,12 10,12 R300 1 2 10.0kohm B1 3,12 ATA_IOR_CFG_1 R301 1 2 10.0kohm B2 3,12 ATA_IOW_CFG_2 R302 1 2 10.0kohm B3 R98 1 2 10.0kohm B4 R303 1 2 10.0kohm B5 10,12 ALE_CFG_4 4x47K TP44 TP45 C SW3 3,12 ATA_DACK_CFG_0 7,10,12 RWB_CFG_3 TP42 TP43 8 7 6 5 ATA_CS0 ATA_CS1 4x47K B A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 DEFAULT SWITCH SETTING H L H L CFG 4 CFG 3 CFG 2 CFG 1 CFG 0 Jumper Switch 5 RP5 1 2 3 4 A bit = 0: non-muxed boot ROM bus, single tenure transfer. bit = 1: muxed boot ROM bus, with address & data tenures, ALE_b & TS_b active. BOOT CONFIGURATION SETTING 3.3 V 5 3,12 3,12 C SW1 10,12 TS_CFG_5 R228 1 2 10.0kohm B1 8,12,22 USB1_TXN R229 1 2 10.0kohm B2 8,12,22 USB1_TXP R230 1 2 10.0kohm B3 9,12,22 ETH_TXEN R231 1 2 10.0kohm B4 9,12,22 ETH_TXD[0] R235 1 2 10.0kohm B5 9,12,22 ETH_TXD[1] R236 1 2 10.0kohm B6 9,12,22 ETH_TXD[2] R237 1 2 10.0kohm B7 9,12,22 ETH_TXD[3] R238 1 2 10.0kohm B8 9,12,22 ETH_TXERR R239 1 2 10.0kohm B9 9,12,22 ETH_MDC R246 1 2 10.0kohm B10 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 XLB SYS FVCO MG LF HI/LO WAIT SWAP WIDE MUXED Freescale Semiconductor Jumper Switch 10 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D D Lite5200B Evaluation Board HW Reset Config Word Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 11 of 24 1 2 3 4 5 21 A IRQ0 IRQ1 IRQ2 IRQ3 G19 G20 F20 B19 A19 B18 A18 V13 W13 V12 Y12 V11 W12 U11 Y11 A0 A1 A2 A3 A4 A5 A6 A7 EXT_AD_8 EXT_AD_9 EXT_AD_10 EXT_AD_11 EXT_AD_12 EXT_AD_13 EXT_AD_14 EXT_AD_15 W11 V10 Y10 V9 Y9 V8 W9 U8 A8 A9 A10 A11 A12 A13 A14 A15 EXT_AD_16 EXT_AD_17 EXT_AD_18 EXT_AD_19 EXT_AD_20 EXT_AD_21 EXT_AD_22 EXT_AD_23 W4 Y5 V4 Y4 V2 Y3 V3 W3 A16 A17 A18 A19 A20 A21 A22 A23 EXT_AD_24 EXT_AD_25 EXT_AD_26 EXT_AD_27 EXT_AD_28 EXT_AD_29 EXT_AD_30 EXT_AD_31 U3 W2 T2 Y1 T3 W1 R3 V1 D0 D1 D2 D3 D4 D5 D6 D7 GPIO (2) [SDRM CS1] [TSIZE_1] TEST_SEL_1 D[0:7] R86 10.0kohm LP_OE 7 TS_CFG_5 ATA_DACK ATA_INTRQ Y16 V17 W17 Y17 W18 Y18 Y19 ATA_Isolation 3 ATA_DMA_Req 3 ATA_IOW_CFG_2 3,11 ATA_IOR_CFG_1 3,11 ATA_IOCHDRY 3 ATA_DACK_CFG_0 3,11 ATA_INT_Req 3 I2C_1 I2C_0 I2C_3 I2C_2 W19 V19 W20 V20 CAN1_HS_RXD CAN1_HS_TXD I2C_IO I2C_CLK LP_OE LP_TS LP_ACK LP_ALE LP_R/W I2C (4) [CAN 1] [ATA CS] 7,10,15,16 3.3 V D8 Y13 U14 V14 W16 ATA Bus dedicated ATA_ISOLATION ATA_DRQ Signals (7) ATA_IOW [MOST ATA_IOR Graphics A16-A22] ATA_IOCHDRY [TSIZE_2] B 10,11 RWB_CFG_3 7,10,11 ACK 10 ALE_CFG_4 R87 10,11 C 33.2 4 4 5 5 R88 0ohm R81 10.0kohm Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA 2 21 uP_SDRAM_CS1 8,10 ID_CHIP IR_USB_CLK IR_RX IR_TX IRDA_RX 8,10 8,10 8,10 8,10 PSC3_0 PSC3_1 PSC3_2 PSC3_3 PSC3_4 PSC3_5 PSC3_6 PSC3_7 PSC3_8 PSC3_9 2 10 10 10 10 10 10 10 10 10 10 PSC2_0 PSC2_1 PSC2_2 PSC2_3 PSC2_4 9 9 9 9 9 TX0 RX0 RTS0 CTS0 ATA_SW_RESET GND D Lite5200B Evaluation Board CORE: Functional Signals Author Size J. Hartvigsen Rev A A3 1 D 23 23 23 23 18 15,16 PCI_Bus_Grant PCI_Reset 14 15 PCI_Clock 15 PCI_Init_Dev_Sel 14 PCI_Bus_Req 15,16 PCI_C/B_En3 15,16 PCI_C/B_En2 15,16 PCI_C/B_En1 15,16 PCI_C/B_En0 14,15,16 PCI_Frame 14,15,16 PCI_Target_ready 15,16 PCI_Trans_Stop 15,16 PCI_Initiator_ready PCI_Parity 14,15,16 15,16 PCI_Device_Select 15,16 PCI_Parity_Error 15,16 PCI_System_Error 1 C3 IR/IrDA (4) [IR Blaster] [IR Remote] [IrDA] [UART 6] [CODEC 6] PSC3 (10) [UART 5] [USB 2] [CODEC 5] [SPI FULL] [SPI SC] [CS6, CS7] [GPIO] PSC2 (5) [UART 3] [AC 97] [CAN 1] [CAN 2] [CODEC 3] [GPIO] GPIO_WKUP_6 GPIO_WKUP_7 PSC1 (5) [UART 1] [AC 97] [CODEC 1] [GPIO] C15 C12 SIU (12) [CS0-5 and IRQ 0-3] [ATA CS] PCI dedicated Signals (17) [MOST Graphics A0-A15] [Large Flash A16-A25] GND EXT_AD_0 EXT_AD_1 EXT_AD_2 EXT_AD_3 EXT_AD_4 EXT_AD_5 EXT_AD_6 EXT_AD_7 Local Plus Bus dedicated Signals (4) [MOST Graphics A23] 3,7,10,15,16 2 MEM_CLK MEM_CLK MEM_CLK_EN MEM_CAS MEM_WE MEM_CS_0 MEM_RAS MEM_MBA_1 MEM_MBA_0 A17 C18 F19 E20 B17 E19 D20 D19 C20 C19 B20 C16 B16 A16 C17 MEM_MA_12 MEM_MA_11 MEM_MA_10 MEM_MA_9 MEM_MA_8 MEM_MA_7 MEM_MA_6 MEM_MA_5 MEM_MA_4 MEM_MA_3 MEM_MA_2 MEM_MA_1 MEM_MA_0 MEM_MDQS_3 MEM_MDQS_2 MEM_MDQS_1 MEM_MDQS_0 ETHERNET 18-Wire (18) [USB 2] [ETHERNET 7 Wire] [UART 2] [UART 4] [J1850] [GPIO] PSC6_3 PSC6_0 PSC6_2 PSC6_1 LP_CS0 LP_CS1 LP_CS2 LP_CS3 LP_CS4 LP_CS5 MPC5200B C13 B12 A12 C11 W14 Y14 V15 W15 Y15 V16 A[0:23] 1 P3 P1 P2 R1 R437 10.0kohm 2 ETH_0 ETH_1 ETH_2 ETH_3 ETH_4 ETH_5 ETH_6 ETH_7 ETH_8 ETH_9 ETH_10 ETH_11 ETH_12 ETH_13 ETH_14 ETH_15 ETH_16 ETH_17 R4 R2 T1 U2 U1 Y2 W6 Y8 W10 V5 W5 V6 Y6 V7 W7 Y7 W8 7,11 CS_0 7,10,11 CS_1 10,11 CS_2 10,11 CS_3 3,11 ATA_CS0 3,11 ATA_CS1 K1 K2 K3 J1 J2 L3 N2 N1 M3 L1 J3 L4 M2 M1 N4 N3 L2 J4 External Muxed Address/Data Bus EXT_AD_0 is LS-bit (32) [ATA D0-D15, A0-A3] [PCI AD0-AD31] [MOST Graphics D0-D31] [Large Flash A0-A15, D0-D16] PSC3_0 PSC3_1 PSC3_2 PSC3_3 PSC3_4 PSC3_5 PSC3_6 PSC3_7 PSC3_8 PSC3_9 IRQ_0 IRQ_1 IRQ_2 IRQ_3 USB 1 (10) [UART 2] [UART 4] [GPIO] C7 B7 A7 C6 B6 A6 C5 B5 A5 C4 9 9 9 9 USB_0 USB_1 USB_2 USB_3 USB_4 USB_5 USB_6 USB_7 USB_8 USB_9 PSC2_0 PSC2_1 PSC2_2 PSC2_3 PSC2_4 C ETH_TXEN ETH_TXD[0] ETH_TXD[1] ETH_TXD[2] ETH_TXD[3] ETH_TXERR ETH_MDC ETH_MDIO ETH_RXDV ETH_RXCLK ETH_COL ETH_TXCLK ETH_RXD[0] ETH_RXD[1] ETH_RXD[2] ETH_RXD[3] ETH_RXERR ETH_CRS H1 H2 H3 G1 G2 G3 G4 F1 F2 F3 SDRAM/DDR Memory Control Bus (30) [Little Endian for Address] C9 B9 A9 B8 A8 9,11,22 9,11,22 9,11,22 9,11,22 9,11,22 9,11,22 9,11,22 9,22 9,22 6,9 9,22 6,9 9,22 9,22 9,22 9,22 9,22 9,22 TIMER PORT (8) [CAN 2] [SPI FULL] [ATA CS] [GPIO] SDRAM/DDR Memory Data Bus (32) [Little Endian] PSC1_0 PSC1_1 PSC1_2 PSC1_3 PSC1_4 8,22 USB1_OE 8,11,22 USB1_TXN 8,11,22 USB1_TXP 8,22 USB1_RXD 8,22 USB1_RXP 8,22 USB1_RXN 8,22 USB1_PORTPWR 8,22 USB1_SPEED 8,22 USB1_SUSPEND 8,22 USB1_OVRCURRENT TIMER_0 TIMER_1 TIMER_2 TIMER_3 TIMER_4 TIMER_5 TIMER_6 TIMER_7 B11 A11 C10 B10 A10 Y20 V18 D3 D2 D1 E3 E2 E1 PCI_GNT PCI_RESET PCI_CLOCK PCI_IDSEL PCI_REQ PCI_CBE_3 PCI_CBE_2 PCI_CBE_1 PCI_CBE_0 PCI_FRAME PCI_TRDY PCI_STOP PCI_IRDY PCI_PAR PCI_DEVSEL PCI_PERR PCI_SERR B 4 CAN2_HS_TXD 4 CAN2_HS_RXD 8 Timer_2 8 Timer_3 8 Timer_4 8 Timer_5 8 Timer_6 8 Timer_7 MEM_DQM_3 MEM_DQM_2 MEM_DQM_1 MEM_DQM_0 MEM_MDQ_31 MEM_MDQ_30 MEM_MDQ_29 MEM_MDQ_28 MEM_MDQ_27 MEM_MDQ_26 MEM_MDQ_25 MEM_MDQ_24 MEM_MDQ_23 MEM_MDQ_22 MEM_MDQ_21 MEM_MDQ_20 MEM_MDQ_19 MEM_MDQ_18 MEM_MDQ_17 MEM_MDQ_16 MEM_MDQ_15 MEM_MDQ_14 MEM_MDQ_13 MEM_MDQ_12 MEM_MDQ_11 MEM_MDQ_10 MEM_MDQ_9 MEM_MDQ_8 MEM_MDQ_7 MEM_MDQ_6 MEM_MDQ_5 MEM_MDQ_4 MEM_MDQ_3 MEM_MDQ_2 MEM_MDQ_1 MEM_MDQ_0 U17A U18 T18 R18 R17 P18 N18 N17 M18 K18 J17 J18 H18 G18 G17 F18 E18 M20 M19 L20 L19 K20 K19 J20 J19 P19 P20 R19 R20 T19 T20 U19 U20 1 21 21 21 21 21 21 21 21 21 uP_SDRAM_BA_1 uP_SDRAM_BA_0 uP_SDRAM_CLK uP_SDRAM_CLK_b uP_SDRAM_CLKEN uP_SDRAM_CAS uP_SDRAM_WE uP_SDRAM_CS0 uP_SDRAM_RAS uP_SDRAM_ADD12 uP_SDRAM_ADD11 uP_SDRAM_ADD10 uP_SDRAM_ADD9 uP_SDRAM_ADD8 uP_SDRAM_ADD7 uP_SDRAM_ADD6 uP_SDRAM_ADD5 uP_SDRAM_ADD4 uP_SDRAM_ADD3 uP_SDRAM_ADD2 uP_SDRAM_ADD1 uP_SDRAM_ADD0 uP_SDRAM_DS_3 uP_SDRAM_DS_2 uP_SDRAM_DS_1 uP_SDRAM_DS_0 L18 D18 H20 N20 uP_SDRAM_D31 uP_SDRAM_D30 uP_SDRAM_D29 uP_SDRAM_D28 uP_SDRAM_D27 uP_SDRAM_D26 uP_SDRAM_D25 uP_SDRAM_D24 uP_SDRAM_D23 uP_SDRAM_D22 uP_SDRAM_D21 uP_SDRAM_D20 uP_SDRAM_D19 uP_SDRAM_D18 uP_SDRAM_D17 uP_SDRAM_D16 uP_SDRAM_D15 uP_SDRAM_D14 uP_SDRAM_D13 uP_SDRAM_D12 uP_SDRAM_D11 uP_SDRAM_D10 uP_SDRAM_D9 uP_SDRAM_D8 uP_SDRAM_D7 uP_SDRAM_D6 uP_SDRAM_D5 uP_SDRAM_D4 uP_SDRAM_D3 uP_SDRAM_D2 uP_SDRAM_D1 uP_SDRAM_D0 21 uP_SDRAM_D[0:31] A 21 21 21 21 uP_SDRAM_DM_3 uP_SDRAM_DM_2 uP_SDRAM_DM_1 uP_SDRAM_DM_0 L17 A20 H19 N19 21 21 21 21 uP_SDRAM_ADD[0:12] PWR_DN_CTL_STS 17 1 2 3 Friday, September 02, 2005 4 Scale 20860 Sheet 5 12 of 24 1 2 3 4 5 CORE POWER SECTION 3.3 V C37 47uF DNP C173 100nF C162 100nF C150 100nF C151 100nF C169 100nF C172 100nF C170 100nF C185 100nF C175 100nF C155 100nF C160 100nF C163 100nF + GND A A 2.5V for DDR SDRAM 2.5 V C181 100nF 1.5 V U16 U13 U10 U9 U6 U5 T4 H4 F4 E4 D9 D6 C183 100nF C154 100nF VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO U17B C178 100nF C174 100nF B B D12 D13 D15 D17 E17 F17 H17 K17 M17 P17 T17 C168 100nF C180 100nF VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO I/O Power 3.3 V (12) C164 100nF Memory Power 2.5V/3.3V (11) MPC5200 C61 100nF C184 100nF B14 C14 CORE_PLL_AVDD PLL's SYS_PLL_AVDD SYS_PLL_AVSS C152 100nF C176 100nF C161 100nF C153 100nF C171 100nF D4 D16 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 U4 U17 C166 100nF C C165 100nF Core and I/O GND (20) Power and GND (3) C182 100nF U15 U12 U7 P4 M4 K4 D11 D10 D7 D5 VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE C8 VDD_CORE VDD_CORE VDD_CORE VDD_CORE Core Power VDD_CORE VDD_CORE 1.5V (10) VDD_CORE VDD_CORE VDD_CORE VDD_CORE C C149 100nF + C179 100nF GND C167 100nF + 1.5 V C62 47uF DNP R82 10 1.5 V R247 10 TP39 TP34 C159 470pF TP40 C55 47uF DNP GND C54 10uF GND C53 470pF Freescale Semiconductor R90 10 C50 10uF Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D GND Lite5200B Evaluation Board GND CORE: Power Pins Author Size J. Hartvigsen 2 3 Rev A A3 Friday, September 02, 2005 1 D 4 Scale 20860 Sheet 5 13 of 24 1 2 3 4 5 3.3 V 3.3 V 2 1 3.3 V 1 D17 BAT54S 2 D73 BAT54S 2 2 3.3 V 3.3 V R227 10.0kohm 2 HRESET A D16 BAT54S 2 D24 BAT54S 3COP_TRST CN1 COP_TDO COP_TDI 2 2 R83 10.0kohm 3 1 R69 10.0kohm 1 1 3.3 V R54 10.0kohm 2 R53 10.0kohm 1 1 3 COP_TDO A COP_TCK COP_TMS SRESET HRESET CHKSTPO 1 3 5 7 9 11 13 15 3 COP_TCK 1 2 4 6 8 10 12 14 16 COP_TRST 1 18 2 CON COP D52 BAT54S 3 GND 2 D25 BAT54S SRESET 3 COP_TDI 1 1 B B R84 2.2K R77 10Mohm 2 TP46 SYS_XTAL_IN SYS_XTAL_OUT A2 B3 A3 A4 B4 3 JTAG_TDO JTAG_TRST JTAG_TDI JTAG_TMS JTAG_TCK R234 130 JTAG_TRST 1 R80 10.0kohm R116 0ohm C49 22pF QZ3 22pF GND 1 GND GND D30 Green 1 2 32.768KHz 18 3 CHKSTPO 1 C59 33pF GND C60 33pF 33.0000MHz GND R79 10.0kohm GND GND GND C 2 C48 SYS_PLL_TPA A15 D14 B1 2 1 C B15 TEST_SEL_0 3 COP_TMS C R78 332kohm QZ2 MPC5200 RTC_XTAL_IN RTC_XTAL_OUT 2 D26 BAT54S A C2 C1 1 1 2 1.0kohm 2 R89 A1 B2 D62 BAT54S 1 1 TEST_MODE_1 TEST_MODE_0 2 9 HRESET 6,7,9,18 PORRESET SRESET HRESET PORRESET 2 U15 BSR15_16 1 U17C A14 B13 A13 2 3.3 V 3.3 V GND TP69 TP70 TP66 TP71 U38 9 12 15 16 12,15,16 12,15,16 12,15,16 PCI_Reset PCI_Bus_Grant PCI_Bus_Req_0 PCI_Bus_Req_1 PCI_Frame PCI_Initiator_Ready PCI_Target_Ready D JP2 GND HDR_8X1 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 30 I/CLK 29 4 13 21 TCK TMS TDI TDO TP67 TP68 TP72 TP73 TP63 TP64 TP65 8 7 6 5 4 3 2 1 15 PCI_CLK_4 31 32 1 2 3 6 7 8 9 10 14 28 27 5 IOQ1 IOQ2 IOQ3 IOQ4 IOQ5 IOQ6 IOQ7 IOQ8 IOQ9 IOQ10 26 25 24 23 22 19 18 17 16 15 GNDO GNDO GND TAB 20 12 11 33 PCI_Bus_Grant_0 PCI_Bus_Grant_1 DualRequest FF_Reset REMOVE OR CUT PIN 5 AS KEY Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA PCI_Bus_Req NextGrant D 12 Lite5200B Evaluation Board CORE: Reset and Clocks Author Size J. Hartvigsen GND 2 15 16 Last_Grant FF_Set ISPGAL22V10AV JTAG I/F FOR PROGRAMMING PAL 1 VCC VCCO VCCO Friday, September 02, 2005 3 Rev A A3 4 Scale 20860 Sheet 5 14 of 24 1 2 3 4 5 3,7,10,12,16 A[0:23] 5V 3.3 V C66 47nF C31 47nF C93 47nF C23 47nF C92 47nF C24 47nF C57 47nF C32 47nF C41 47nF C42 47nF C67 47nF C65 47nF Put these capacitors as close as possible to the Power Pins of the connector. C25 47nF 9,16 9,16 TP28 PCI_INTB PCI_INTD 14 PCI_Bus_Req_0 D7 D5 B D3 D1 12,16 PCI_C/B_En3 A23 A21 A19 A17 12,16 PCI_C/B_En2 12,14,16 PCI_Initiator_Ready 12,16 PCI_Device_Select 12,16 PCI_Parity_Error 12,16 PCI_System_Error 12,16 PCI_C/B_En1 A14 A12 A10 C 16 C51 47nF A RP2 4x5.6K 1 2 3 4 -12 V TP27 8 7 6 5 GND 1 2 3 4 RP1 4x5.6K 1 2 3 4 RP4 4x5.6K M66EN A8 A7 A5 A3 A1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 -12V TCK GND TDO +5V +5V INTB INTD PRSNT1 Reserved1 PRSNT2 TRST +12V TMS TDI +5V INTA INTC +5V Reserved6 +3.3V (I/O) Reserved5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 Reserved2 GND CLK GND REQ 3.3V (I/O) AD31 AD29 GND AD27 AD25 +3.3V C/BE3 AD23 GND AD21 AD19 +3.3V AD17 C/BE2 GND IRDY +3.3V DEVSEL GND LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 GND AD12 AD10 M66EN GND GND AD08 AD07 +3.3V AD05 AD03 GND AD01 +3.3V (I/O) ACK64 +5V +5V +3.3V (AUX) RST +3.3V (I/O) GNT GND PME AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME GND TRDY GND STOP +3.3V Reserved4 Reserved3 GND PAR AD15 +3.3V AD13 AD11 GND AD09 GND GND C/BE0 +3.3V AD06 AD04 GND AD02 AD00 +3.3V (I/O) REQ64 +5V +5V A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 PCI 32 Bit / 3.3V GND +12 V GND J13 PCI Connector 32 Bit / 3.3V A 3.3 V 8 7 6 5 8 7 6 5 7,10,12,16 D[0:7] 3.3 V PCI_Init_Dev_Sel TP29 PCI_INTA PCI_INTC PCI_Reset R74 0ohm DNP 9,16 9,16 1 R72 33.2 PCI_Bus_Grant_0 12 TP33 2 R73 1 0ohm 2 R75 5.62K 12,16 14 GND D6 B D4 D2 D0 D0 PCI_IDSEL1 R71 33.2 A22 A20 A18 A16 PCI_Frame 12,14,16 PCI_Target_Ready 12,14,16 PCI_Trans_Stop 12,16 PCI_Parity 12,16 A15 A13 A11 A9 PCI_C/B_En0 C 12,16 A6 A4 A2 A0 GND 1 PCI_Clock REF VDD U13 C47 100nF GND D CY2305 Freescale Semiconductor CLKOUT 8 CLK1 3 CLK2 2 PCI_CLK_2 16 CLK3 5 PCI_CLK_3 9 CLK4 7 PCI_CLK_4 14 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA PCI_CLK_1 C39 22pF 4 12 6 3.3 V C45 22pF C38 22pF Lite5200B Evaluation Board PCI-1 C46 22pF Author Size J. Hartvigsen GND GND GND 2 GND Friday, September 02, 2005 3 Rev A A3 GND 1 D 4 Scale 20860 Sheet 5 15 of 24 1 2 3 4 5 3,7,10,12,15 A[0:23] 5V 3.3 V C27 47nF C28 47nF C69 47nF C94 47nF C33 47nF C26 47nF C43 47nF C34 47nF C68 47nF C58 47nF C70 47nF C44 47nF C95 47nF 7,10,12,15 D[0:7] 3.3 V GND 8 7 6 5 A -12 V PCI_INTC PCI_INTA 15 PCI_CLK_2 14 PCI_Bus_Req_1 D7 D5 B D3 D1 12,15 PCI_C/B_En3 A23 A21 A19 A17 12,15 PCI_C/B_En2 12,14,15 PCI_Initiator_Ready 12,15 PCI_Device_Select 12,15 PCI_Parity_Error 12,15 PCI_System_Error 12,15 PCI_C/B_En1 A14 A12 A10 C A8 A7 A5 A3 A1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 -12V TCK GND TDO +5V +5V INTB INTD PRSNT1 Reserved1 PRSNT2 TRST +12V TMS TDI +5V INTA INTC +5V Reserved6 +3.3V (I/O) Reserved5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 Reserved2 GND CLK GND REQ 3.3V (I/O) AD31 AD29 GND AD27 AD25 +3.3V C/BE3 AD23 GND AD21 AD19 +3.3V AD17 C/BE2 GND IRDY +3.3V DEVSEL GND LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 GND AD12 AD10 M66EN GND GND AD08 AD07 +3.3V AD05 AD03 GND AD01 +3.3V (I/O) ACK64 +5V +5V +3.3V (AUX) RST +3.3V (I/O) GNT GND PME AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME GND TRDY GND STOP +3.3V Reserved4 Reserved3 GND PAR AD15 +3.3V AD13 AD11 GND AD09 GND GND C/BE0 +3.3V AD06 AD04 GND AD02 AD00 +3.3V (I/O) REQ64 +5V +5V A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 PCI 32 Bit / 3.3V GND M66EN PCI Connector 32 Bit / 3.3V 9,15 9,15 +12 V GND J14 A C52 47nF 1 2 3 4 RP6 4x5.6K Put these capacitors as close as possible to the Power Pins of the connector. PCI_INTB PCI_INTD PCI_Reset PCI_Bus_Grant_1 9,15 9,15 12,15 14 D6 B D4 D2 PCI_IDSEL2 R70 D0 D1 33.2 A22 A20 A18 A16 PCI_Frame 12,14,15 PCI_Target_Ready 12,14,15 PCI_Trans_Stop 12,15 PCI_Parity 12,15 A15 A13 A11 A9 PCI_C/B_En0 C 12,15 A6 A4 A2 A0 GND Freescale Semiconductor 15 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D D R157 1 R158 33.2 R156 2 1 0ohm DNP 3.3 V Lite5200B Evaluation Board PCI-2 2 0ohm C115 10nF Author Size J. Hartvigsen GND GND 1 Friday, September 02, 2005 2 3 Rev A A3 4 Scale 20860 Sheet 5 16 of 24 1 2 3 4 1.5V Core & PLL Power Supply 3.3V I/O Power Supply 1.5 V VEXT J35 J27 BANANA WHITE U28 BANANA GREEN 1 FUSE 4 1.5V 1.5 V SHDN Supply Rail 3 R148 0 LT1764AEQ-1.5 VIN 1 DC POWER JACK + D84 6CWQ03FN J32 1 D45 BAT721A GND 4 SMD 2010 SENSE C88 100uF C87 100nF R155 0 U29 5 5 VIN 4 3.3 V SHDN Supply Rail 3 TAB BANANA BLACK 1.5 V BANANA BLUE 1 2 1 3 2 3.3 V J28 + C85 100nF 6 C86 33uF + C111 100uF 3.3V GND TAB LT1529-3.3 C112 100nF A 1 SMD 2010 SENSE 2 6 + C114 100nF C113 33uF 3 GND GND GND GND GND GND GND GND GND GND GND GND 2.5V DDR Power Supply 5V BANANA YELLOW 2 C132 100nF U32 2 R209 10.0kohm 3.3V Power Supply for HC08 5V 1 GND A5 M68HLC908QT1 6 A2 5 + R207 10.0kohm 2 4 PBSW 1 VIN 3 SHDN 2 GND 3.3V 5 BYP 4 3.3 V Supply Rail C128 1nF GND C131 + 100nF LT1761-3.3 C129 100nF C127 100uF C126 100nF 5 GND GND GND GND C124 + 100nF 6 GND GND GND GND C130 10uF 1.5 V 2.5 V GND C125 33uF GND 5V 1 1 3 3.3 V 5V Press Pushbutton to Initiate Power Down or Power Up Power Supply Monitoring R153 0ohm 5V 5V 5V 5V 2 GND SENSE 1 A1 SW4 Power Down Control GND SMD 2010 1 A4 2 A0 2 3 VDD 2 1.0kohm 1 B 4 TAB VSS 1 R208 12 PWR_DN_CTL_STS A3 2.5V 2.5 V SHDN Supply Rail 1 R201 0 LT1764AEQ-2.5 VIN 3 U33 7 8 U34 4 2.5 V J26 2 R149 10.0kohm B GND GND 1 GND 1 1 C91 100nF EPC:50uA @ 3.3 V C R273 536 R277 536 R279 536 R278 536 C U21 J8 BANANA BLUE 1 -12 V 0ohm DNP 2 5 V LS Typical Threshold 4.5 V 3.0 V 2.13 V 1.20 V 4.63 3.08 2.19 1.23 GND J34 GND J11 GND J30 3.3V D48 Green 5.0V D50 Green D49 Green Maximum Threshold 4.75 3.15 2.25 1.26 V V V V V V V V GND GND GND GND Freescale Semiconductor GND 1 D Q2-2 IRF7314 5 6 GND 4 Minimum Threshold 2.5V D47 Green A 1 3 3 R160 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA GND J7 D Lite5200B Evaluation Board Jumper Jumper Jumper 2 1 2 1 2 1 1 Power Supply 2 -12V Q1 BSR13_14 1 ATX PWR Q2-1 IRF7314 5V 47.5K 1.5V GND C R159 2.2K 1 2 3 4 2 2 +12V GND GND +5V 2 7 8 1 J36 MAX6338BUB 5V R161 A 5V C 3.3 V 1 5V, 3.3V, 2.5V, 1.23 V Monitor GND 10 9 8 7 6 A Delayed 5.0V VEXT Vcc Out1 Out2 Out3 Out4 C BANANA BLUE +12 V In1 In2 In3 In4 Gnd A +12V J5 1 2 3 4 5 C A 5V J25 5V F1 5 Author Size J. Hartvigsen Jumper Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 17 of 24 1 2 3 Dual Supply Supervisory Circuit Manual Reset and COP Reset 5 TP50 1 3.3 V 4 A Typical Reset Timeout (ms) 1.31 V (1.28 - 1.35) 180 A + C89 10uF C90 100nF TP52 1 2.93 V (2.85 - 3.000) R122 100.0kohm 1.5 V Reset Threshold 2 3.3 V Reset Threshold GND R123 0ohm DNP PORRESET 2 GND 6,7,9,14 TP47 1.5 V 1 3.3 V TP48 R124 0ohm V1.5 Circuit 2 GND RST 1 UP Supervisor J24 MR MAX6718UKSHD3-T B GND 1 SW2 1 3 GND 3.3 V 3 PBSW GND B 2 2 4 1 C63 100nF V3.3 4 Jumper GND R152 0ohm GND 1 R151 10.0kohm D46 BAT54A TP51 2 C64 100nF 5 2 U20 2 POR RESET JTAG_TRST 14 14 COP_TRST Reset for the COP/BDM Interface on the CORE The COP_RESET signal is driven by the external BDM 1 3.3 V TP49 R150 10.0kohm 2 D42 BAT54A C C ATA_3V_RESET 3 12 ATA_SW_RESET SW Reset for the ATA interface driven from PSC1 Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D D Lite5200B Evaluation Board Reset Circuitry & Supervisor Circuitry Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 18 of 24 3 4 2.5 V C192 1uF C209 100nF C118 100nF C119 100nF NC/A13 NC1 NC2 NC3 NC4 NC5 1 18 33 VDD VDD VDD 34 48 66 VSS VSS VSS 16 51 DNU 50 VDDQ VDDQ VDDQ VDDQ VDDQ 3 9 15 55 61 VSSQ VSSQ VSSQ VSSQ VSSQ 6 12 52 58 64 VREF 49 2.5 V A 1 17 43 19 25 14 53 LDQS UDQS Put these termination at the physical end of the clock lines. SDRAM_D0 SDRAM_D1 SDRAM_D2 SDRAM_D3 SDRAM_D4 SDRAM_D5 SDRAM_D6 SDRAM_D7 SDRAM_D8 SDRAM_D9 SDRAM_D10 SDRAM_D11 SDRAM_D12 SDRAM_D13 SDRAM_D14 SDRAM_D15 R125 10.0kohm GND R276 10.0kohm R291 1.0kohm 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 20,21 SDRAM_data_strobe_0 SDRAM_data_strobe_1 20,21 20,21 1 BA0 BA1 29 30 31 32 35 36 37 38 39 40 28 41 42 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 SDRAM_D[0:31] 20,21 20,21 TP61 R292 68.1 2.5 V C202 100nF DNP R290 1.0kohm 20,21 SDRAM_memclk C109 100nF C110 100nF C206 100nF C207 100nF C208 100nF 2.5 V GND R293 39.2 DNP C194 1uF GND GND GND GND R128 1.0kohm GND GND C203 22pF DNP GND GND B 1 B 26 27 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDRAM_data_mask_0 SDRAM_data_mask_1 2 SDRAM_ADD0 SDRAM_ADD1 SDRAM_ADD2 SDRAM_ADD3 SDRAM_ADD4 SDRAM_ADD5 SDRAM_ADD6 SDRAM_ADD7 SDRAM_ADD8 SDRAM_ADD9 SDRAM_ADD10 SDRAM_ADD11 SDRAM_ADD12 WE# CAS# RAS# CE# 20 47 1 20,21 SDRAM_Bank_add_0 20,21 SDRAM_Bank_add_1 A 21 22 23 24 LDM UDM 2 SDRAM_we SDRAM_cas SDRAM_ras SDRAM_cs0 CK CK# CKE 1 20,21 20,21 20,21 21 45 46 44 5 2 20,21 SDRAM_memclk 20,21 SDRAM_memclk_b 20,21 SDRAM_clk_en DDR 64 MByte U26 20,21 SDRAM_ADD[0:12] 1 2 2 1 GND GND GND MT46V32M16 GND R275 1.0kohm 2 GND C75 100nF GND GND R139 100 DNP GND 2.5 V 2.5 V C196 100nF C122 100nF C201 100nF 1 18 33 VDD VDD VDD 34 48 66 VSS VSS VSS DNU 50 VDDQ VDDQ VDDQ VDDQ VDDQ 3 9 15 55 61 VSSQ VSSQ VSSQ VSSQ VSSQ 6 12 52 58 64 VREF 49 1 NC/A13 NC1 NC2 NC3 NC4 NC5 16 51 2 17 43 19 25 14 53 LDQS UDQS R297 1.0kohm 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 SDRAM_D16 SDRAM_D17 SDRAM_D18 SDRAM_D19 SDRAM_D20 SDRAM_D21 SDRAM_D22 SDRAM_D23 SDRAM_D24 SDRAM_D25 SDRAM_D26 SDRAM_D27 SDRAM_D28 SDRAM_D29 SDRAM_D30 SDRAM_D31 TP62 GND GND R274 10.0kohm GND GND GND C205 100nF DNP R296 1.0kohm 20,21 SDRAM_memclk_b R145 10.0kohm GND R294 39.2 DNP SDRAM_data_strobe_2 SDRAM_data_strobe_3 GND C 20,21 20,21 C204 22pF DNP 2.5 V GND C123 100nF C105 100nF C108 100nF C106 100nF C107 100nF 2.5 V C190 1uF GND GND GND R147 1.0kohm GND GND GND C81 100nF MT46V32M16 Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA R146 1.0kohm 2 D GND R295 68.1 2 29 30 31 32 35 36 37 38 39 40 28 41 42 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 20,21 1 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDRAM_D[0:31] 20,21 20,21 1 C188 1uF 26 27 SDRAM_data_mask_2 SDRAM_data_mask_3 2 C WE# CAS# RAS# CE# 20 47 1 20,21 SDRAM_Bank_add_0 20,21 SDRAM_Bank_add_1 SDRAM_ADD0 SDRAM_ADD1 SDRAM_ADD2 SDRAM_ADD3 SDRAM_ADD4 SDRAM_ADD5 SDRAM_ADD6 SDRAM_ADD7 SDRAM_ADD8 SDRAM_ADD9 SDRAM_ADD10 SDRAM_ADD11 SDRAM_ADD12 21 22 23 24 LDM UDM 2 SDRAM_we SDRAM_cas SDRAM_ras SDRAM_cs0 CK CK# CKE 1 20,21 20,21 20,21 21 45 46 44 2 20,21 SDRAM_memclk 20,21 SDRAM_memclk_b 20,21 SDRAM_clk_en DDR 64 MByte U27 20,21 SDRAM_ADD[0:12] GND GND D Lite5200B Evaluation Board GND SDRAM Memory on CS0 Author DDR Memory 128 MByte on each CS Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 19 of 24 2 3 4 2.5 V C191 1uF C71 100nF C76 100nF C77 100nF BA0 BA1 29 30 31 32 35 36 37 38 39 40 28 41 42 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 17 43 19 25 14 53 NC/A13 NC1 NC2 NC3 NC4 NC5 1 18 33 VDD VDD VDD 34 48 66 VSS VSS VSS 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 LDQS UDQS 16 51 DNU 50 VDDQ VDDQ VDDQ VDDQ VDDQ 3 9 15 55 61 VSSQ VSSQ VSSQ VSSQ VSSQ 6 12 52 58 64 VREF 49 SDRAM_D[0:31] 19,21 19,21 19,21 SDRAM_D0 SDRAM_D1 SDRAM_D2 SDRAM_D3 SDRAM_D4 SDRAM_D5 SDRAM_D6 SDRAM_D7 SDRAM_D8 SDRAM_D9 SDRAM_D10 SDRAM_D11 SDRAM_D12 SDRAM_D13 SDRAM_D14 SDRAM_D15 A 2.5 V R283 1.0kohm SDRAM_data_strobe_0 SDRAM_data_strobe_1 19,21 19,21 2.5 V R284 68.1 C197 100nF DNP R282 1.0kohm C116 100nF C121 100nF C74 100nF C73 100nF C72 100nF 2.5 V 19,21 SDRAM_memclk C193 1uF GND GND GND R298 1.0kohm GND GND GND R285 39.2 DNP GND GND C198 22pF DNP B 1 B 26 27 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDRAM_data_mask_0 SDRAM_data_mask_1 1 SDRAM_ADD0 SDRAM_ADD1 SDRAM_ADD2 SDRAM_ADD3 SDRAM_ADD4 SDRAM_ADD5 SDRAM_ADD6 SDRAM_ADD7 SDRAM_ADD8 SDRAM_ADD9 SDRAM_ADD10 SDRAM_ADD11 SDRAM_ADD12 WE# CAS# RAS# CE# 20 47 2 19,21 SDRAM_Bank_add_0 19,21 SDRAM_Bank_add_1 A 21 22 23 24 LDM UDM 2 SDRAM_we SDRAM_cas SDRAM_ras SDRAM_cs1 CK CK# CKE 1 19,21 19,21 19,21 21 45 46 44 2 19,21 SDRAM_memclk 19,21 SDRAM_memclk_b 19,21 SDRAM_clk_en DDR 64 MByte U37 19,21 SDRAM_ADD[0:12] 5 1 1 GND GND GND GND R299 1.0kohm GND 2 GND C210 100nF MT46V32M16 GND GND GND U36 C 2.5 V C83 100nF C82 100nF C84 100nF A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 17 43 19 25 14 53 NC/A13 NC1 NC2 NC3 NC4 NC5 1 18 33 VDD VDD VDD 34 48 66 VSS VSS VSS SDRAM_D16 SDRAM_D17 SDRAM_D18 SDRAM_D19 SDRAM_D20 SDRAM_D21 SDRAM_D22 SDRAM_D23 SDRAM_D24 SDRAM_D25 SDRAM_D26 SDRAM_D27 SDRAM_D28 SDRAM_D29 SDRAM_D30 SDRAM_D31 LDQS UDQS 16 51 SDRAM_data_strobe_2 SDRAM_data_strobe_3 DNU 50 VDDQ VDDQ VDDQ VDDQ VDDQ 3 9 15 55 61 VSSQ VSSQ VSSQ VSSQ VSSQ 6 12 52 58 64 VREF 49 2.5 V 1 BA0 BA1 29 30 31 32 35 36 37 38 39 40 28 41 42 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 19,21 R288 1.0kohm 2 26 27 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDRAM_D[0:31] 19,21 19,21 R287 68.1 C104 100nF C80 100nF C79 100nF GND GND GND GND R289 1.0kohm C C78 100nF 2.5 V GND C199 22pF DNP GND C187 1uF GND GND GND R280 1.0kohm GND GND GND C195 100nF MT46V32M16 Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA R281 1.0kohm 2 D GND GND R286 39.2 DNP 19,21 19,21 2.5 V C120 100nF C200 100nF DNP 19,21 SDRAM_memclk_b 1 C189 1uF WE# CAS# RAS# CE# SDRAM_data_mask_2 SDRAM_data_mask_3 1 19,21 SDRAM_Bank_add_0 19,21 SDRAM_Bank_add_1 SDRAM_ADD0 SDRAM_ADD1 SDRAM_ADD2 SDRAM_ADD3 SDRAM_ADD4 SDRAM_ADD5 SDRAM_ADD6 SDRAM_ADD7 SDRAM_ADD8 SDRAM_ADD9 SDRAM_ADD10 SDRAM_ADD11 SDRAM_ADD12 21 22 23 24 20 47 2 SDRAM_we SDRAM_cas SDRAM_ras SDRAM_cs1 LDM UDM 1 19,21 19,21 19,21 21 CK CK# CKE 2 45 46 44 19,21 SDRAM_memclk 19,21 SDRAM_memclk_b 19,21 SDRAM_clk_en DDR 64 MByte 19,21 SDRAM_ADD[0:12] GND GND D Lite5200B Evaluation Board GND SDRAM Memory on CS1 Author DDR Memory 128 MByte on each CS Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 20 of 24 1 2 3 4 5 12 uP_SDRAM_D[0:31] A B 12 uP_SDRAM_CS0 R250 1 2 22ohm SDRAM_cs0 19 12 uP_SDRAM_CS1 R248 1 2 22ohm SDRAM_cs1 20 12 uP_SDRAM_CLKEN R138 1 2 22ohm SDRAM_clk_en 19,20 12 uP_SDRAM_CLK R109 1 2 22ohm SDRAM_memclk 12 uP_SDRAM_CLK_b R137 1 2 22ohm SDRAM_memclk_b 12 uP_SDRAM_WE R115 1 2 22ohm SDRAM_we 19,20 12 uP_SDRAM_CAS R114 1 2 22ohm SDRAM_cas 19,20 12 uP_SDRAM_RAS R249 1 2 22ohm SDRAM_ras 19,20 12 uP_SDRAM_BA_0 R251 1 2 22ohm SDRAM_Bank_add_0 19,20 12 uP_SDRAM_BA_1 R119 1 2 22ohm SDRAM_Bank_add_1 19,20 12 uP_SDRAM_DM_0 R103 1 2 22ohm SDRAM_data_mask_0 19,20 12 uP_SDRAM_DM_1 R108 1 2 22ohm SDRAM_data_mask_1 19,20 12 uP_SDRAM_DM_2 R144 1 2 22ohm SDRAM_data_mask_2 19,20 12 uP_SDRAM_DM_3 R263 1 2 22ohm SDRAM_data_mask_3 19,20 12 uP_SDRAM_DS_0 R131 1 2 22ohm SDRAM_data_strobe_0 19,20 12 uP_SDRAM_DS_1 R136 1 2 22ohm SDRAM_data_strobe_1 19,20 12 uP_SDRAM_DS_2 R253 1 2 22ohm SDRAM_data_strobe_2 19,20 12 uP_SDRAM_DS_3 R264 1 2 22ohm SDRAM_data_strobe_3 19,20 12 uP_SDRAM_ADD[0:12] 19,20 19,20 SDRAM_ADD[0:12] 19,20 C SDRAM_D[0:31] uP_SDRAM_D0 R126 1 2 22ohm SDRAM_D0 uP_SDRAM_D1 R99 1 2 22ohm SDRAM_D1 uP_SDRAM_D2 R127 1 2 22ohm SDRAM_D2 uP_SDRAM_D3 R100 1 2 22ohm SDRAM_D3 uP_SDRAM_D4 R129 1 2 22ohm SDRAM_D4 uP_SDRAM_D5 R101 1 2 22ohm SDRAM_D5 uP_SDRAM_D6 R130 1 2 22ohm SDRAM_D6 uP_SDRAM_D7 R102 1 2 22ohm SDRAM_D7 uP_SDRAM_D8 R107 1 2 22ohm SDRAM_D8 uP_SDRAM_D9 R135 1 2 22ohm SDRAM_D9 uP_SDRAM_D10 R106 1 2 22ohm SDRAM_D10 uP_SDRAM_D11 R134 1 2 22ohm SDRAM_D11 uP_SDRAM_D12 R105 1 2 22ohm SDRAM_D12 uP_SDRAM_D13 R133 1 2 22ohm SDRAM_D13 uP_SDRAM_D14 R104 1 2 22ohm SDRAM_D14 uP_SDRAM_D15 R132 1 2 22ohm SDRAM_D15 uP_SDRAM_D16 R255 1 2 22ohm SDRAM_D16 uP_SDRAM_D17 R256 1 2 22ohm SDRAM_D17 uP_SDRAM_D18 R257 1 2 22ohm SDRAM_D18 uP_SDRAM_D19 R258 1 2 22ohm SDRAM_D19 uP_SDRAM_D20 R259 1 2 22ohm SDRAM_D20 uP_SDRAM_D21 R261 1 2 22ohm SDRAM_D21 uP_SDRAM_D22 R260 1 2 22ohm SDRAM_D22 uP_SDRAM_D23 R262 1 2 22ohm SDRAM_D23 uP_SDRAM_D24 R265 1 2 22ohm SDRAM_D24 uP_SDRAM_D25 R266 1 2 22ohm SDRAM_D25 uP_SDRAM_D26 R267 1 2 22ohm SDRAM_D26 uP_SDRAM_D27 R268 1 2 22ohm SDRAM_D27 uP_SDRAM_D28 R269 1 2 22ohm SDRAM_D28 uP_SDRAM_D29 R270 1 2 22ohm SDRAM_D29 uP_SDRAM_D30 R271 1 2 22ohm SDRAM_D30 uP_SDRAM_D31 R272 1 2 22ohm SDRAM_D31 A B C uP_SDRAM_ADD0 R252 1 2 22ohm SDRAM_ADD0 uP_SDRAM_ADD1 R117 1 2 22ohm SDRAM_ADD1 uP_SDRAM_ADD2 R118 1 2 22ohm SDRAM_ADD2 uP_SDRAM_ADD3 R254 1 2 22ohm SDRAM_ADD3 uP_SDRAM_ADD4 R143 1 2 22ohm SDRAM_ADD4 uP_SDRAM_ADD5 R113 1 2 22ohm SDRAM_ADD5 uP_SDRAM_ADD6 R142 1 2 22ohm SDRAM_ADD6 uP_SDRAM_ADD7 R112 1 2 22ohm SDRAM_ADD7 uP_SDRAM_ADD8 R141 1 2 22ohm SDRAM_ADD8 uP_SDRAM_ADD9 R111 1 2 22ohm SDRAM_ADD9 uP_SDRAM_ADD10 R120 1 2 22ohm SDRAM_ADD10 uP_SDRAM_ADD11 R140 1 2 22ohm SDRAM_ADD11 Freescale Semiconductor uP_SDRAM_ADD12 R110 1 2 22ohm SDRAM_ADD12 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D 19,20 D Lite5200B Evaluation Board SDRAM Termination Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A3 4 Scale A 20860 Sheet 5 21 of 24 1 2 3 4 5 De-coupling SWITCHES A A 3.3 V 3.3 V 3.3 V 3.3 V 1OE 1A1 1A2 1A3 1A4 1A5 14 17 18 21 22 2A1 2A2 2A3 2A4 2A5 13 12 2OE GND VCC 24 1B1 1B2 1B3 1B4 1B5 2 5 6 9 10 USB1_OE_S USB1_TXN_S USB1_TXP_S USB1_RXD_S USB1_RXP_S 2B1 2B2 2B3 2B4 2B5 15 16 19 20 23 USB1_RXN_S 24 USB1_PORTPWR_S 24 USB1_SPEED_S 24 USB1_SUSPEND_S 24 USB1_OVRCURRENT_S 24 24 24 24 24 9,11,12 ETH_TXEN 9,11,12 ETH_TXD[0] 9,12 ETH_RXDV 9,12 ETH_COL C9 100nF 9,12 ETH_RXD[0] 9,11,12 ETH_TXD[1] 24 2 U10 CORE SIDE TRANSCEIVER SIDE 1 1 2 R60 2 R61 1.0kohm 1.0kohm SN74CBTLV3384 1 1OE 3 4 7 8 11 1A1 1A2 1A3 1A4 1A5 14 17 18 21 22 2A1 2A2 2A3 2A4 2A5 13 12 2OE GND VCC 24 1B1 1B2 1B3 1B4 1B5 2 5 6 9 10 2B1 2B2 2B3 2B4 2B5 15 16 19 20 23 10 bit FET BUS Switch 8,12 USB1_RXN 8,12 USB1_PORTPWR 8,12 USB1_SPEED 8,12 USB1_SUSPEND 8,12 USB1_OVRCURRENT CORE SIDE 1 3 4 7 8 11 R62 0ohm 10/100 Base-T Ethernet De-coupling Switch R63 47.5K 2 USB1_OE USB1_TXN USB1_TXP USB1_RXD USB1_RXP 10 bit FET BUS Switch 2 U6 8,12 8,11,12 8,11,12 8,12 8,12 B Jumper USB De-coupling Switch 1 1 Jumper R43 47.5K Use Jumper to open switch U24 and U25 (to de-couple Ethernet transceiver from external Connector) 2 2 2 1 R14 0ohm Use Jumper to open switch U23 (to de-couple USB transceiver from external Connector) 1 J9 1 J12 1 TRANSCEIVER SIDE ETH_TXEN_S 6 ETH_TXD[0]_S 6 ETH_RXDV_S 6 ETH_COL_S 6 C40 100nF ETH_RXD[0]_S 6 ETH_TXD[1]_S 6 B 3.3 V SN74CBTLV3384 GND GND GND GND GND 1 GND 2 R64 0ohm 10/100 Base-T Ethernet De-coupling Switch U11 1OE 9,11,12 9,11,12 9,11,12 9,11,12 9,12 ETH_TXD[2] ETH_TXD[3] ETH_TXERR ETH_MDC ETH_MDIO 3 4 7 8 11 1A1 1A2 1A3 1A4 1A5 9,12 9,12 9,12 9,12 9,12 ETH_RXD[1] ETH_RXD[2] ETH_RXD[3] ETH_RXERR ETH_CRS CORE SIDE 14 17 18 21 22 2A1 2A2 2A3 2A4 2A5 13 12 2OE GND VCC 24 1B1 1B2 1B3 1B4 1B5 2 5 6 9 10 ETH_TXD[2]_S ETH_TXD[3]_S ETH_TXERR_S ETH_MDC_S ETH_MDIO_S 6 6 6 6 6 2B1 2B2 2B3 2B4 2B5 15 16 19 20 23 ETH_RXD[1]_S ETH_RXD[2]_S ETH_RXD[3]_S ETH_RXERR_S ETH_CRS_S 6 6 6 6 6 10 bit FET BUS Switch C 1 C147 100nF C TRANSCEIVER SIDE SN74CBTLV3384 GND GND 6,9,12 ETH_RXCLK ETH_RXCLK_S 6,9,12 6,9,12 ETH_TXCLK ETH_TXCLK_S 6,9,12 Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D D Lite5200B Evaluation Board Switches Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 22 of 24 1 2 3 4 5 3.3 V 1 A A MONITOR UART Controlled by PSC1 Port Implements only HW Handshake 2 R41 0ohm C21 100nF Monitor UART Transceiver (ESD protected) GND C218 100nF C1- 5 C2+ 6 C2- 19 Monitor UART DSUB Connector V+ V- 7 C219 100nF J3 100nF C217 TX0 13 T1IN T1_OUT 17 12 RTS0 12 T2IN T2_OUT 8 12 CTS0 15 R1OUT 12 RX0 10 R2OUT 11 14 INVALID FORCEON GND 12 16 R2IN 9 READY FORCEOFF GND 11 B 10 DSUB9M 1 20 3.3 V L5 BLM21A 1 Max3224ECAP R1IN GND 5 9 4 8 3 7 2 6 1 18 B C1+ 4 3 1 C211 100nF VCC U1 2 2 GND 2 R40 10.0kohm R39 0ohm DNP 1 GND 2 To shutdown UART, close jumper C C Freescale Semiconductor Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA D D Lite5200B Evaluation Board MONITOR Uart Author Size J. Hartvigsen Friday, September 02, 2005 1 2 3 Rev A A3 4 Scale 20860 Sheet 5 23 of 24 1 2 3 4 5 USB Port plus Power Management 1 5V Power Management Section for a single MASTER USB Port EN is active high. 2 R44 0ohm 2 R42 10.0kohm A 1 3.3 V A J4 U3 7 8 6 5 1 MIC2025 D1D1+ R21 221 + GND GND VBus DD+ GND SHR USB Connector C11 100nF D4 Green GND R17 15.0kohm R20 15.0kohm GND L6 0805_Bead B 2 2 2 C B SHL 1 2 3 4 R C22 47uF A C135 100nF 1 Sleep Mode: 5uA EPC: 160uA @ 3.3 V TP25 TP22 2 L7 0805_Bead L 1 EN USB Power IN FLG OUT NC1 OUT GND NC2 1 1 2 4 3 22 USB1_PORTPWR_S 22 USB1_OVRCURRENT_S GND GND GND 3.3 V 1 GND GND 2 R600 0ohm C10 100nF 14 GND 22 USB1_TXN_S 22 USB1_TXP_S 22 USB1_RXP_S 22 USB1_RXN_S 4 5 VP VM 22 USB1_RXD_S 3 RCV 22 USB1_SPEED_S 22 USB1_SUSPEND_S 9 6 SPEED SUSPND 1 MODE TP21 TP17 TP18 TP20 TP26 TP19 TP24 OE GND VMO/FSE0 VPO D+ 11 R18 33.2 D- 10 R19 33.2 NC 8 C USB1T11AMTC 7 C 2 13 12 VCC U2 22 USB1_OE_S TP23 GND 2 3.3 V 1 R16 10.0kohm Freescale Semiconductor 2 Freescale Semiconductor 7700 Parmer Lane Austin, Texas 78729 USA R15 10.0kohm DNP 1 D Lite5200B Evaluation Board GND USB Author Size J. Hartvigsen 2 3 Rev A A3 Friday, September 02, 2005 1 D 4 Scale 20860 Sheet 5 24 of 24