INTEGRATED CIRCUITS DATA SHEET SAB9075H Picture-in-Picture (PIP) controller for NTSC Preliminary specification File under Integrated Circuits, IC02 Philips Semiconductors February 1995 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H FEATURES GENERAL DESCRIPTION Display The SAB9075H is a picture-in-picture controller for the NTSC environment in combination with the Integrated NTSC decoder and sync processor TDA8315. • One or two live pictures can be displayed simultaneously The device inserts one or two live video channels with reduced sizes into a live video signal. All video signals are expected to be analog baseband signals. The conversion into the digital environment and back to the analog environment is carried out on-chip. Internal clocks are generated by two PLLs. • Wide range of multi-Picture-In-Picture (PIP) modes available • Six 6-bit Analog-to-Digital Converters (ADC) with clamping circuit • Enhanced vertical resolution at most modes for live pictures Due to the two PIP channels and a large external memory, a wide range of PIP modes are offered. The emphasis is put on double-PIP and multi-PIP modes. In combination with the different border colours and some external software the IC concept can be used as an excellent channel selection tool. • Two Phase-Locked-Loops (PLL) with Voltage Controlled Oscillator (VCO) to generate the line-locked clocks • Three 7-bit Digital-to-Analog Converters (DAC) • 4 : 1 : 1 data format Some of the I2C-bus registers are for controlling the saturation and HUE of the colours. There are also outputs for the mute function of main and sub-channel. • Data reduction factors 1 to 4, 1 to 9 and 1 to 16. I2C-bus programmable • Different single, double and multi-PIP modes can be set • Several aspect ratios can be handled • Reduction factors can be set automatically and manually • Selection of vertical filtering type • Freeze of live pictures • Single-PIP display position, four corners on-screen • Multi-PIP display position, left or right on-screen • Fine tuned display position, H (6-bit), V (6-bit) • Fine tuned acquisition area, H (4-bit), V (4-bit) • Channel-border and live PIP selectable • Eight main-border, sub-border, channel-border and background colours selectable • Border and background brightness adjustable, 30%, 50%, 70% and 100% IRE • Several types of decoder input signals can be set • 6-bit HUE and SAT signals (0 to 5 V) adjustable by I2C-bus • Main and sub-audio mute controllable by I2C-bus. February 1995 2 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION SAB9075H QFP100(1) plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm SOT317-2 Note 1. When using IR reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Handbook” (order number 9398 510 63011) are followed. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage all positive supply pins 4.5 5.0 5.5 V Itot total supply current note 1 tbf 220 tbf mA fsys system frequency note 2 − 27 30 MHz floop loop bandwidth frequency 4 − − kHz tjitter short term stability time − − 4 ns ς damping factor − 0.7 − − jitter during 1 line (64 µs) Notes 1. Digital clocks are silent and analog bias current is zero. 2. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see Section “PLLs and clock generation”. February 1995 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... MY MU MV MAI bias MAV refT MAV refB 98 94 96 93 97 95 100 92 91 82 81 89 90 CLAMP AND A/D CONVERTER 72 73 9 8 47 45 44 32 4 SAI bias SAV refT SAV refB HUE SAT MMUTE SMUTE 27 DAV DDA 11 20 AD0 to 8 DAI0 to 7 36,39,40,38 29,31,35,33 41,46,37,34 26,25,30,28 48 to 56 10 21 18 14 16 ACQUISITION MAIN D/A CONVERTER AND BUFFER 87 83 85 88 86 84 CLAMP AND A/D CONVERTER 19 13 15 17 MEMORY CONTROL SAB9075H SY SU SV DAO0 to 7 DAV SSA DAV DDD ACQUISITION SUB 24 DISPLAY 65 66 70 69 67 68 HUE AND SAT D/A CONVERTERS DISPLAY TIMING CONTROL AND PLL BLOCK 22 42 43 71 I C VDD V DDD V SSS SV sync 2 23 74 76 77 78 79 80 3 4 2 I C-BUS 5 7 2 1 59 60 61 58 6 63 64 DY DU DV DAI bias DAV refTU DAV refTV DAV refTY DBF Philips Semiconductors 99 DAV SSD SC Picture-in-Picture (PIP) controller for NTSC BLOCK DIAGRAM dbook, full pagewidth February 1995 SV SSD MVSSD MAVSSD MAV SSA SAVSSD SAVSSA RAS WE SAVDDA SV DDD MV DDD MAVDDD MAV DDA SAV DDD CAS DT SCL SDA POR A0 75 MBE084 SPVDDD MVsync SPI bias SPVSSD MH sync MPV SSD MPV SSA TM0 SPVSSA SPVDDA SH sync TM1 MPI bias MPV DDD MPV DDA TC STCLK Preliminary specification SAB9075H Fig.1 Block diagram. MTCLK TM2 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H PINNING SYMBOL PIN I/O TYPE DESCRIPTION MPVDDA 1 I/O E030 analog positive power supply for PLL main-channel MPVSSA 2 I/O E009 analog negative power supply for PLL main-channel MHsync 3 I E027 horizontal synchronization for main-channel MPIbias 4 I E027 analog bias reference current for PLL main-channel MPVSSD 5 I/O E009 digital negative power supply for PLL main-channel MTCLK 6 I HPP01 MPVDDD 7 I/O E030 digital positive power supply for PLL main-channel MVDDD 8 I/O E030 digital positive power supply for main-channel core MVSSD 9 I/O E009 digital negative power supply for main-channel core DAVDDD 10 I/O E030 digital positive power supply for DACs test clock for main-channel DAVSSD 11 I/O E009 n.c. 12 − − DAVrefTU 13 I/O E027 analog reference voltage for top U DAC DU 14 O E027 analog U output DAVrefTV 15 I/O E027 analog reference voltage for top V DAC DV 16 O E027 analog V output DAVrefTY 17 I/O E027 analog reference voltage for top Y DAC DY 18 O E027 analog Y output DAIbias 19 I E027 analog bias reference current for DACs DAVSSA 20 I/O E009 analog negative power supply for DACs DAVDDA 21 I/O E030 analog positive power supply for DACs I2CVDD 22 I/O E030 positive supply for HUE and SAT decoders MVsync 23 I HPP01 vertical synchronization for main-channel DBF 24 O SPF20 fast blanking control output signal DAI5 25 I HPP01 data bus input from memory; bit 5 DAI4 26 I HPP01 data bus input from memory; bit 4 SC 27 O OPF20 memory shift clock DAI7 28 I HPP01 data bus input from memory; bit 7 DAI0 29 I HPP01 data bus input from memory; bit 0 DAI6 30 I HPP01 data bus input from memory; bit 6 DAI1 31 I HPP01 data bus input from memory; bit 1 DT 32 O OPF20 memory data transfer; active LOW DAI3 33 I HPP01 data bus input from memory; bit 3 DAO7 34 O OPF20 data bus output to memory; bit 7 DAI2 35 I HPP01 data bus input from memory; bit 2 DAO0 36 O OPF20 data bus output to memory; bit 0 DAO6 37 O OPF20 data bus output to memory; bit 6 DAO3 38 O OPF20 data bus output to memory; bit 3 DAO1 39 O OPF20 data bus output to memory; bit 1 DAO2 40 O OPF20 data bus output to memory; bit 2 February 1995 digital negative power supply for DACs not connected 5 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SYMBOL SAB9075H PIN I/O TYPE DESCRIPTION DAO4 41 O OPF20 VDDD 42 I/O E030 digital positive power supply for peripherals VSSS 43 I/O E009 digital negative power supply for peripherals WE 44 O OPF20 memory write enable; active LOW data bus output to memory; bit 4 CAS 45 O OPF20 memory column address strobe; active LOW DAO5 46 O OPF20 data bus output to memory; bit 5 RAS 47 O OPF20 memory row address strobe; active LOW AD0 48 O OPF20 memory address bus; bit 0 AD8 49 O OPF20 memory address bus; bit 8 AD1 50 O OPF20 memory address bus; bit 1 AD6 51 O OPF20 memory address bus; bit 6 AD2 52 O OPF20 memory address bus; bit 2 AD5 53 O OPF20 memory address bus; bit 5 AD3 54 O OPF20 memory address bus; bit 3 AD4 55 O OPF20 memory address bus; bit 4 AD7 56 O OPF20 memory address bus; bit 7 n.c. 57 − − TC 58 I HPP01 test control TM0 59 I HPP01 test mode 0 TM1 60 I HPP01 test mode 1 TM2 61 I HPP01 test mode 2 n.c. 62 − − not connected POR 63 I HUP07 power-on reset A0 64 I HPF01 I2C-bus address 0 selection pin SCL 65 I HPF01 shift clock for I2C-bus SDA 66 I/O IOI41 MMUTE 67 O SPF20 not connected shift I2C-bus input data; acknowledge I2C-bus output data mute output for main-channel SMUTE 68 O SPF20 SAT 69 O E027 analog output for SAT decoder HUE 70 O E027 analog output for HUE decoder SVsync 71 I HPP01 SVSSD 72 I/O E009 digital negative power supply for sub-channel core SVDDD 73 I/O E030 digital positive power supply for sub-channel core SPVDDD 74 I/O E030 STCLK 75 I HPP01 SPVSSD 76 I/O E009 digital negative power supply for PLL sub-channel SPIbias 77 I E027 analog bias reference current for PLL sub-channel SHsync 78 I E027 horizontal synchronization for sub-channel SPVSSA 79 I/O E009 analog negative power supply for PLL sub-channel SPVDDA 80 I/O E030 analog positive power supply for PLL sub-channel SAVDDD 81 I/O E030 digital positive power supply for ADC sub-channel February 1995 mute output for sub-channel vertical synchronization for sub-channel digital positive power supply for PLL sub-channel test clock for sub-channel 6 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SYMBOL SAB9075H PIN I/O TYPE SAVSSD 82 I/O E009 digital negative power supply for ADC sub-channel SU 83 I E027 analog U input for sub-channel SAVrefB 84 I/O E027 analog reference voltage for bottom ADC sub-channel SV 85 I E027 analog V input for sub-channel SAVrefT 86 I/O E027 analog reference voltage for top ADC sub-channel SY 87 I E027 analog Y input for sub-channel SAIbias 88 I E027 analog bias reference current for ADC sub-channel SAVSSA 89 I/O E009 analog negative power supply for ADC sub-channel SAVDDA 90 I/O E030 analog positive power supply for ADC sub-channel MAVDDA 91 I/O E030 analog positive power supply for ADC main-channel MAVSSA 92 I/O E009 analog negative power supply for ADC main-channel MAIbias 93 I E027 analog bias reference current for ADC main-channel MU 94 I E027 analog U input for main-channel MAVrefB 95 I/O E027 analog reference voltage for bottom ADC main-channel MV 96 I E027 analog V input for main-channel MAVrefT 97 I/O E027 analog reference voltage for top ADC main-channel MY 98 I E027 analog Y input for main-channel MAVSSD 99 I/O E009 digital negative power supply for ADC main-channel MAVDDD 100 I/O E030 digital positive power supply for ADC main-channel Table 1 DESCRIPTION Pin type explanation PIN TYPE DESCRIPTION E030 VDD pin; diode to VSS E009 VSS pin; diode to VDD E027 analog input pin; diode to VDD and VSS HPF01 digital input pin; CMOS levels, diode to VSS HPP01 digital input pin; CMOS levels, diode to VDD and VSS HUP07 digital input pin; CMOS levels with hysteresis, pull up resistor to VDD, diode to VDD and VSS IOI41 I2C-bus pull-down output stage; CMOS input levels OPF20 digital output pin SPF20 digital output pin; slew rate controlled February 1995 7 51 AD6 52 AD2 53 AD5 54 AD3 55 AD4 56 AD7 57 n.c. 58 TC 59 TM0 60 TM1 61 TM2 62 n.c. 63 POR 64 A0 65 SCL 66 SDA 67 MMUTE 68 SMUTE 69 SAT 70 HUE 71 SV sync 74 SPVDDD 73 SVDDD 72 SVSSD 75 STCLK 80 SPVDDA 79 SPVSSA 78 SH sync 50 AD1 SAV SSD 82 49 AD8 SU 83 48 AD0 SAVrefB 84 47 RAS SV 85 46 DAO5 SAV refT 86 45 CAS SY 87 44 WE 43 V SSS SAI bias 88 SAV SSA 89 42 V DDD SAV DDA 90 41 DAO4 SAB9075H 40 DAO2 MAV SSA 92 MAI bias 93 39 DAO1 MU 94 37 DAO6 MAVrefB 95 36 DAO0 38 DAO3 35 DAI2 MV 96 MAV refT 97 34 DAO7 MY 98 33 DAI3 DAI6 30 DAI0 29 SC 27 DAI7 28 DAI4 26 DAI5 25 DBF 24 MV sync 23 I 2 C V DD 22 DAVSSA 20 DAVDDA 21 DAI bias 19 DY 18 DAV refTY 17 DV 16 DAV refTV 15 DU 14 n.c. 12 DAV refTU 13 DAV SSD 11 MV SSD 9 DAV DDD 10 8 MV DDD 6 5 4 7 MPV DDD MTCLK MPVSSD MH sync MPI bias MBE083 SAB9075H Fig.2 Pin configuration. DAI1 Preliminary specification MPV SSA 3 31 2 32 DT MAVDDD 100 1 MAVSSD 99 MPV DDA 8 MAV DDA 91 Philips Semiconductors SAV DDD 81 Picture-in-Picture (PIP) controller for NTSC February 1995 77 SPI bias 76 SPVSSD This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H It is expected that the input signals do not contain frequencies outside the video bandwidth (YBW = 4.5 MHz; UBW and VBW = 1.125 MHz). FUNCTIONAL DESCRIPTION Acquisition area The acquisition area is in the centre of the visible screen area. Vertically 228 lines are sampled. Horizontally 672 Y-pixels are processed. The exact active processing area can be fine tuned in horizontal (2 pixels/steps, 16 steps) and vertical (1 line/step, 16 steps) direction for both main and sub-channel by the I2C-bus (see Fig.3). The given numbers are pixel numbers at a 13.5 MHz data rate. The signals, which are dependent on the I2C-bus registers, can also be related to the Hsync, in which event they are delayed by 68 pixels. Display area The display area is shown in Fig.4. The given numbers are pixels at a data rate of 13.5 MHz. The signals are related to the burstkey and the Vsync. Dependent on the I2C-bus registers the signals can also be related to the Hsync. The internal 13.5 MHz data rate is upsampled to the double frequency (27 MHz) and then fed to the DACs. The display output can be fine positioned by the I2C-bus in 64 steps of 4 pixels in horizontal direction and 64 steps of 1 line/field in vertical direction. Chrominance format The chrominance format is 4 : 1 : 1. The YUV signals are sampled at a rate of 27 MHz and then filtered and subsampled to a data rate of 13.5 MHz. 32 handbook, full pagewidth clamp 68 864 H sync burstkey V sync 80 104 18 262.5 FT FT FT 672 624 1/1, 1/3 and 1/4 reduction 1/2 reduction 228 MBE085 18 FT Fig.3 Acquisition area. February 1995 9 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC handbook, full pagewidth 68 SAB9075H 864 H sync burstkey 36 11 262.5 FT 672 V sync FT 228 MBE086 11 FT Fig.4 Display area. February 1995 10 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H PIP modes The controller contains two independent acquisition-channels which provide the scaling factors to support the range of different modes. With the external memory of 2 Mbit it is possible to select between single, double and multi-PIP modes. Table 2 gives an overview of the different PIP modes. Table 2 PIP modes SUB SIZE(1) MODE SUB MAIN PIXELS MAIN SIZE(1) REDUCTION(2) PIXELS REDUCTION(2) 4 : 3 main + 4 : 3 sub to 4 : 3 screen or 16 : 9 main + 16 : 9 sub to 16 : 9 screen SPS 1⁄ SPL 1⁄ 1.3 DP 1⁄ 1.4 MP3 3 × 1⁄16 − 1.5 MP4 3 × 1⁄16 1⁄ 1.1 1.2 − 16 9 − 4 1⁄ MP7 7× 1⁄ 1.7 MP8 7× 1⁄ 1.8 MP9 8 × 1⁄9 1.6 16 − 16 1⁄ 1⁄ 160P, 53L 216P, 72L 4 304P, 108L 160P, 53L 4 160P, 53L 160P, 53L 4 160P, 53L 9 216P, 72L 1⁄ H, 4 1⁄ H, 3 1⁄ H, 2 1⁄ H, 4 1⁄ H, 4 1⁄ H, 4 1⁄ H, 4 1⁄ H, 3 1⁄ 4V − 1⁄ − 3V − − 1⁄ 2V 304P, 108L 1⁄ 1⁄ 4V − − 1⁄ 4V 304P, 108L 1⁄ 1⁄ 4V − − 1⁄ 4V 304P, 108L 1⁄ 1⁄ 3V 216P, 72L 1⁄ − − − − 304P, 108L 1⁄ 2H, 1⁄ 2V 2H, 1⁄ 2V 2H, 1⁄ 2V 1 3H, ⁄3V 16 : 9 sub + 4 : 3 main to 4 : 3 screen 2.1 SPS 1⁄ 2.2 SPL 1⁄ 16 − 216P, 53L 9 − 304P, 72L 160P, 72L 1⁄ H, 1⁄ V 3 4 1⁄ H, 1⁄ V 2 3 4 : 3 sub + 16 : 9 main to 16 : 9 screen 3.1 SPS 1⁄ 16 − 3.2 DP 1⁄ 4 1⁄ 4 216P, 108L 1⁄ H, 1⁄ V 4 3 1⁄ H, 1⁄ V 3 2 2H, 1⁄ 2V Notes 1. The given sub/main sizes are visible PIP sizes, a border is drawn around these PIPs and does not influence these sizes. The size of the border is 4 pixels wide and 2 lines/fields high. 2. The SAB9075H can be set in automatic mode in which the reduction factors are automatically set by the mode select and aspect ratio select bits of the I2C-bus. If the automatic mode is switched OFF the reduction factors can be set manually. This will give more flexibility to adjust the aspect ratios of incoming signals. PIP positions The positions are graphically depicted in Figs 5 to 17. February 1995 11 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 288 168 168 24 11 S 57 228 92 57 11 MBE087 Fig.5 Single-PIP, size 1⁄16 (mode SPS). burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 224 176 224 24 11 76 S 228 54 76 11 MBE088 Fig.6 Single-PIP, size 1⁄9 (mode SPL). February 1995 12 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 312 24 312 58 S 112 M 228 58 MBE089 Fig.7 Double-PIP, size 1⁄16 (mode DP). burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 36 168 264 168 36 24 57 C0 57 C1 57 C2 5 228 5 23 MBE090 Fig.8 Multi PIP, 3 × sub 1⁄16 (mode MP3). February 1995 13 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H burstkey handbook, full pagewidth V sync 36 FT 672 11 36 FT 168 120 312 36 24 34 57 C0 5 57 C1 112 M 228 5 C2 57 35 23 MBE091 Fig.9 Multi-PIP, 3 × sub 1⁄16, 1 × main 1⁄4 (mode MP4). burstkey handbook, full pagewidth V sync 36 FT 672 11 36 FT 312 120 168 36 24 57 34 C0 5 57 112 M C1 228 5 C2 57 35 23 MBE092 Fig.10 Multi-PIP, 3 × sub 1⁄16, 1 × main 1⁄4 (mode MP4, Right). February 1995 14 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H burstkey handbook, full pagewidth V sync 36 FT 672 11 168 FT 57 C0 57 C1 168 168 168 228 57 C2 57 C3 C4 C5 C6 MBE093 Fig.11 Multi-PIP, 7 × sub 1⁄16, main life (mode MP7). burstkey handbook, full pagewidth V sync 36 FT 672 168 11 FT 168 168 96 168 312 96 30 57 C0 57 C1 112 M 228 57 C2 29 57 C3 C4 C5 C6 MBE094 Fig.12 Multi-PIP, 7 × sub 1⁄16, 1 × main 1⁄4 (mode MP8). February 1995 15 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H burstkey handbook, full pagewidth V sync 36 FT 672 224 224 224 76 C0 C1 C2 76 C3 M C4 76 C5 C6 C7 11 FT 228 MBE095 Fig.13 Multi-PIP, 8 × sub 1⁄9, 1 × main 1⁄9 (mode MP9). burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 168 288 24 168 11 76 S 228 54 76 11 MBE097 Fig.14 Single-PIP, 4 : 3 sub to 16 : 9 screen (mode SPS). February 1995 16 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 176 224 224 24 11 S 57 228 92 57 11 MBE096 Fig.15 Single-PIP, 16 : 9 sub to 4 : 3 screen (mode SPS). burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 312 312 24 11 76 S 228 54 76 11 MBE098 Fig.16 Single-PIP, 16 : 9 sub to 4 : 3 screen (mode SPL). February 1995 17 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H burstkey handbook, full pagewidth V sync 36 FT 696 11 FT 238 MBE099 Fig.17 Factory mode. February 1995 18 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H I2C-bus I2C-bus control is in accordance with the I2C-bus protocol. The I2C-bus provides bi-directional 2-line communication between different ICs. The SDA line is the Serial Data line and the SCL serves as Serial Clock Line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. First a start sequence must be put on the I2C-bus, then the I2C-bus address 2C or 2E, followed by a subaddress 00 to 0F. After this sequence, the data of the subaddress must be sent. An auto-increment function then gives the option ‘send data’ of the incremented subaddresses until a stop sequence has been given. The SAB9075H has the I2C-bus addresses 2C and 2E, switchable by the pin A0. Valid subaddresses are 00H to 0FH. Table 3 Overview of I2C-bus addresses (note 1) Data Bytes SA BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00 PIPON MANRED MASPECT SASPECT MODE3 MODE2 MODE1 MODE0 01 HPOS VPOS MFREEZE SFREEZE note 2 BCOLPOL MVFILT SVFILT 02 note 2 note 2 DHFP5 DHFP4 DHFP3 DHFP2 DHFP1 DHFP0 03 note 2 note 2 DVFP5 DVFP4 DVFP3 DVFP2 DVFP1 DVFP0 04 MREDH1 MREDH0 MREDV1 MREDV0 SREDH1 SREDH0 SREDV1 SREDV0 05 note 2 CBSEL2 CBSEL1 CBSEL0 note 2 SLSEL2 SLSEL1 SLSEL0 06 note 2 MBON MBBRT1 MBBRT0 note 2 MBCOL2 MBCOL1 MBCOL0 07 note 2 SBON SBBRT1 SBBRT0 note 2 SBCOL2 SBCOL1 SBCOL0 08 note 2 CBON CBBRT1 CBBRT0 note 2 CBCOL2 CBCOL1 CBCOL0 09 FACMODE BGON BGBRT1 BGBRT0 note 2 BGCOL2 BGCOL1 BGCOL0 0A MCOLPOL MVSPOL MHSYNC MFPOL SCOLPOL SVSPOL SHSYNC SFPOL 0B MAAHFP3 MAAHFP3 MAAHFP3 MAAVFP3 MAAVFP3 MAAVFP3 MAAVFP3 0C SAAHFP3 SAAHFP3 SAAHFP3 SAAHFP3 SAAVFP3 SAAVFP3 SAAVFP3 SAAVFP3 0D note 2 note 2 HUE5 HUE4 HUE3 HUE2 HUE1 HUE0 0E note 2 note 2 SAT5 SAT4 SAT3 SAT2 SAT1 SAT0 0F MMUTE SMUTE note 2 note 2 note 2 note 2 note 2 note 2 MAAHFP3 Notes 1. Table 3 gives an overview of the I2C-bus addresses. They will be explained in more detail in the following pages. 2. Some address spaces are unused but already implemented for future functionality. February 1995 19 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC Table 4 SAB9075H PIP mode control (note 1) PIP MODE NAME MODE(3) MAIN-REDUCTION(2) ASPECT RATIO MAIN(4) SUB(4) HOR VER HOR VER 1⁄ 4 1⁄ 3 1⁄ 4 1⁄ 4 1⁄ 3 1⁄ 2 1⁄ 3 1⁄ 2 1⁄ 3 1⁄ 2 1⁄ 4 1⁄ 4 1⁄ 4 1⁄ 4 1⁄ 3 1⁄ 4 1⁄ 4 1⁄ 3 1⁄ 4 1⁄ 3 1⁄ 3 1⁄ 3 1⁄ 2 1⁄ 2 1⁄ 2 1⁄ 4 1⁄ 4 1⁄ 4 1⁄ 4 1⁄ 3 SPS 0000 0 0 − − SPS 0000 0 1 − − SPS 0000 1 0 − − SPS 0000 1 1 − − SPL 0001 0 0 − − SPL 0001 0 1 − − SPL 0001 1 X − − 1⁄ 2 1⁄ 2 1⁄ 2 1⁄ 2 1⁄ 2 1⁄ 2 DP 1010 0 X DP 1010 1 0 DP 1010 1 1 MP3 0110 X X − − MP4 1110 X X 1⁄ 2 1⁄ 2 MP7 0100 X X − − 1⁄ 2 1⁄ 3 1⁄ 2 1⁄ 3 MP8 1100 X X MP9 1001 X X SUB-REDUCTION(2) Notes 1. Table 4 gives an overview of the possible PIP modes and how to set them via the I2C-bus. 2. The columns main and sub-reduction indicate how the PIP pictures appear on the screen. 3. The column mode corresponds to the lower 4 bits of I2C-bus Register 0. 4. The main and sub-aspect ratios correspond to the bits 5 and 6 of I2C-bus Register 0. February 1995 20 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC Table 5 SAB9075H Register 0; PIP mode control register BIT MODE RESULT 7 PIPON logic 0 = PIP function is OFF(1); logic 1 = PIP function is ON 6 MANRED logic 0 = automatic reduction factors(2); logic 1 = manual reduction factors(3) 5 MASPECT(4) main-aspect ratio; 0 = 4 : 3; 1 = 16 : 9 4 SASPECT(4) sub-aspect ratio; 0 = 4 : 3; 1 = 16 : 9 3 MODE(3)(5) PIP mode 2 MODE(2)(5) PIP mode 1 MODE(1)(5) PIP mode 0 MODE(0)(5) PIP mode Notes 1. With PIPON in OFF mode the fast blanking signal is made inactive. All other functions will operate as if the circuit were in operational mode. 2. With MANRED set to logic 0 the reduction factors will be set automatically, dependent on the PIP mode and the aspect ratio bits of main and sub (bits 5 and 4). Table 4 indicates which bits should be set to obtain a certain PIP mode. 3. With MANRED set to logic 1 the calculation of the reduction factors is not carried out and should be set by Register 4 (see Table 9). Only combinations with MANRED set to logic 0 are guaranteed. 4. MASPECT and SASPECT are used in automatic mode (MANRED) to indicate the type of input signals, together with MODE the PIP mode can be set (see Table 4). In manual mode these bits are ignored. 5. The MODE bits set the PIP mode. For the multi-PIP modes the frozen PIPs are set to the 30% grey colour. Once a PIP has been made live it will always display the last video data. Table 6 Register 1; general control register BIT MODE RESULT 7 HPOS(1) logic 0 = left; logic 1 = right 6 VPOS(1) logic 0 = top; logic 1 = bottom 5 MFREEZE(2) logic 0 = main-freeze is OFF; logic 1 = main-freeze is ON 4 SFREEZE(2) logic 0 = sub-freeze is OFF; logic 1 = sub-freeze is ON 3 − not used 2 BCOLPOL(3) border UV polarity; logic 0 = +(B−Y), +(R−Y); logic 1 = −(B−Y), −(R−Y) 1 MVFILT(4) main-vertical filter mode; logic 0 = Mode 0; logic 1 = Mode 1 0 SVFILT(4) sub-vertical filter mode; logic 0 = Mode 0; logic 1 = Mode 1 Notes 1. HPOS and VPOS determine the general location of the sub-PIP on the screen. HPOS only operates in modes SPS, SPL, DP, MP3 and MP4. VPOS only operates in modes SPS and SPL. The default location of the sub-pictures will be left top. 2. MFREEZE will freeze the main-picture, and SFREEZE will freeze the sub-picture selected by the live select bits as in Register 8 (see Table 13). 3. BCOLPOL can invert the border polarity of U and V. 4. MVFILT and SVFILT set the type of vertical filtering for the main and sub-channel. Mode 1 means that diagonal lines are linearized, in Mode 0 this option is switched OFF. This filtering mode only operates with vertical reduction factors 1⁄3 and 1⁄4. February 1995 21 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC Table 7 SAB9075H Register 2; display horizontal fine position register BIT DESCRIPTION(1) MODE 7 − not used 6 − not used 5 DHFP(5) horizontal fine position (64 steps) 4 DHFP(4) horizontal fine position 3 DHFP(3) horizontal fine position 2 DHFP(2) horizontal fine position 1 DHFP(1) horizontal fine position 0 DHFP(0) horizontal fine position Note 1. The display position can be set in steps of 4 pixels/lines and 1 line/field. The offsets on the display position are depicted in Fig.4. Table 8 Register 3; display vertical fine position register BIT DESCRIPTION(1) MODE 7 − not used 6 − not used 5 DVFP(5) vertical fine position (64 steps) 4 DVFP(4) vertical fine position 3 DVFP(3) vertical fine position 2 DVFP(2) vertical fine position 1 DVFP(1) vertical fine position 0 DVFP(0) vertical fine position Note 1. The display position can be set in steps of 4 pixels/lines and 1 line/field. The offsets on the display position are depicted in Fig.4. Table 9 Register 4; reduction factor register BIT DESCRIPTION(1) MODE 7 MREDH(1) main-horizontal reduction factor 6 MREDH(0) main-horizontal reduction factor 5 MREDV(1) main-vertical reduction factor 4 MREDV(0) main-vertical reduction factor 3 SREDH(1) sub-horizontal reduction factor 2 SREDH(2) sub-horizontal reduction factor 1 SREDV(1) sub-vertical reduction factor 0 SREDV(0) sub-vertical reduction factor Note 1. 01 = 1⁄1; 10 = 1⁄2; 11 = 1⁄3; 00 = 1⁄4. February 1995 22 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 10 Register 5; channel select register BIT MODE DESCRIPTION 7 − not used 6 CBSEL(2)(1) channel-border select (maximum 8 channels) 5 CBSEL(1)(1) channel-border select 4 CBSEL(0)(1) channel-border select 3 − not used 2 SLSEL(2)(2) sub-live select (maximum 8 channels) 1 SLSEL(1)(2) sub-live select 0 SLSEL(0)(2) sub-live select Notes 1. With CBSEL one border of the displayed sub-borders can be selected independently of the SLSEL. This only operates when the channel select-border is ON as in Register 8 (see Table 13) and when the selected channel number is displayed. 2. With SLSEL the active sub-live picture can be selected. This only operates when the SFREEZE is OFF as in Register 1 (see Table 6) and when the selected channel is displayed. Background, main and sub-borders are black when they are OFF. The channel-border gets the current sub-border colour when it is switched OFF. The brightness can be set in 4 steps (30%, 50%, 70% and 100%). Eight different colours can be set in accordance with Table 15. Background and main, sub and channel-border colour and brightness handling Registers 6 to 9 (see Tables 11 to 14) handle background and main, sub and channel-border colour and brightness. The borders and background can be set ON and OFF. Table 11 Register 6; main-border control register BIT MODE DESCRIPTION 7 − not used 6 MB0N logic 0 = MB is OFF; logic 1 =MB is ON 5 MBBRT(1) main-border brightness (4 steps) 4 MBBRT(0) main-border brightness 3 − not used 2 MBCOL(2) main-border colour (8 colours) 1 MBCOL(1) main-border colour 0 MBCOL(0) main-border colour February 1995 23 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 12 Register 7; sub-border control register BIT MODE DESCRIPTION 7 − not used 6 SBON logic 0 = SB is OFF; logic 1 = SB is ON 5 SBBRT(1) sub-border brightness (4 steps) 4 SBBRT(0) sub-border brightness 3 − not used 2 SBCOL(2) sub-border colour (8 colours) 1 SBCOL(1) sub-border colour 0 SBCOL(0) sub-border colour Table 13 Register 8; channel-border control register BIT MODE DESCRIPTION 7 − not used 6 CBON logic 0 = CB is OFF; logic 1 = CB is ON 5 CBBRT(1) channel-border brightness (4 steps) 4 CBBRT(0) channel-border brightness 3 − not used 2 CBCOL(2) channel-border colour (8 colours) 1 CBCOL(1) channel-border colour 0 CBCOL(0) channel-border colour Table 14 Register 9; background control register BIT MODE DESCRIPTION 7 FACMODE(1) logic 0 = FM is OFF; logic 1 = FM is ON 6 BGON logic 0 = BG is OFF; logic 1 = BG is ON 5 BGBRT(1) background brightness (4 steps) 4 BGBRT(0) background brightness 3 − not used 2 BGCOL(2) background colour (8 colours) 1 BGCOL(1) background colour 0 BGCOL(0) background colour Note 1. The FACMODE bit controls the factory mode which shows an enlarged background colour as depicted in Fig.17 (BGON must be set). February 1995 24 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 15 Colour table BRIGHTNESS (%)(1) COLOUR TYPE 0 10 30 50 60 70 80 100 40H 50H 60H 70H 47H 57H 67H 77H Blue − − 41H 51H − 61H − 71H Red − − 42H 52H − 62H − 72H Magenta − − 43H 53H − 63H − 73H Green − − 44H 54H − 64H − 74H Cyan − − 45H 55H − 65H − 75H Yellow − − 46H 56H − 66H − 76H Black/white Note 1. The values in are the I2C-bus register values for the Colour Control Registers 6 to 9 (see Tables 11 to 14). The values are hexadecimal values of which the left part indicates the brightness and the right part the colour value. Table 16 Border display PIP MODES MP4 MP8 MP9 FFS SPS SPL DP MP3 MP4 MP7 MP8 MP9 MBON BGON(1) SBON CBON MAINBORDER DISPLAY(2) BACKGROUND DISPLAY OFF OFF − − live BG(3) live BG(3) − − OFF ON − − BGCOL BGCOL − − ON OFF − − MBCOL − − ON ON − − MBCOL BGCOL − − − − OFF − − − live BG(3) − − − ON − − − SBCOL − BG(3) BG(3) live SUBCHANNEL BORDER BORDER DISPLAY(2) DISPLAY BG(3) OFF OFF OFF − OFF ON OFF − BGCOL BGCOL BGCOL − ON OFF ON − MBCOL live BG(3) SBCOL − live live live − BG(3) ON ON ON − MBCOL BGCOL SBCOL − − OFF OFF ON − live BG(3) live BG(3) CBCOL − ON OFF ON − BGCOL BGCOL CBCOL − OFF ON ON − − ON ON ON − live BG(3) BGCOL SBCOL CBCOL SBCOL CBCOL Notes 1. The BGON I2C-bus bit controls the display area outside the PIP and border area, set to ON means that the background gets the BGCOL colour value. 2. The main and sub-border displays are dependent on the I2C-bus switches. 3. ‘Live BG’ means that the original picture is shown. February 1995 25 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 17 Register A; decoder format register BIT MODE RESULT 7 MCOLPOL(1) main-UV polarity; logic 0 = original; logic 1 = inverted 6 MVSPOL(2) main-vertical sync polarity; logic 0 = positive pulse; logic 1 = negative pulse 5 MHSYNC(3) main-horizontal sync selection; logic 0 = burst edge; logic 1 = H − sync 4 MFPOL main-field polarity; inverts field identification window 3 SCOLPOL(1) sub-UV polarity; logic 0 = original; logic 1 = inverted 2 SVSPOL(2) sub-vertical sync polarity; logic 0 = positive pulse; logic 1 = negative pulse 1 SHSYNC(3) sub-horizontal sync selection; logic 0 = burst edge; logic 1 = H − sync 0 SFPOL sub-field polarity, inverts field identification window Notes 1. MCOLPOL and SCOPOL invert the UV video data. 2. MVSPOL and SVSPOL determine the active edge of the Vsync. If VSPOL is logic 0, the positive edge of the Vsync will be taken; if VSPOL is logic 1, the negative edge of the Vsync will be taken. 3. MHSYNC and SHSYNC determine whether the Hsync signal or the burstkey is used as internal horizontal synchronization. active edge of the Vsync occurs when the F-ID signal is logic 0, it will be regarded as the 1st field. If FPOL is logic 0 and an active edge of the Vsync occurs when the F-ID signal is logic 1, it will be regarded as the 2nd field. If FPOL is logic 1 the 1st and 2nd field IDs are changed over. The exact timing of the Vsync in relation to the Hsync reference pulse is depicted in Fig.18. A field identification window determines whether a Vsync is being handled as a 1st field or a 2nd field. This field identification window can be inverted by the FPOL bit. If FPOL is logic 0 and an handbook, full Hpagewidth (external) sync field ID (internal) (number of pixels) 43 389 432 V sync (external) 1st field V sync (external) MBE100 2nd field Fig.18 Vsync timing and field identification. February 1995 26 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 18 Register B; main-acquisition area fine position BIT DESCRIPTION(1) MODE 7 MAAHFP(3) main-acquisition area horizontal fine position 6 MAAHFP(2) main-acquisition area horizontal fine position 5 MAAHFP(1) main-acquisition area horizontal fine position 4 MAAHFP(0) main-acquisition area horizontal fine position 3 MAAVFP(3)(2) main-acquisition area vertical fine position 2 MAAVFP(2)(2) main-acquisition area vertical fine position 1 MAAVFP(1)(2) main-acquisition area vertical fine position 0 MAAVFP(0)(2) main-acquisition area vertical fine position Notes 1. The acquisition area can be adjusted in 16 steps of 2 pixels horizontally and 1 line/field vertically. 2. With MAAVFP a complete field must have been processed before the next Vsync occurs. This is relevant for non-standard signals. Table 19 Register C; sub-acquisition area fine position BIT DESCRIPTION (1) MODE 7 SAAHFP(3) sub-acquisition area horizontal fine position 6 SAAHFP(2) sub-acquisition area horizontal fine position 5 SAAHFP(1) sub-acquisition area horizontal fine position 4 SAAHFP(0) sub-acquisition area horizontal fine position 3 SAAVFP(3)(2) sub-acquisition area vertical fine position 2 SAAVFP(2)(2) sub-acquisition area vertical fine position 1 SAAVFP(1)(2) sub-acquisition area vertical fine position 0 SAAVFP(0)(2) sub-acquisition area vertical fine position Notes 1. The acquisition area can be adjusted in 16 steps of 2 pixels horizontally and 1 line/field vertically. 2. With SAAVFP a complete field must have been processed before the next Vsync occurs. This is relevant for non-standard signals. February 1995 27 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H Auxiliary registers The Auxiliary Registers D to F (see Tables 20 to 22) are implemented to generate I2C-bus controlled signals for circuits which do not have an on-board I2C-bus. Table 20 Register D; Auxiliary Control Register 1 BIT 7 MODE − DESCRIPTION not used 6 − not used 5 HUE(5) hue control (output pin HUE) 4 HUE(4) hue control 3 HUE(3) hue control 2 HUE(2) hue control 1 HUE(1) hue control 0 HUE(0) hue control Table 21 Register E; Auxiliary Control Register 2 BIT MODE DESCRIPTION 7 − not used 6 − not used 5 SAT(5) saturation control (output pin SAT) 4 SAT(4) saturation control 3 SAT(3) saturation control 2 SAT(2) saturation control 1 SAT(1) saturation control 0 SAT(0) saturation control Table 22 Register F; Auxiliary Control Register 3 BIT MODE DESCRIPTION 7 MMUTE data bit directly to output pin MMUTE 6 SMUTE data bit directly to output pin SMUTE 5 − not used 4 − not used 3 − not used 2 − not used 1 − not used 0 − not used February 1995 28 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H External memory Output DACs For the external memory two VDRAMS of type Mitsubishi M5442256 are used. They have a storage capacity of 262144 words of 4-bit each and will be used in parallel. The digital processed signals are converted to analog signals by means of three DACs. The output voltages of these DACs are default set by the DAVrefTU, DAVrefTV and DAVrefTY pins for the TOP-levels. Default signal levels are 1.5 V. The output buffer after each DAC is a PMOS source follower. An overview of the timing to the VDRAM is depicted in Fig.19. Three different timing modes are shown. If the SAB9075 is not in one of these three modes, it is in idle mode in which all the control signals are HIGH. An idle mode takes at least 4 clock periods. Switching from one mode to another is always carried out via this idle mode. For more information see chapter “Test and application information”. HUE and SAT DACs The clock signal shown is an internal clock derived from the PLLs and is approximately 27 MHz. The HUE and SAT DACs are resistor DACs based on a R2R network. They have a direct control from their I2C-bus register and therefore their sample frequency is limited by the I2C-bus frequency. The output voltage is linear with the I2CVDD. Therefore the VDD of this block is a separate pin. Main and sub-ADCs Both main and sub-channels convert the analog input signals to digital signals by three ADCs for each channel. The input levels of the ADCs are equal and can set by the MAVrefT, SAVrefT, MAVrefB, and SAVrefB pins.The reference levels are made internally by a resistor network which divides the analog VDD to a default set of preferred signal levels of 1.5 V. If the application requires a different set of levels the internal resistors can be shunted. External capacitors are required to filter AC components on the reference levels. PLLs and clock generation The SAB9075H has two PLLs on-board, one for the subchannel and one for the main-channel and the display part. The PLLs lock to the input signals MHsync and SHsync. The internal clock frequency is 1 728 times higher which is approximately 27 MHz in a standard NTSC system. The positive edges of the Hsync signals are the driving timing points. For good short term stability they have to be noise/jitter free. The resolution of the ADCs is 6-bit and the sampling is carried out at the system frequency of 27 MHz. The bias current Ibias is made internally but can be increased or decreased. The inputs should be AC-coupled and an internal clamping circuit will clamp the input to MAVrefB and SAVrefB for the luminance channels and to MAV refT + MAV refB LSB ----------------------------------------------------- + -----------2 2 SAV refT + SAV refB LSB --------------------------------------------------- + -----------2 2 for the chrominance channels. The clamping starts at the active edge of the burstkey. For more information see chapter “Test and application information”. February 1995 29 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H handbook, full pagewidth CLOCK RAS CAS refresh cycle CLOCK RAS CAS AD0 to AD8 ROW COLUMN COLUMN COLUMN COLUMN COLUMN WE DAI0 to DAI7 write cycle (SUB or MAIN) CLOCK RAS CAS AD0 to AD8 ROW COLUMN WE DT read cycle SC DAO0 to DAO7 MBE101 SC cycles Fig.19 VDRAM timing. February 1995 30 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 V ∆VDD supply voltage variation − 0.2 V Tstg storage temperature −25 +150 °C Tamb operating ambient temperature 0 70 °C Vesd electrostatic discharge handling − − V Ptot total power dissipation − 1.5 W THERMAL CHARACTERISTICS SYMBOL Rthj-a PARAMETER thermal resistance from junction to ambient in free air QUALITY SPECIFICATION In accordance with SNW-FQ-611, Part E, dated 14 December 1992. February 1995 31 VALUE UNIT 38 K/W Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H CHARACTERISTICS VDD = 5.0 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD positive supply voltage 4.5 5.0 5.5 V VSS negative supply voltage − 0 − V ∆VDD maximum voltage difference between all positive supply pins − 0 100 mV ∆VSS maximum voltage difference between all negative supply pins − 0 100 mV IDDQ quiescent current digital positive supply pins − 2 tbf µA MPIVDDA supply current PLL main − 2.5 tbf mA SPIVDDA supply current PLL sub − 2.5 tbf mA MAIVDDA supply current 3 main-ADCs − 36 tbf mA SAIVDDA supply current 3 sub-ADCs − 36 tbf mA DIVDDA supply current 3 display DACs − 18 tbf mA I2CVDD supply current HUE and SAT DACs − 2.5 5 mA Itot total supply current tbf 220 tbf mA note 1 note 2 Converter and clamping AVrefT top reference voltage note 3 1.0 1.9 2.0 V AVrefB bottom reference voltage note 3 0 0.4 1.0 V Rinref input resistance VrefT to VrefB note 3; 1 ADC tbf 860 tbf Ω VI DC input voltage VrefB − VrefT V Vi AC input voltage (peak-to-peak value) 1.0 1.5 − V Ri input resistance clamping OFF 1 − − MΩ RiY input resistance for Y channel clamping ON − 200 − Ω RiV input resistance for V channel clamping ON − 800 − Ω RiU input resistance for U channel clamping ON − 800 − Ω Ci input capacitance − 15 − pF Res resolution − 6 − bit fs sample frequency rate − 27 − MHz note 4 DNL differential non-linearity −1.0 − +1.0 LSB INL integral non-linearity −1.0 − +1.0 LSB Vos input offset voltage −1.0 − +1.0 LSB αcs channel separation within channel tbf 40 − dB to other channel tbf 40 − dB tbf 40 − dB PSRR power supply rejection ratio February 1995 32 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SYMBOL PARAMETER SAB9075H CONDITIONS MIN. TYP. MAX. UNIT TDclamp delay burstkey edge to clamping start − 0 − µs Tclamp duration of clamping − 2.33 − µs VclampY clamping voltage level Y − Vs − V V ADout = 0H VclampU clamping voltage level U ADout = 20H − 0.5 VT+B − VclampV clamping voltage level V ADout = 20H − 0.5 VT+B − V Digital-to-analog converter VrefT top reference voltage (Y, U and V) note 3 1.0 1.5 2.0 V Rinref input resistance VrefT to VrefB note 3; 1 DAC tbf 1.0 tbf kΩ Vo(max) maximum output voltage VrefB − VrefT V RL(min) minimum load resistance 10 − − kΩ CL(max) maximum load capacitance − 50 − pF Res resolution − 7 − bit fs sample frequency rate − 27 − MHz note 4 DNL differential non-linearity −0.5 − +0.5 LSB INL integral non-linearity −1.0 − +1.0 LSB αcs channel separation tbf 40 − dB PSRR power supply rejection ratio tbf 40 − dB VSS − VDD V Digital-to-analog converter HUE/SAT Vo output voltage RL(min) minimum load resistance 100 − − kΩ CL(max) maximum load capacitance − 50 − pF Res resolution − 6 − bit note 2 DNL differential non-linearity −1.0 − +1.0 LSB INL integral non-linearity −1.0 − +1.0 LSB PSRR power supply rejection ratio − 0 − dB note 2 PLL and clock generation; note 4 VTOP TOP-level input voltage 2.5 − PVDD V VLOW LOW-level input voltage − − 0.5 V Vslice slicing voltage level below TOP 0.45 1.0 2.0 V fPLL input frequency 14750 15734 17250 Hz Notes 1. Digital clocks are silent and analog bias current is zero. 2. The HUE and SAT DACs are based on a R2R ladder network as describe in the section “HUE and SAT DACs”. The maximum output sample frequency is determined by the I2C-bus. 3. The input configuration of the ADCs is depicted in Fig.20. The minimum difference AVrefT − AVrefB should be larger than 1.0 V. The reference voltages can be calculated as follows: 1.9 0.4 V refT = AV DD × -------- V ; V refB = AV DD × -------- V 5.0 5.0 4. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see section “PLLs and clock generation”. February 1995 33 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H DC CHARACTERISTICS FOR DIGITAL PART All VDD pins = 4.5 to 5.5 V; Tamb = −20 to +75 °C; unless otherwise specified. SYMBOL VIH VIL PARAMETER HIGH level input voltage LOW level input voltage CONDITIONS MIN. TYP. MAX. UNIT HPF01 70 − − %VDD HPP01 70 − − %VDD HUP07 80 − − %VDD IOI41 70 − − %VDD HPF01 − − 30 %VDD HPP01 − − 30 %VDD HUP07 − − 20 %VDD IOI41 − − 30 %VDD Vhys hysteresis voltage HUP07 − 33 − %VDD VOH HIGH level output voltage OPF20; IOL = −2 mA; VDD = 4.5 V 4.4 − − V SPF20; IOL = −2 mA; VDD = 4.5 V 4.4 − − V VOL LOW level output voltage IOI41; IOL = +2 mA; VDD = 4.5 V − − 0.15 V OPF20; IOL = +2 mA; VDD = 4.5 V − − 0.15 V SPF20; IOL = +2 mA; VDD = 4.5 V − − 0.15 V HPF01 − 0.1 1 µA HPP01 − 0.1 1 µA ILI input leakage current ILOZ three-state output leakage current IOI41; VDD = 5.5 V − 0.2 5.0 µA Rpu internal pull up resistor HUP07 17 − 134 kΩ AC CHARACTERISTICS FOR DIGITAL PART VDD = 4.5 5.5 V; Tamb = −20 to +75 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT fsys system frequency note 1 − 27 30 MHz tr rise time VDD = 4.5 V − 6 25 ns tf fall time VDD = 4.5 V − 6 25 ns Note 1. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see section “PLLs and clock generation”. February 1995 34 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H A modification of these reference voltages can be achieved by external shunting. TEST AND APPLICATION INFORMATION Fig.20 shows how the ADCs and the DACs can be connected in the application. The ADC reference voltages are the same for all Y/U/V channels which means that their input levels need to be the same. The DAC voltage references can be set separately for Y/U/V channels. These reference voltages can be modified by shunting. The generation of the reference voltages is carried out internally and they have to be externally decoupled for AC signals. For all ADCs and DACs the internal resistor division is such that a maximum signal voltage level of 1.5 V is obtained. For the ADCs there is a DC offset voltage of 0.4 V. The output buffers of the DACS are PMOS source followers with a minimum output load of 10 kΩ. handbook, full pagewidth MAV DDA DAVDDA 3R top R top MAV refT MY DAV refTY ADC DAVrefTU MU ADC MV ADC DAV refTV DY DAC MAV refB MAV SSA SAV DDA R bottom R top DU VIDEO SIGNAL PROCESSING DAC DV SAV refT SY DAC ADC DAV SSA SU ADC SV ADC SAV refB SAV SSA R bottom MGC001 Fig.20 Analog application diagram ADCs and DACs. February 1995 35 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H handbook, full pagewidth TMS44C250 4 4 4 0 V or 5 V 5V 5V 4 5V 9 TMS44C250 SCL 5V DAI bias DAVDDA DAVSSA MPVDDA MPVDDD MPVSSD DAVrefTV SPIbias 5V DBF SAB9075H SPV DDA SPV SSA SPV DDD SPV SSD 5V SAVDDD MAVSSA MAVDDA MAVrefB MAVrefT MV sync MH sync MV MU MMUTE MY SMUTE I2 CVDD SAT HUE SY SU SV SH sync SAVrefB SVsync SAVSSA SAVrefT SAIbias SAVDDA SAVSSD analog U output DV analog V output DAVDDD DAVSSD 5V MAVDDD MAVSSD 5V TDA8315T CVBS/Y CVBS/Y CVBS/Y sub-channel input CVBS/Y main-channel input Fig.21 Application diagram. February 1995 VOUT V HOUT U Y 5V sub-channel mute output SAT HUE SAT HUE U V Y VOUT HOUT 5V 5V main-channel mute output MGC053 TDA8315T 36 fast blanking control output analog Y output DY DU MAI bias 5V 5V DAVrefTY DAVrefTU MPVSSA 5V SDA A0 SCL POR MVDDD MVSSD SVDDD SVSSD TM1 TM2 TC TM0 MTCLK DT STCLK WE RAS SC CAS DAI4 to DAI7 DAI0 to DAI3 AD0 to AD8 DAO0 to DAO3 MPI bias DAO4 to DAO7 V SSS V DDD SDA Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2 c y X 80 A 51 81 50 ZE e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 31 100 detail X 30 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 20.1 19.9 14.1 13.9 0.65 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.15 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT317-2 February 1995 EUROPEAN PROJECTION 37 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC SAB9075H applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. SOLDERING Plastic quad flat-packs Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C. BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.) A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. February 1995 38 Philips Semiconductors Preliminary specification Picture-in-Picture (PIP) controller for NTSC NOTES February 1995 39 SAB9075H Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. 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(021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (081)730-5000, Fax. (081)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD36 © Philips Electronics N.V. 1994 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 533061/1500/01/pp40 Document order number: Date of release: February 1995 9397 745 30011