AN55659 Migrating from CY14B101L/STK14CA8 to CY14B101LA Author: Ravi Prakash Associated Project: No Associated Part Family: CY14B101L/STK14CA8, CY14B101LA Related Application Notes: None AN55659 gives information for migrating from the nvSRAM parts CY14B101L/STK14CA8 to the CY14B101LA. This application note also lists the parameter differences between the parts and the design considerations when converting existing applications from CY14B101L/STK14CA8 to CY14B101LA. Table 2. Feature Set Comparison Introduction Cypress CY14B101LA is a 3 V, 1 Mbit (128 K x 8) nvSRAM in 0.13 micron technology. This part is functionally equivalent to CY14B101L/STK14CA8 (0.25 µ) and is intended as a drop in replacement. (STK14CA8 is the Simtek part number for CY14B101L.) This application note highlights the differences between the CY14B101L/STK14CA8 and the CY14B101LA and the parameters that must be considered while migrating. Overview The following tables compare the features and parameters of the two parts. As shown in Table 1, the 1 Mbit nvSRAM is available in x8 and x16 configurations. Table 1. Part Number Description Description Original Part Number Replacement Part Number 128 Kb x 8 CY14B101L/STK14CA8 CY14B101LA 1 Mbit nvSRAM is also available in x16 I/O option (CY14B101NA) for new applications. Feature Set Both the parts share the same overall feature set and are available in the operation speed bins as given in Table 2. CY14B101L/ STK14CA8 CY14B101LA AutoStore Available Available Software STORE Available Available Hardware STORE Available Available AutoStore Enable/Disable Available Available Software RECALL Available Available Feature Set - 20 ns 25 ns 25 ns 35 ns 45 ns 45 ns STORE Cycles 200,000 1,000,000 Data Retention 20 years at 55 °C 20 years at 85 °C Speed Operating Temperature Range While CY14B101L/STK14CA8 is available in both commercial and industrial temperature ranges, CY14B101LA is offered only in the industrial temperature range. Table 3. Operating Temperature Range Comparison Operating Temperature Range www.cypress.com CY14B101L/ STK14CA8 CY14B101LA Commercial (0 to 70 °C) Available Not Available Industrial (–40 to 85 °C) Available Available Document No. 001-55659 Rev. *D 1 Migrating from CY14B101L/STK14CA8 to CY14B101LA Parameters Packages CY14B101LA is pin compatible with CY14B101L/STK14CA8 and is available in the same packages and pin configurations, as well as in additional packages. Table 4. Packages Comparison CY14B101L/ STK14CA8 CY14B101LA 32-pin SOIC Available Available 48-pin SSOP Available Available 44-pin TSOPII Not Available Available Package The CY14B101LA is a drop in replacement for CY14B101L/STK14CA8 and requires no changes in the application board in most applications. However, the differences in parameters should be considered before replacing one part with the other. Table 5 lists the differences in parameters between CY14B101L/STK14CA8 and CY14B101LA. Table 5. Parameter Comparison CY14B101L/STK14CA8 Parameter Description CY14B101LA Speed Unit Min Max Min Max 20 ns - - - 70 25 ns - 70 - 70 35 ns - 60 - - 45 ns - 55 - 52 - - 3 - 10 DC Parameters ICC1 ICC2 Average VCC Current mA Average VCC Current during STORE mA ICC3 ICC4 ISB VCAP Average VCC Current at - tRC = 200 ns, 3 V, 25 °C Average VCAP Current 10 (typ) - - VCC Standby Current - - Storage Capacitor - during AutoStore Cycle 35 (typ) 3 - 3 - 17 to 120 5 mA 5 mA 61 to 180 uF AC Switching Parameters Read and Write cycle parameters are identical AutoStore / Power-Up RECALL Parameters tSTORE tDELAY VHDIS tLZHSB tHHHD STORE Cycle Duration Time Allowed to Complete SRAM Write Cycle - - 12.5 - 8 20 ns - - - 20 25 ns 1,000 70,000 - 25 35 ns 1,000 70,000 - - 45 ns 1,000 70,000 - 25 ms ns ������ Output Disable Voltage HSB - Not specified - 1.9 V - Not specified - 5 us ������ High Active Time HSB - Not specified - 500 ns Address Hold Time - 0 - ns ������ To Output Active Time HSB Software Controlled STORE/RECALL Cycle Parameters tHA www.cypress.com 1 Document No. 001-55659 Rev. *D - 2 Migrating from CY14B101L/STK14CA8 to CY14B101LA CY14B101L/STK14CA8 Parameter tRECALL tSS Description CY14B101LA Speed Unit Min Max Min Max RECALL Duration - - 120 - 200 us Soft Sequence Processing Time - - 70 - 100 us Hardware STORE Cycle Parameters tDHSB ������ HSB LOW to STORE Busy ������ HSB To Output Active Time when write latch not set - Not specified - 25 (tDELAY) ns - Not specified - 25 ns Critical Considerations The impact of the differences in CY14B101LA with respect to the CY14B101L/STK14CA8 in existing applications are discussed in this section. System designers are recommended to review the detailed datasheets when migrating to the new part. DC Parameters ICC1 (Average current at full speed) is the same in CY14B101LA and hence power supply design in applications with CY14B101L/STK14CA8 would require no changes when replacing the nvSRAM with the CY14B101LA in spite of the higher values in the lower speed / higher standby current. The critical parameter to consider is the VCAP. VCAP VCAP is the capacitor that provides the required charge for AutoStore to complete NV store of the SRAM data during power down. The required capacitor range is different for the two parts. parts as replacement (since 35 ns speed grade is not available in the CY14B101LA). AutoStore/Power-Up RECALL Parameters The AutoStore/Power-Up RECALL parameters are better in the CY14B101LA compared to the CY14B101L/STK14CA8 and hence applications would not require any changes during migration. The improvements are listed under the Details of Improvement section. Software Controlled STORE/RECALL Cycle Parameters The Software RECALL time (tRECALL) and Soft sequence processing time (tSS) are higher in CY14B101LA as described in Table 7. Table 7. Software Controlled STORE/RECALL Cycle Parameters Comparison Description CY14B101L/ STK14CA8 CY14B101LA tRECALL 120 µs 200 µs tSS 70 µs 100 µs Table 6. VCAP Comparison Description CY14B101L/ STK14CA8 CY14B101LA VCAP 17 µF to 120 µF 61 µF to 180 µF Voltage Rating 6V 4V Therefore, in any existing application which uses a capacitor value outside the overlapping range (61 µF to 120 µF) the impact of capacitor dimensions needs to be considered while changing to the new capacitor. The capacitor voltage rating requirement is lower in CY14B101LA as the VCAP voltage is not boosted above the VCC voltage as done in the CY14B101L/STK14CA8. Note The capacitor range is the absolute value of the capacitor, net of tolerence. Note In the CY14B101L/STK14CA8, reads/writes are only inhibited after tSS and only for the STORE or RECALL command. In the CY14B101LA, reads/writes are inhibited after tDELAY and remain disabled until the end of the soft command (tSS or tRECALL or tSTORE). This is an improvement but applications where reads/writes are performed within the tSS time after initiating a software sequence would require firmware change to include the wait time. Software Sequence AC Switching Parameters The AC parameters are identical between the CY14B101LA and the CY14B101L/STK14CA8 for identical speed grades. For replacing 35 ns speed parts, choose the 25 ns speed www.cypress.com This difference could require firmware change in the existing application to increase the controller wait state when software RECALL or AutoStore Enable/Disable cycles are initiated. The CY14B101LA has been designed to be compatible with the CY14B101L/STK14CA8 in the software sequence modes. Hence, the same Software STORE and RECALL Document No. 001-55659 Rev. *D 3 Migrating from CY14B101L/STK14CA8 to CY14B101LA address sequences in the CY14B101L/STK14CA8 works in CY14B101LA, requiring no firmware change. Hardware STORE Cycle Parameters The Hardware STORE parameters are improved in the CY14B101LA and hence applications would not require any changes during migration. The improvements are listed under the Details of Improvement section. No changes are required in applications. changes are improvements from the original part specification and should be considered as added benefits in your system while migrating to the new part number. tDELAY STORE Cycles If a write latch is set and the HSB pin is pulled low, CY14B101L/STK14CA8 enables 1 µs to 70 µs time for write operations to complete before STORE operation begins and reads and writes are inhibited. This potentially enables inadvertent data to be written to the nvSRAM during the tDELAY duration. The NV STORE cycles endurance in the CY14B101LA is improved five times compared to the older technology giving it one million STORE cycles against 200 K STORE cycles in the older part. Note Write Latch: When a write operation is done, a ‘write latch’ is set internally. When HSB is pulled low, nvSRAM checks this write latch before initiating a STORE. This is done to prevent any unnecessary loss of endurance cycles. Data Retention In CY14B101LA, the tDELAY parameter enables only one write cycle time for any ongoing write to complete after HSB pin is pulled low. This improvement provides better security from inadvertent write operations. The Data Retention in CY14B101LA part is improved from the older technology part. The CY14B101LA has data retention of 20 years at 85 °C against the CY14B101L/STK14CA8 data retention of 20 years at 55 °C. This would translate to over 20 times improvement in data retention at the same temperatures. Details of Improvement Hardware STORE Related Improvements HSB P i n ( H a r dw a r e S T O R E B u s y Indication/Hardw are STORE Initiation) The HSB pin of the nvSRAM is an open drain I/O pin used to indicate or initiate a STORE operation. When a STORE operation is in progress, nvSRAM pulls the HSB pin low to indicate that the device is busy and cannot be accessed for read/write operation. During normal operation, the HSB pin can be pulled low to initiate a Hardware STORE operation. As shown in Table 5, several timing parameters related to the HSB pin input and output have changed from CY14B101L/STK14CA8 to CY14B101LA. All of these Also, if HSB pin is pulled low externally for a minimum of tPHSB time on CY14B101LA, the output driver of HSB pin pulls the pin low only indicating a STORE operation within 20 to 25 ns (tDELAY). This parameter for HSB low to STORE busy is not specified in the CY14B101L/STK14CA8. (See Figure 1 and Figure 2) HSB L O W W h e n W r i t e L a t c h N o t S e t If no writes are performed since the last STORE/RECALL operation, STORE operation does not start when HSB is pulled low. However, the HSB pin is still internally pulled low for 1 µs to 70 µs (tDELAY) time in the CY14B101L/ STK14CA8 device. CY14B101LA device does not pull the HSB pin low internally if write latch is not set. This improvement prevents the possibility of being in an infinite loop when HSB pins of two nvSRAM devices are ganged. Figure 1. CY14B101L/STK14CA8: AC Parameters Related to HSB Figure 2. CY14B101LA: AC Parameters Related to HSB www.cypress.com Document No. 001-55659 Rev. *D 4 Migrating from CY14B101L/STK14CA8 to CY14B101LA Write Latch Set Write Latch Not Set Power-Up Recall Related Improvements Additional parameters are specified in CY14B101LA, such as HSB Output Disable Voltage (VHDIS), HSB To Output Active Time (tLZHSB), and HSB High Active Time (tHHHD), which helps in system design. See Figure 3 and Figure 4 for the definition of the additional specs in power-up. Also, note that HSB remains low until the end of the power-up in the new part. This would guard against the system inadvertently thinking the part has completed the boot up prior to real completion. Figure 3. CY14B101L/STK14CA8: Power-Up Recall www.cypress.com Document No. 001-55659 Rev. *D 5 Migrating from CY14B101L/STK14CA8 to CY14B101LA Figure 4. CY14B101LA: Power-Up Recall Summary The application note discusses the differences between CY14B101LA in the latest 0.13 micron technology and CY14B101L/STK14CA8 in the 0.25 micron technology. Several parameters related to HSB and power-up have improved / specified in the new device enabling faster device response, greater data security, and ease of design. www.cypress.com CY14B101LA is pin compatible and can replace the CY14B101L/STK14CA8 device with no changes in application board in most applications. Value of VCAP in the existing design and the controller wait state during software RECALL and AutoStore Enable/Disable cycles need to be considered while migrating. Document No. 001-55659 Rev. *D 6 Migrating from CY14B101L/STK14CA8 to CY14B101LA Document History Document Title: Migrating from CY14B101L/STK14CA8 to CY14B101LA – AN55659 Document Number: 001-55659 Revision ECN Orig. of Change Submission Date Description of Change ** 2773089 PSR 10/01/2009 New Spec. *A 3016464 PSR 09/01/2010 Changed STORE cycles of CY14B101LA in Table 2 to 1,000,000 and added a paragraph under Critical Consideration indicating the improvement. *B 3556305 GVCH 03/20/2012 Updated template Changed title from “Converting” to “Migrating” Text and drawing updates for more clarity. No change in technical content. *C 4168519 GVCH 10/21/2013 Obsolete document. *D 4221941 GVCH 12/16/2013 Document reactivated. Updated in new template. www.cypress.com Document No. 001-55659 Rev. *D 7 Migrating from CY14B101L/STK14CA8 to CY14B101LA Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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