INTEGRATED CIRCUITS DATA SHEET UDA1334BTS Low power audio DAC Preliminary specification File under Integrated Circuits, IC01 2000 Feb 07 Philips Semiconductors Preliminary specification Low power audio DAC UDA1334BTS CONTENTS 9 LIMITING VALUES 10 HANDLING 11 THERMAL CHARACTERISTICS 12 QUALITY SPECIFICATION 13 DC CHARACTERISTICS 14 AC CHARACTERISTICS 2.0 V supply voltage 3.0 V supply voltage Timing 11 FEATURES 1.1 1.2 1.3 1.4 General Multiple format data interface DAC digital sound processing Advanced audio configuration 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 14.1 14.2 14.3 5 QUICK REFERENCE DATA 15 APPLICATION INFORMATION 6 BLOCK DIAGRAM 16 PACKAGE OUTLINE 7 PINNING 17 SOLDERING 8 FUNCTIONAL DESCRIPTION 17.1 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 System clock Interpolation filter Noise shaper Filter stream DAC Power-on reset Feature settings Digital interface format select Mute control De-emphasis control Power control and sampling frequency select Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 2000 Feb 07 17.2 17.3 17.4 17.5 2 18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS Philips Semiconductors Preliminary specification Low power audio DAC 1 1.1 UDA1334BTS FEATURES General • 1.8 to 3.6 V power supply voltage • Integrated digital filter plus DAC • Supports sample frequencies from 8 to 100 kHz • Automatic system clock versus sample rate detection • Low power consumption • No analog post filtering required for DAC 2 • Slave mode only applications This audio DAC is excellently suitable for digital audio portable application, such as portable MD, MP3 and DVD players. • Easy application • SSOP16 package. 1.2 Multiple format data interface 3 • I2S-bus and LSB-justified format compatible DAC digital sound processing The UDA1334BTS has basic features such as de-emphasis (at 44.1 kHz sampling rate) and mute. • Digital de-emphasis for 44.1 kHz sampling rate • Mute function. 1.4 GENERAL DESCRIPTION The UDA1334BTS supports the I2S-bus data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits. • 1fs input data rate. 1.3 APPLICATIONS Advanced audio configuration • High linearity, wide dynamic range and low distortion • Standby or Sleep mode in which the DAC is powered down. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION UDA1334BTS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 2000 Feb 07 3 Philips Semiconductors Preliminary specification Low power audio DAC 5 UDA1334BTS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1.8 2.0 3.6 Supplies VDDA DAC analog supply voltage VDDD digital supply voltage IDDA DAC analog supply current IDDD digital supply current V 1.8 2.0 3.6 V normal operating mode − 2.3 − mA Sleep mode − 125 − µA normal operating mode − 1.4 − mA clock running − 250 − µA no clock running − 20 − µA −40 − +85 °C at 0 dB (FS) digital input; note 1 − 600 − mV Sleep mode Tamb ambient temperature Digital-to-analog converter (VDDA = VDDD = 2.0 V) Vo(rms) output voltage (RMS value) (THD + N)/S total harmonic distortion-plus-noise to signal ratio S/N αcs signal-to-noise ratio fs = 44.1 kHz; at 0 dB − −80 − dB fs = 44.1 kHz; at −60 dB; A-weighted − −37 − dB fs = 96 kHz; at 0 dB − −75 − dB fs = 96 kHz; at −60 dB; A-weighted − −35 − dB fs = 44.1 kHz; code = 0; A-weighted − 97 − dB fs = 96 kHz; code = 0; A-weighted − 95 − dB − 100 − dB at 0 dB (FS) digital input; note 1 − 900 − mV fs = 44.1 kHz; at 0 dB − −90 − dB fs = 44.1 kHz; at −60 dB; A-weighted − −40 − dB fs = 96 kHz; at 0 dB − −85 − dB fs = 96 kHz; at −60 dB; A-weighted − −38 − dB fs = 44.1 kHz; code = 0; A-weighted − 100 − dB fs = 96 kHz; code = 0; A-weighted − 98 − dB − 100 − dB at 2.0 V supply voltage − 7.4 − mW at 3.0 V supply voltage − 17 − mW clock running − 0.75 − mW no clock running − 0.3 − mW channel separation Digital-to-analog converter (VDDA = VDDD = 3.0 V) Vo(rms) output voltage (RMS value) (THD + N)/S total harmonic distortion-plus-noise to signal ratio S/N αcs signal-to-noise ratio channel separation Power dissipation (at fs = 44.1 kHz) P power dissipation playback mode Sleep mode; at 2.0 V supply voltage Note 1. The DAC output voltage scales proportionally to the power supply voltage. 2000 Feb 07 4 Philips Semiconductors Preliminary specification Low power audio DAC 6 UDA1334BTS BLOCK DIAGRAM VSSD VDDD handbook, full pagewidth 4 BCK WS DATAI 1 2 3 5 DIGITAL INTERFACE DE-EMPHASIS UDA1334BTS SYSCLK MUTE DEEM PCS 6 7 8 11 INTERPOLATION FILTER 9 SFOR1 SFOR0 10 NOISE SHAPER VOUTL DAC 14 13 15 VDDA VSSA Fig.1 Block diagram. 2000 Feb 07 16 DAC 5 12 Vref(DAC) VOUTR MGL964 Philips Semiconductors Preliminary specification Low power audio DAC 7 UDA1334BTS PINNING SYMBOL PIN PAD TYPE DESCRIPTION BCK 1 5 V tolerant digital input pad; note 1 bit clock input WS 2 5 V tolerant digital input pad; note 1 word select input DATAI 3 5 V tolerant digital input pad; note 1 serial data input VDDD 4 digital supply pad digital supply voltage VSSD 5 digital ground pad digital ground SYSCLK 6 5 V tolerant digital input pad; note 1 system clock input SFOR1 7 5 V tolerant digital input pad; note 1 serial format select 1 MUTE 8 5 V tolerant digital input pad; note 1 mute control DEEM 9 5 V tolerant digital input pad; note 1 de-emphasis control PCS 10 3-level input pad; note 2 power control and sampling frequency select SFOR0 11 digital input pad; note 2 serial format select 0 Vref(DAC) 12 analog pad DAC reference voltage VDDA 13 analog supply pad DAC analog supply voltage VOUTL 14 analog output pad DAC output left VSSA 15 analog ground pad DAC analog ground VOUTR 16 analog output pad DAC output right Notes 1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages this is maximum 3.3 V tolerant. 2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a maximum of 0.5 V above that level. handbook, halfpage BCK 1 16 VOUTR WS 2 15 VSSA DATAI 3 VDDD 4 14 VOUTL UDA1334BTS VSSD 5 13 VDDA 12 Vref(DAC) SYSCLK 6 11 SFOR0 SFOR1 7 10 PCS MUTE 8 9 DEEM MGL963 Fig.2 Pin configuration. 2000 Feb 07 6 Philips Semiconductors Preliminary specification Low power audio DAC 8 UDA1334BTS Table 2 FUNCTIONAL DESCRIPTION 8.1 System clock Example using a 12.228 MHz system clock CLOCK MODE SAMPLING FREQUENCY 128fs 96 kHz 192fs 64 kHz(1) The UDA1334BTS operates in slave mode only; this means that in all applications the system must provide the system clock and the digital audio interface signals (BCK and WS). The system clock must be locked in frequency to the digital interface signals. The UDA1334BTS automatically detects the ratio between the SYSCLK and WS frequencies. 256fs 48 kHz 384fs 32 kHz 512fs 24 kHz 768fs 16 kHz Note 1. This mode can only be supported for power supply voltages down to 2.4 V. For lower voltages, in 192fs mode the sampling frequency should be limited to 55 kHz. The BCK clock can be up to 64fs, or in other words the BCK frequency is 64 times the Word Select (WS) frequency or less: fBCK ≤ 64 × fWS. Remarks: 8.2 1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface The interpolation digital filter interpolates from 1fs to 64fs by cascading FIR filters (see Table 3). 2. For LSB-justified formats it is important to have a WS signal with a duty factor of 50%. Table 3 The modes which are supported are given in Table 1. Table 1 Interpolation filter Supported sampling ranges Interpolation filter characteristics ITEM CONDITION VALUE (dB) Pass-band ripple 0 to 0.45fs ±0.02 >0.55fs −50 0 to 0.45fs >114 Stop band CLOCK MODE SAMPLING RANGE 768fs 8 to 55 kHz 512fs 8 to 100 kHz 8.3 384fs 8 to 100 kHz 256fs 8 to 100 kHz 192fs 8 to 100 kHz(1)(2) 128fs 8 to 100 kHz(2) The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC). Dynamic range Notes 1. This mode can only be supported for power supply voltages down to 2.4 V. For lower voltages, in 192fs mode the sampling frequency should be limited to 55 kHz. 2. Not supported in the low sampling frequency mode. An example is given in Table 2 for a 12.228 MHz system clock input. 2000 Feb 07 7 Noise shaper Philips Semiconductors Preliminary specification Low power audio DAC 8.4 UDA1334BTS Filter stream DAC 8.5 The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post-filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. Power-on reset The UDA1334BTS has an internal Power-on reset circuit (see Fig.3) which resets the test control block. The reset time (see Fig.4) is determined by an external capacitor which is connected between pin Vref(DAC) and ground. The reset time should be at least 1 µs for Vref(DAC) < 1.25 V. When VDDA is switched off, the device will be reset again for Vref(DAC) < 0.75 V. During the reset time the system clock should be running. The output voltage of the FSDAC scales proportionally with the power supply voltage. 3.0 VDDD handbook, halfpage (V) 1.5 0 t handbook, halfpage 3.0 V 3.0 VDDA VDDA 13 (V) 25 kΩ Vref(DAC) C1 > 10 µF 1.5 RESET CIRCUIT 12 0 25 kΩ t UDA1334BTS 3.0 Vref(DAC) MGL985 (V) 1.5 1.25 0.75 0 >1 µs t MGL984 Fig.3 Power-on reset circuit. 2000 Feb 07 Fig.4 Power-on reset timing. 8 Philips Semiconductors Preliminary specification Low power audio DAC 8.6 UDA1334BTS 8.6.4 Feature settings The features of the UDA1334BTS can be set by control pins SFOR1, SFOR0, MUTE, DEEM and PCS. 8.6.1 Pin PCS is a 3-level pin and is used to set the mode of the UDA1334BTS. The definition is given in Table 7. DIGITAL INTERFACE FORMAT SELECT Table 7 The digital audio interface formats (see Fig.5) can be selected via the pins SFOR1 and SFOR0 as shown in Table 4. Table 4 SFOR0 LOW LOW I2S-bus input LOW HIGH LSB-justified 16 bits input HIGH LOW LSB-justified 20 bits input HIGH HIGH LSB-justified 24 bits input Mute control FUNCTION LOW mute off HIGH mute on 8.6.3 DE-EMPHASIS CONTROL De-emphasis can be switched on for fs = 44.1 kHz by setting pin DEEM at HIGH level. The function description of pin DEEM is given in Table 6. Table 6 De-emphasis control DEEM FUNCTION LOW de-emphasis off HIGH de-emphasis on Remark: the de-emphasis function in only supported in the normal operating mode, not in the low sampling frequency mode. 2000 Feb 07 normal operating mode MID low sampling frequency mode Power-down or Sleep mode The low sampling frequency mode is required to have a higher oversampling rate in the noise shaper in order to improve the signal-to-noise ratio. In this mode the oversampling ratio of the noise shaper will be 128fs instead of 64fs. The output signal can be soft muted by setting pin MUTE to HIGH level as shown in Table 5. MUTE FUNCTION LOW HIGH INPUT FORMAT MUTE CONTROL Table 5 PCS function definition PCS Data format selection SFOR1 8.6.2 POWER CONTROL AND SAMPLING FREQUENCY SELECT 9 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2 >=8 3 2 3 MSB B2 1 >=8 BCK DATA MSB B2 MSB I2S-BUS FORMAT WS LEFT Philips Semiconductors 1 Low power audio DAC handbook, full pagewidth 2000 Feb 07 RIGHT LEFT WS RIGHT 16 15 1 16 B15 LSB MSB 2 15 2 1 BCK DATA MSB B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS 10 WS LEFT 20 RIGHT 19 18 17 16 15 1 20 B19 LSB MSB 2 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS WS LEFT 24 23 22 21 20 RIGHT 19 18 17 16 15 2 1 24 B23 LSB MSB 23 22 21 20 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB Preliminary specification Fig.5 Digital audio formats UDA1334BTS MGS752 LSB-JUSTIFIED FORMAT 24 BITS Philips Semiconductors Preliminary specification Low power audio DAC UDA1334BTS 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT − 4.0 V maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling voltage human body model −2000 +2000 V machine model −200 +200 V output short-circuited to VSSA − 450 mA output short-circuited to VDDA − 300 mA VDD supply voltage Txtal(max) Isc(DAC) note 1 short-circuit current of DAC note 2 Note 1. All supply connections must be made to the same power supply. 2. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted. 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE UNIT 145 K/W thermal resistance from junction to ambient in free air 12 QUALITY SPECIFICATION In accordance with “SNW-FQ-611-E”. 13 DC CHARACTERISTICS VDDD = VDDA = 2.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA DAC analog supply voltage note 1 1.8 2.0 3.6 V VDDD digital supply voltage 1.8 2.0 3.6 V IDDA DAC analog supply current normal operating mode at 2.0 V supply voltage − 2.3 − mA at 3.0 V supply voltage − 3.5 − mA at 2.0 V supply voltage − 125 − µA at 3.0 V supply voltage − 175 − µA note 1 Sleep mode 2000 Feb 07 11 Philips Semiconductors Preliminary specification Low power audio DAC SYMBOL IDDD PARAMETER digital supply current UDA1334BTS CONDITIONS MIN. TYP. MAX. UNIT normal operating mode at 2.0 V supply voltage − 1.4 − mA at 3.0 V supply voltage − 2.1 − mA clock running − 250 − µA no clock running − 20 − µA clock running − 375 − µA no clock running − 30 − µA Sleep mode; at 2.0 V supply voltage Sleep mode; at 3.0 V supply voltage Digital input pins; note 2 VIH HIGH-level input voltage at 2.0 V supply voltage 1.3 − 3.3 V at 3.0 V supply voltage 2.0 − 5.0 V at 2.0 V supply voltage −0.5 − +0.5 V VIL LOW-level input voltage −0.5 − +0.8 V ILI input leakage current − − 1 µA Ci input capacitance − − 10 pF at 3.0 V supply voltage 3-level input: pin PCS VIH HIGH-level input voltage 0.9VDDD − VDDD + 0.5 V VIM MID-level input voltage 0.4VDDD − 0.6VDDD V VIL LOW-level input voltage −0.5 − +0.5 V 0.45VDDA 0.5VDDA 0.55VDDA V − 12.5 − kΩ (THD + N)/S < 0.1%; RL = 800 Ω − tbf − mA 3 − − kΩ note 3 − − 50 pF DAC Vref(DAC) reference voltage Ro(ref) output resistance on pin Vref(DAC) Io(max) maximum output current RL load resistance CL load capacitance with respect to VSSA Notes 1. All supply connections must be made to the same external power supply unit. 2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be accepted, but levels from 3.3 V domain can be applied to the pins. 3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent oscillations in the output operational amplifier. 2000 Feb 07 12 Philips Semiconductors Preliminary specification Low power audio DAC UDA1334BTS 14 AC CHARACTERISTICS 14.1 2.0 V supply voltage VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ.; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DAC Vo(rms) output voltage (RMS value) ∆Vo unbalance between channels − 600 − mV − 0.1 − dB − −80 − dB − −37 − dB fs = 96 kHz; at 0 dB − −75 − dB fs = 96 kHz; at −60 dB; A-weighted − −35 − dB fs = 44.1 kHz; code = 0; A-weighted − 97 − dB − 95 − dB − 100 − dB − 60 − dB at 0 dB (FS) digital input (THD + N)/S total harmonic fs = 44.1 kHz; at 0 dB distortion-plus-noise to signal fs = 44.1 kHz; at −60 dB; ratio A-weighted S/N signal-to-noise ratio fs = 96 kHz; code = 0; A-weighted αcs channel separation PSRR power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) 14.2 3.0 V supply voltage VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DAC Vo(rms) output voltage (RMS value) ∆Vo unbalance between channels − 900 − mV − 0.1 − dB − −90 − dB − −40 − dB fs = 96 kHz; at 0 dB − −85 − dB fs = 96 kHz; at −60 dB; A-weighted − −38 − dB fs = 44.1 kHz; code = 0; A-weighted − 100 − dB − 98 − dB − 100 − dB − 60 − dB at 0 dB (FS) digital input (THD + N)/S total harmonic fs = 44.1 kHz; at 0 dB distortion-plus-noise to signal fs = 44.1 kHz; at −60 dB; ratio A-weighted S/N signal-to-noise ratio fs = 96 kHz; code = 0; A-weighted αcs channel separation PSRR power supply rejection ratio 2000 Feb 07 fripple = 1 kHz; Vripple = 30 mV (p-p) 13 Philips Semiconductors Preliminary specification Low power audio DAC UDA1334BTS 14.3 Timing VDDD = VDDA = 1.8 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing (see Fig.6) Tsys system clock cycle time tCWH system clock HIGH time tCWL system clock LOW time fsys = 256fs 35 88 780 ns fsys = 384fs 23 59 520 ns fsys = 512fs 17 44 390 ns fsys < 19.2 MHz 0.3Tsys − 0.7Tsys ns fsys ≥ 19.2 MHz 0.4Tsys − 0.6Tsys ns fsys < 19.2 MHz 0.3Tsys − 0.7Tsys ns fsys ≥ 19.2 MHz 0.4Tsys − 0.6Tsys ns Reset timing treset reset time 1 − − µs Serial interface timing (see Fig.7) fBCK bit clock frequency − − 64fs Hz tBCKH bit clock HIGH time 50 − − ns tBCKL bit clock LOW time 50 − − ns tr rise time − − 20 ns tf fall time − − 20 ns tsu(DATAI) set-up time data input 20 − − ns th(DATAI) hold time data input 0 − − ns tsu(WS) set-up time word select 20 − − ns th(WS) hold time word select 10 − − ns Note 1. The typical value of the timing is specified at fs = 44.1 kHz (sampling frequency). 2000 Feb 07 14 Philips Semiconductors Preliminary specification Low power audio DAC UDA1334BTS t CWH handbook, full pagewidth MGR984 t CWL Tsys Fig.6 System clock timing. handbook, full pagewidth WS th(WS) tBCKH tr tsu(WS) tf BCK tsu(DATAI) tBCKL Tcy(BCK) th(DATAI) DATAI MGL880 Fig.7 Serial interface timing. 2000 Feb 07 15 Philips Semiconductors Preliminary specification Low power audio DAC UDA1334BTS 15 APPLICATION INFORMATION analog supply voltage handbook, full pagewidth R7 1Ω C9 system clock R5 SYSCLK 47 Ω digital supply voltage 47 µF (16 V) 47 µF (16 V) C10 C6 100 nF (63 V) VSSA 100 nF (63 V) 15 VDDA 13 R6 1Ω C5 VSSD 5 VDDD 4 6 14 BCK WS DATAI SFOR1 SFOR0 MUTE DEEM PCS VOUTL C3 47 µF (16 V) 1 2 R3 R1 220 kΩ C1 3 7 11 UDA1334BTS 16 8 9 VOUTR C4 47 µF (16 V) 12 left output 100 Ω 10 nF (63 V) R4 right output 100 Ω R2 220 kΩ C2 10 nF (63 V) Vref(DAC) C8 100 nF (63 V) 10 C7 47 µF (16 V) MGL965 Fig.8 Typical application diagram. 2000 Feb 07 16 Philips Semiconductors Preliminary specification Low power audio DAC UDA1334BTS 16 PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 2000 Feb 07 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-152 17 o Philips Semiconductors Preliminary specification Low power audio DAC UDA1334BTS If wave soldering is used the following conditions must be observed for optimal results: 17 SOLDERING 17.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 17.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.3 17.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2000 Feb 07 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 18 Philips Semiconductors Preliminary specification Low power audio DAC 17.5 UDA1334BTS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 18 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 19 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2000 Feb 07 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 69 © Philips Electronics N.V. 2000 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/01/pp20 Date of release: 2000 Feb 07 Document order number: 9397 750 06674