SN54/74LS540 SN54/74LS541 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The SN54 / 74LS540 and SN54 / 74LS541 are octal buffers and line drivers with the same functions as the LS240 and LS241, but with pinouts on the opposite side of the package. These device types are designed to be used as memory address drivers, clock drivers and bus-oriented transmitters / receivers. These devices are especially useful as output ports for the microprocessors, allowing ease of layout and greater PC board density. OCTAL BUFFER / LINE DRIVER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • • • • Hysteresis at Inputs to Improve Noise Margin PNP Inputs Reduce Loading 3-State Outputs Drive Bus Lines Inputs and Outputs Opposite Side of Package, Allowing Easier Interface to Microprocessors • Input Clamp Diodes Limit High-Speed Termination Effects 20 LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) VCC 20 19 J SUFFIX CERAMIC CASE 732-03 1 SN54 / 74LS540 18 17 16 15 14 13 12 N SUFFIX PLASTIC CASE 738-03 11 20 1 1 2 VCC 20 19 3 4 5 6 7 8 9 10 GND 1 SN54 / 74LS541 18 17 16 15 14 DW SUFFIX SOIC CASE 751D-03 20 13 12 11 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 1 2 3 4 5 6 7 8 9 10 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54 74 – 12 – 15 mA IOL Output Current — Low 54 74 12 24 mA FAST AND LS TTL DATA 5-1 SN54/74LS540 • SN54/74LS541 BLOCK DIAGRAM LS540 LS541 (1) E1 (19) E2 D1 D2 D3 D4 D5 D6 D7 D8 (1) E1 (19) E2 (2) (18) (3) (17) (4) (16) (5) (15) (6) (14) (7) (13) Y1 D1 Y2 D2 Y3 D3 Y4 D4 Y5 D5 D6 Y6 (8) (12) D7 Y7 (9) (11) Y8 D8 INPUTS (2) (18) (3) (17) (4) (16) (5) (15) (6) (14) (7) (13) (8) (12) (9) (11) Y1 Y2 Y3 Y4 OUTPUTS E1 E2 D LS540 LS541 L H X L L X H L H X X L L Z Z H H Z Z L L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial Z = High Impedance Y5 Y6 Y7 Y8 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VT+–VT– Hysteresis IOZH Output Off Current HIGH IOZL Output Off Current LOW IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH ICC Min P Parameter Total Output LOW Total, Total Output 3-State Typ Max U i Unit 2.0 54 0.7 74 0.8 – 0.65 54, 74 2.4 54, 74 2.0 – 1.5 3.4 T Test C Conditions di i V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input p LOW Voltage g for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = – 3.0 mA V VCC = MIN, IOH = MAX, VIL = 0.5 V VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 12 mA 74 0.35 0.5 V IOL = 24 mA V VCC = MIN 20 µA VCC = MAX, VOUT = 2.7 V – 20 µA VCC = MAX, VOUT = 0.4 V 20 µA VCC = MAX, VIN = 2.7 V 0.2 0.4 – 40 0.1 mA VCC = MAX, VIN = 7.0 V – 0.2 mA VCC = MAX, VIN = 0.4 V – 225 mA VCC = MAX mA LS540 25 LS541 32 mA LS540 45 mA LS541 52 mA LS540 52 mA LS541 55 mA Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-2 VCC = MAX SN54/74LS540 • SN54/74LS541 AC CHARACTERISTICS (TA = 25°C) Limits S b l Symbol P Parameter tPLH tPLH tPHL Propagation P p g i D Delay, l y, Data to Output tPHL Typ Max LS540 Min 9.0 15 LS541 12 15 LS540 12 15 LS541 12 18 U i Unit T Test C Conditions di i ns Output p Enable Time to HIGH Level LS540 15 25 tPZH LS541 15 32 Output p Enable Time to LOW Level LS540 20 38 tPZL LS541 20 38 Output p Disable Time to HIGH Level LS540 10 18 tPHZ LS541 10 18 LS540 15 25 tPLZ Output p Disable Time to LOW Level LS541 15 29 VCC = 5.0 50V CL = 45 pF RL = 667 Ω ns ns ns CL = 5.0 5 0 pF F ns AC WAVEFORMS VCC VIN 1.3 V 1.3 V tPLH VOUT RL tPHL 1.3 V 1.3 V SW1 Figure 1 TO OUTPUT UNDER TEST VIN 1.3 V 1.3 V tPLH tPHL 1.3 V VOUT 5 kΩ 1.3 V CL* SW2 Figure 2 VE 1.5 V VE 1.5 V tPZL tPLZ ≈ 1.5 V VOL 1.5 V VOUT SWITCH POSITIONS 0.5 V Figure 3 VE 1.5 V VE 1.5 V tPZH VOUT 1.5 V tPHZ ≥VOH ≈ 1.5 V 0.5 V Figure 4 SYMBOL SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed Figure 5 FAST AND LS TTL DATA 5-3