SN54/74LS322A 8-BIT SHIFT REGISTERS WITH SIGN EXTEND These 8-bit shift registers have multiplexed input/output data ports to accomplish full 8-bit data handling in a single 20-pin package. Serial data may enter the shift-right register through either D0 or D1 inputs as selected by the data select pin. A serial output is also provided. Synchronous parallel loading is achieved by taking the register enable and the S / P inputs low. This places the three-state input / output ports in the data input mode. Data is entered on the low-to-high clock transition. The data extend function repeats the sign in the QA flip-flop during shifting. An overriding clear input clears the internal registers when taken low whether the outputs are enabled or off. The output enable does not affect synchronous operation of the register. • • • • Multiplexed Inputs/ Outputs Provide Improved Bit Density Sign Extend Function Direct Overriding Clear 3-State Outputs Drive Bus Lines Directly 8-BIT SHIFT REGISTERS WITH SIGN EXTEND LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 732-03 20 1 (TOP VIEW) DATA SIGN VCC SELECT EXTEND D1 20 19 18 17 B/QB D/QD 16 F/QF H/QH Q/H CLOCK 14 13 12 11 15 N SUFFIX PLASTIC CASE 738-03 20 DS SE D1 B/QB D/QD F/QF H/GH Q/H D0 A/QA C/QC E/QE G/QG OE CK G S/P 1 DW SUFFIX SOIC CASE 751D-03 CLR 20 1 2 REGISTER S/P ENABLE 3 D0 4 5 A/QA C/QC 6 7 8 9 1 10 E/QE G/QG OUTPUT CLEAR GND ENABLE ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High Q H′ 54, 74 – 0.4 mA IOL Output Current — Low Q H′ Q H′ 54 74 4.0 8.0 mA IOH Output Current — High QA– QH QA– QH 54 74 – 1.0 – 2.6 mA IOL Output Current — Low QA– QH QA– QH 54 74 12 24 mA FAST AND LS TTL DATA 5-1 SN54/74LS322A BLOCK DIAGRAM REGISTER ENABLE G (1) S/P SIGN EXTEND SE (2) (18) (17) DATA D1 (19) SELECT DS (3) D0 CLOCK CLEAR OUTPUT ENABLE OE Q Q CK D Q CLR CK D Q CLR FOUR IDENTICAL CHANNELS NOT SHOWN (12) Q Q CK D Q CLR CK D Q CLR (7) (13) QH (11) (9) (8) (4) (16) A/QA B/QB G/QG H/QH FUNCTION TABLE INPUTS OPERATION CLEAR REGISTER ENABLE Clear L L Hold INPUTS/OUTPUTS OUTPUT Q H′ S/P SIGN EXTEND DATA SELECT OUTPUT ENABLE CLOCK A/QA B/QB H X X H X X X X L L X X L L L L L L L L L L H H X X X L X QA0 QB0 QC0 QH0 QH0 Shift Right H H L L H H H H L H L L ↑ ↑ D0 D1 QAn QAn QBn QBn QGn QGn QGn QGn Sign Extend H L H L X L ↑ QAn QAn QBn QGn QGn Load H L L X X X ↑ a b c h h C/QC … H/QH When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. If both the register enable input and the S/P input are low while the clear input is low, the register is cleared while the eight input/output terminals are disabled to the high-impedance state. H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW to HIGH level QA0…QH0 = the level of QA through QH, respectively, before the indicated steady-state conditions were established QAn…QHn = the level of QA through QH, respectively, before the most recent ↑ transition of the clock D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively a…h = the level of steady-state inputs at inputs A through H respectively FAST AND LS TTL DATA 5-2 SN54/74LS322A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter Typ Max Unit 2.0 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage Output HIGH Voltage QA– QH 54 2.4 3.2 V VOH 74 2.4 3.2 V Output HIGH Voltage Q H′ 54 2.5 3.4 V VOH 74 2.7 3.4 V Output LOW Voltage QA– QH 54, 74 0.25 0.4 V VOL IOL = 12 mA 74 0.35 0.5 V IOL = 24 mA Output LOW Voltage Q H′ 54, 74 0.4 V VOL IOL = 4.0 mA 74 0.5 V IOL = 8.0 mA 54 0.7 74 0.8 – 0.65 – 1.5 VCC = MIN, IOH = MAX VCC = MIN, IOH = MAX VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table IOZH Output Off Current HIGH QA– QH 40 µA VCC = MAX, VOUT = 2.7 V IOZL Output Off Current LOW QA– QH – 400 µA VCC = MAX, VOUT = 0.4 V Other 20 µA A – H, Data Select 40 µA IIH IIL Input HIGH Current Input LOW Current Sign Extend 60 µA Other 0.1 mA Data Select 0.2 mA Sign Extend 0.3 mA A–H 0.1 mA Other – 0.4 mA Data Select – 0.8 mA Sign Extend IOS Short Circuit Current (Note 1) ICC Power Supply Current VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 5.5 V VCC = MAX, VIN = 0.4 V – 1.2 mA Q H′ – 20 –100 mA VCC = MAX QA– QH – 30 –130 mA VCC = MAX 60 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-3 SN54/74LS322A AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ 25 35 Max Unit Test Conditions fMAX Maximum Clock Frequency MHz tPHL tPLH Propagation Delay, Clock to QH′ 26 22 35 33 ns tPHL Propagation Delay, Clear to QH′ 27 35 ns tPHL tPLH Propagation Delay, Clock to QA– QH 22 16 33 25 ns tPHL Propagation Delay, Clear to QA– QH 22 35 ns tPZH tPZL Output Enable Time 15 15 35 35 ns tPHZ tPLZ Output Disable Time 15 15 25 25 ns CL = 5.0 pF Max Unit Test Conditions CL = 15 pF CL = 45 pF, RL = 667 Ω AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ tW Clock Pulse Width HIGH 25 ns tW Clock Pulse Width LOW 15 ns tW Clear Pulse Width LOW 20 ns ts Data Setup Time 20 ns ts Select Setup Time 15 ns th Data Hold Time 0 ns th Select Hold Time 10 ns trec Recovery Time 20 ns VCC = 5.0 V DEFINITIONS OF TERMS recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH Data to the Q outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued FAST AND LS TTL DATA 5-4