NTMD2P01R2 Power MOSFET −2.3 Amps, −16 Volts Dual SOIC−8 Package Features • • • • • http://onsemi.com High Efficiency Components in a Single SOIC−8 Package High Density Power MOSFET with Low RDS(on) Logic Level Gate Drive SOIC−8 Surface Mount Package, Mounting Information for SOIC−8 Package Provided Pb−Free Packages are Available VDSS RDS(ON) Typ ID Max −16 V 100 mW @ −4.5 V −2.3 A P−Channel Applications D • Power Management in Portable and Battery−Powered Products, i.e.: Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS −16 V Gate−to−Source Voltage − Continuous VGS "10 V Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 100°C Pulsed Drain Current (Note 4) RqJA PD ID ID IDM 175 0.71 −2.3 −1.45 −9.0 °C/W W A A A Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 100°C Pulsed Drain Current (Note 4) RqJA PD ID ID IDM 105 1.19 −2.97 −1.88 −12 °C/W W A A A Thermal Resistance − Junction−to−Ambient (Note 3) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 100°C Pulsed Drain Current (Note 4) RqJA PD ID ID IDM 62.5 2.0 −3.85 −2.43 −15 °C/W W A A A TJ, Tstg −55 to +150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = −16 Vdc, VGS = −4.5 Vdc, Peak IL = −5.0 Apk, L = 28 mH, RG = 25 W) EAS 350 mJ Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL Operating and Storage Temperature Range February, 2006 − Rev. 2 S MARKING DIAGRAM* AND PIN ASSIGNMENT 8 D1 D1 D2 D2 1 SOIC−8 SUFFIX NB CASE 751 STYLE 11 8 ED2P01 AYWW G G 1 S1 G1 S2 G2 ED2P01= Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Minimum FR−4 or G−10 PCB, Steady State. 2. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick single sided), Steady State. 3. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick single sided), t ≤ 10 seconds. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. © Semiconductor Components Industries, LLC, 2006 G 1 Shipping† Device Package NTMD2P01R2 SOIC−8 2500/Tape & Reel SOIC−8 (Pb−Free) 2500/Tape & Reel NTMD2P01R2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D Publication Order Number: NTMD2P01R2/D NTMD2P01R2 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5) Characteristic Symbol Min Typ Max −16 − − −12.7 − − − − − − −1.0 −10 − − −100 − − 100 −0.5 − −0.90 2.5 −1.5 − − − − 0.070 0.100 0.110 0.100 0.130 0.150 − 4.2 − Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = −250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = −16 Vdc, VGS = 0 Vdc, TJ = 25°C) (VDS = −16 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = −10 Vdc, VDS = 0 Vdc) IGSS Gate−Body Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = −250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = −4.5 Vdc, ID = −2.4 Adc) (VGS = −2.7 Vdc, ID = −1.2 Adc) (VGS = −2.5 Vdc, ID = −1.2 Adc) RDS(on) Forward Transconductance (VDS = −10 Vdc, ID = −1.2 Adc) gFS Vdc mV/°C W Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = −16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance Ciss − 540 750 Coss − 215 325 Crss − 100 175 td(on) − 10 20 tr − 35 65 td(off) − 33 60 tf − 29 55 td(on) − 15 − tr − 40 − td(off) − 35 − pF SWITCHING CHARACTERISTICS (Notes 6 and 7) Turn−On Delay Time (VDD = −10 Vdc, ID = −2.4 Adc, VGS = −4.5 Vdc, RG = 6.0 W) Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time (VDD = −10 Vdc, ID = −1.2 Adc, VGS = −2.7 Vdc, RG = 6.0 W) Rise Time Turn−Off Delay Time Fall Time Total Gate Charge (VDS = −16 Vdc, VGS = −4.5 Vdc, ID = −2.4 Adc) Gate−Source Charge Gate−Drain Charge ns ns tf − 35 − Qtot − 10 18 Qgs − 1.5 − Qgd − 5.0 − VSD − − −0.88 −0.75 −1.0 − Vdc trr − 37 − ns ta − 16 − tb − 21 − QRR − 0.025 − nC BODY−DRAIN DIODE RATINGS (Note 6) Diode Forward On−Voltage (IS = −2.4 Adc, VGS = 0 Vdc) (IS = −2.4 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = −2.4 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 mC NTMD2P01R2 VGS = −10 V VGS = −4.5 V VGS = −2.5 V 3 TJ = 25°C VGS = −1.9 V 2 VGS = −1.7 V 1 VGS = −1.5 V 0 2 0.2 4 6 8 3 2 TJ = 25°C 1 TJ = 100°C 1 3 2.5 Figure 2. Transfer Characteristics. 0.05 2 4 8 6 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.12 TJ = 25°C 0.1 VGS = −2.7 V 0.08 VGS = −4.5 V 0.06 0.04 1 1.5 2 2.5 3 3.5 4 4.5 −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage. Figure 4. On−Resistance vs. Drain Current and Gate Voltage. 1.6 1000 VGS = 0 V ID = −2.4 A VGS = −4.5 V 100 −IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2 Figure 1. On−Region Characteristics. 0.1 1.2 1 0.8 0.6 −50 1.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C 1.4 TJ = 55°C −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.15 0 VDS > = −10 V 4 0 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 5 VGS = −2.1 V −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) 4 −25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 TJ = 125°C TJ = 100°C 10 TJ = 25°C 1 0.1 0.01 0 Figure 5. On−Resistance Variation with Temperature. 4 8 12 16 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−to−Source Leakage Current vs. Voltage. http://onsemi.com 3 20 C, CAPACITANCE (pF) VDS = 0 V 1200 VGS = 0 V Ciss 900 TJ = 25°C Crss Ciss 600 300 0 Coss Crss 10 5 0 −VGS −VDS 5 10 15 20 5 20 16 4 14 3 Q1 1 0 2 4 6 8 12 10 100 tr tf td (on) 10 tf VDD = −10 V ID = −2.4 A VGS = −4.5 V td (on) 10 1.0 14 2 0 td (off) tr td (off) 4 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge VDD = −10 V ID = −1.2 A VGS = −2.7 V 100 6 ID = −2.4 A TJ = 25°C Qg, TOTAL GATE CHARGE (nC) t, TIME (ns) t, TIME (ns) 8 VDS Figure 7. Capacitance Variation 10 10 Q2 2 0 12 VGS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 18 QT −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1500 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTMD2P01R2 100 1.0 RG, GATE RESISTANCE (OHMS) 1.0 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance −IS, SOURCE CURRENT (AMPS) 2 1.6 VGS = 0 V TJ = 25°C di/dt IS 1.2 trr ta 0.8 tb TIME 0.25 IS tp 0.4 IS 0 0.4 0.5 0.6 0.7 0.8 0.9 1 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current Figure 12. Diode Reverse Recovery Waveform http://onsemi.com 4 NTMD2P01R2 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 D = 0.5 0.2 0.1 Normalized to R∅ja at Steady State (1 inch pad) 0.1 0.0125 W 0.0563 W 0.110 W 0.273 W 0.113 W 0.436 W 2.93 F 152 F 261 F 0.05 0.02 0.01 0.021 F 0.137 F 1.15 F Single Pulse 0.01 1E−03 1E−02 1E−01 1E+00 1E+03 t, TIME (s) Figure 13. FET Thermal Response http://onsemi.com 5 1E+02 1E+03 NTMD2P01R2 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AG −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N MILLIMETERS DIM MIN MAX A 4.80 5.00 B 3.80 4.00 C 1.35 1.75 D 0.33 0.51 G 1.27 BSC H 0.10 0.25 J 0.19 0.25 K 0.40 1.27 M 0_ 8_ N 0.25 0.50 S 5.80 6.20 STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 X 45 _ SEATING PLANE −Z− H 0.10 (0.004) D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 6 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTMD2P01R2/D