ONSEMI MJF47G

MJF47
High Voltage Power
Transistor
Isolated Package Applications
Designed for line operated audio output amplifiers, switching power
supply drivers and other switching applications, where the mounting
surface of the device is required to be electrically isolated from the
heatsink or chassis.
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NPN SILICON
POWER TRANSISTOR
1 AMPERE
250 VOLTS, 28 WATTS
Features
•
•
•
•
•
•
•
Electrically Similar to the Popular TIP47
250 VCEO(sus)
1 A Rated Collector Current
No Isolating Washers Required
Reduced System Cost
UL Recognized, File #E69369, to 3500 VRMS Isolation
Pb−Free Package is Available*
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MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCEO
250
Vdc
Collector−Base Voltage
VCB
350
Vdc
Emitter−Base Voltage
VEB
5
Vdc
Collector−Emitter Voltage
RMS Isolation Voltage (Note 1)
Test No. 1 Per Figure 10
Test No. 2 Per Figure 11
Test No. 3 Per Figure 12
(for 1 sec, R.H. < 30%, TA = 25_C)
Collector Current
− Continuous
− Peak
VISOL
1
2
Adc
Base Current − Continuous
IB
0.6
Adc
Total Power Dissipation (Note 2) @ TC = 25_C
Derate above 25_C
PD
40
0.31
W
W/_C
Total Power Dissipation @ TA = 25_C
Derate above 25_C
PD
2.0
0.016
W
W/_C
TJ, Tstg
–65 to +150
_C
Symbol
Max
Unit
Thermal Resistance, Junction−to−Ambient
RqJA
62.5
_C/W
Thermal Resistance, Junction−to−Case (Note 2)
RqJC
4.4
_C/W
Lead Temperature for Soldering Purposes
TL
260
_C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Proper strike and creepage distance must be provided.
2. Measurement made with thermocouple contacting the bottom insulated
surface (in a location beneath the die), the devices mounted on a heatsink with
thermal grease and a mounting torque of ≥ 6 in. lbs.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 5
3
MARKING DIAGRAM
MJF47G
AYWW
G
A
Y
WW
THERMAL CHARACTERISTICS
Characteristic
2
TO−220 FULLPACK
CASE 221D
STYLE 2
V
4500
3500
1500
IC
Operating and Storage Temperature Range
1
1
= Pb−Free Package
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MJF47
TO−220 FULLPACK
50 Units/Rail
MJF47G
TO−220 FULLPACK
(Pb−Free)
50 Units/Rail
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Publication Order Number:
MJF47/D
MJF47
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ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
VCEO(sus)
250
−
Vdc
Collector Cutoff Current
(VCE = 150 Vdc, IB = 0)
ICEO
−
0.2
mAdc
Collector Cutoff Current
(VCE = 350 Vdc, VBE = 0)
ICES
−
0.1
mAdc
Emitter Cutoff Current
(VBE = 5 Vdc, IC = 0)
IEBO
−
1
mAdc
30
10
150
−
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 3)
(IC = 30 mAdc, IB = 0)
ON CHARACTERISTICS (Note 3)
DC Current Gain
(IC = 0.3 Adc, VCE = 10 Vdc)
(IC = 1 Adc, VCE = 10 Vdc)
hFE
−
Collector−Emitter Saturation Voltage
(IC = 1 Adc, IB = 0.2 Adc)
VCE(sat)
−
1
Vdc
Base−Emitter On Voltage
(IC = 1 Adc, VCE = 10 Vdc)
VBE(on)
−
1.5
Vdc
fT
10
−
MHz
DYNAMIC CHARACTERISTICS
Current Gain − Bandwidth Product
(IC = 0.2 Adc, VCE 10 Vdc, f = 2 MHz)
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
TYPICAL CHARACTERISTICS
200
1.4
VCE = 10 V
60
40
20
1.2
TJ = 150°C
V, VOLTAGE (VOLTS)
hFE , DC CURRENT GAIN
100
25°C
−55 °C
10
6
4
2
0.02
1
0.8
0.6
VBE(on) @ VCE = 4 V
0.4
TJ = 25°C
0.2
0.04 0.06 0.1
0.2
0.4 0.6
IC, COLLECTOR CURRENT (AMPS)
1
0
0.02
2
VBE(sat) @ IC/IB = 5
Figure 1. DC Current Gain
VCE(sat) @ IC/IB = 5 V
0.04 0.06
0.1
0.2
0.4 0.6
IC, COLLECTOR CURRENT (AMPS)
Figure 2. “On” Voltages
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2
1
2
MJF47
1
5
TJ = 25°C
VCC = 200 V
IC/IB = 5
tr
0.2
2
t, TIME (s)
μ
t, TIME (s)
μ
0.5
td
0.1
0.05
1
0.5
tf
0.2
0.1
0.02
0.01
0.02
TJ = 25°C
VCC = 200 V
IC/IB = 5
ts
0.05
0.2
0.5
0.1
IC, COLLECTOR CURRENT (AMPS)
1
0.05
0.02
2
0.05
Figure 3. Turn−On Time
0.1
0.2
0.5
IC, COLLECTOR CURRENT (AMPS)
1
2
Figure 4. Turn−Off Time
TURN−ON PULSE
APPROX
+11 V
VCC
RC
SCOPE
Vin
Vin 0
VEB(off)
RB
51
t1
Cjd << Ceb
t3
APPROX
+11 V
−4 V
t1 ≤ 7 ns
100 < t2 < 500 ms
t3 < 15 ns
Vin
DUTY CYCLE ≈ 2%
APPROX −9 V
t2
RB and RC VARIED TO OBTAIN
DESIRED CURRENT LEVELS.
TURN−OFF PULSE
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 5. Switching Time Equivalent Circuit
1
0.5
0.3
0.2
0.1
SINGLE PULSE
RqJC(t) = r(t) RqJC
RqJC = 4.4°C/W MAX
TJ(pk) − TC = P(pk) RqJC(t)
0.05
0.03
0.02
0.01
0.1
0.2 0.3
0.5
1
2
3
5
10
20 30
50
t, TIME (msec)
100
Figure 6. Thermal Response
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3
200 300
500
1K
2K
3K
5K
10 K
IC, COLLECTOR CURRENT (AMPS)
MJF47
3
2
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 7 is based on TJ(pk) = 150_C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided TJ(pk)
v 150°C. TJ(pk) may be calculated from the data in
Figure 6. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
100 ms
500 ms
1
1ms
0.5
dc
0.3
0.2
CURRENT LIMIT
THERMAL LIMIT @ TC = 25°C
SECONDARY BREAKDOWN LIMIT
0.1
0.05
0.03
10
20
30
50
200
100
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
300
PD(AV), AVERAGE POWER DISSIPATION (WATTS)
PD(AV), AVERAGE POWER DISSIPATION (WATTS)
Figure 7. Maximum Forward Bias Safe
Operating Area
40
30
20
10
0
0
50
100
150
200
2
1.5
1
0.5
0
0
50
100
150
TC, CASE TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 8. Power Derating
Figure 9. Power Derating
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4
200
MJF47
TEST CONDITIONS FOR ISOLATION TESTS*
CLIP
MOUNTED
FULLY ISOLATED
PACKAGE
MOUNTED
FULLY ISOLATED
PACKAGE
CLIP
MOUNTED
FULLY ISOLATED
PACKAGE
0.099" MIN
LEADS
LEADS
HEATSINK
0.099" MIN
LEADS
HEATSINK
HEATSINK
0.110" MIN
Figure 10. Clip Mounting Position
for Isolation Test Number 1
Figure 11. Clip Mounting Position
for Isolation Test Number 2
Figure 12. Screw Mounting Position
for Isolation Test Number 3
*Measurement made between leads and heatsink with all leads shorted together
MOUNTING INFORMATION
4−40 SCREW
CLIP
PLAIN WASHER
HEATSINK
COMPRESSION WASHER
HEATSINK
NUT
Figure 13. Typical Mounting Techniques*
Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a screw
torque of 6 to 8 in . lbs is sufficient to provide maximum power dissipation capability. The compression washer helps to maintain a
constant pressure on the package over time and during large temperature excursions.
Destructive laboratory tests show that using a hex head 4−40 screw, without washers, and applying a torque in excess of 20 in . lbs will
cause the plastic to crack around the mounting hole, resulting in a loss of isolation capability.
Additional tests on slotted 4−40 screws indicate that the screw slot fails between 15 to 20 in . lbs without adversely affecting the package. However, in order to positively ensure the package integrity of the fully isolated device, ON Semiconductor does not recommend
exceeding 10 in . lbs of mounting torque under any mounting conditions.
** For more information about mounting power semiconductors see Application Note AN1040.
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5
MJF47
PACKAGE DIMENSIONS
TO−220 FULLPAK
CASE 221D−03
ISSUE G
−T−
−B−
F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH
3. 221D−01 THRU 221D−02 OBSOLETE, NEW
STANDARD 221D−03.
SEATING
PLANE
C
S
Q
U
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
U
A
1 2 3
H
−Y−
K
G
N
L
D
J
R
3 PL
0.25 (0.010)
M
B
M
Y
INCHES
MIN
MAX
0.625
0.635
0.408
0.418
0.180
0.190
0.026
0.031
0.116
0.119
0.100 BSC
0.125
0.135
0.018
0.025
0.530
0.540
0.048
0.053
0.200 BSC
0.124
0.128
0.099
0.103
0.101
0.113
0.238
0.258
MILLIMETERS
MIN
MAX
15.88
16.12
10.37
10.63
4.57
4.83
0.65
0.78
2.95
3.02
2.54 BSC
3.18
3.43
0.45
0.63
13.47
13.73
1.23
1.36
5.08 BSC
3.15
3.25
2.51
2.62
2.57
2.87
6.06
6.56
STYLE 2:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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MJF47/D