NTD50N03R Power MOSFET 25 V, 45 A, Single N−Channel, DPAK Features • • • • • Planar Technology Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Pb−Free Packages are Available http://onsemi.com V(BR)DSS Applications RDS(on) TYP 12.5 mW @ 10 V 25 V • VCORE DC−DC Buck Converter Applications • Optimized for High Side Switching Symbol N−Channel D Value Unit Drain−to−Source Voltage VDSS 25 V Gate−to−Source Voltage VGS "20 V ID 9.2 A Continuous Drain Current (RqJA) (Note 1) TA = 25°C Power Dissipation (RqJA) (Note 1) TA = 25°C Continuous Drain Current (RqJA) (Note 2) TA = 25°C G S 7.2 PD 2.1 W 4 4 4 TA = 85°C A 7.8 6.0 1 2 TA = 25°C PD 1.5 W Continuous Drain Current (RqJC) (Note 1) TC = 25°C ID 45 A Power Dissipation (RqJC) (Note 1) TC = 25°C TC = 85°C 35 PD 50 W Pulsed Drain Current TA = 25°C, tp = 10 ms IDM 180 A Current Limited by Package TA = 25°C IDmaxPkg 45 A TJ, Tstg −55 to 175 °C IS 45 A Drain−to−Source (dv/dt) dv/dt 8.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL = 6.32 Apk, L = 1.0 mH, RG = 25 W) EAS 20 mJ Operating Junction and Storage Temperature Source Current (Body Diode) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL °C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 sq in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. 3 1 1 2 3 3 CASE 369AA CASE 369D CASE 369AC DPAK DPAK 3 IPAK (Surface Mount) (Straight Lead) (Straight Lead) STYLE 2 STYLE 2 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain YWW T50 N03RG Steady State ID YWW T50 N03RG Power Dissipation (RqJA) (Note 2) TA = 85°C 45 A 19 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter ID MAX 1 Gate 2 Drain 3 Source Y WW T50N03R G 1 Gate 3 Source 2 Drain = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 4 1 Publication Order Number: NTD50N03R/D NTD50N03R THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 3.0 °C/W Junction−to−Ambient − Steady State (Note 3) RqJA 71.4 Junction−to−Ambient − Steady State (Note 4) RqJA 100 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 25 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V −16 VGS = 0 V, VDS = 20 V mV/°C TJ = 25°C 1.5 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA "100 mA nA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(TH)/TJ RDS(on) VGS = 11.5 V VGS = 10 V VGS = 4.5 V Forward Transconductance gFS 1.0 1.7 2.0 V −5.0 mV/°C ID = 30 A 12 mW ID = 15 A 11.7 ID = 30 A 12.5 ID = 30 A 21 ID = 15 A 19 VDS = 15 V, ID = 15 A 14 23 15 S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Ciss 610 VGS = 0 V, f = 1.0 MHz, VDS = 12 V Coss Crss 125 QG(TOT) 6.0 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 3.7 Total Gate Charge QG(TOT) 15 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD VGS = 11.5 V, VDS = 15 V, ID = 30 A http://onsemi.com 2 10 nC 0.9 1.9 1.0 1.9 3.9 3. Surface−mounted on FR4 board using 1 sq in pad, 1 oz Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size. 5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. pF 300 Total Gate Charge VGS = 4.5 V, VDS = 15 V, ID = 30 A 750 nC NTD50N03R ELECTRICAL CHARACTERISTICS (continued) (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 30 A, RG = 3.0 W 9.6 11.2 tf 6.8 td(on) 5.0 tr 84 td(off) ns 8.2 VGS = 11.5 V, VDS = 15 V, ID = 30 A, RG = 3.0 W tf ns 15 4.0 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR VGS = 0 V, IS = 30 A TJ = 25°C 0.85 TJ = 125°C 0.71 24 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A Charge Time ta Discharge Time tb 10.5 QRR 14 Source Inductance LS 2.49 Drain Inductance LD Reverse Recovery Charge 1.1 V ns 14 nC PACKAGE PARASITIC VALUES Gate Inductance LG Gate Resistance RG 0.02 Ta = 25C 3.46 3.75 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 nH W NTD50N03R 100 10 V 6V 8V 80 7V 5V 4.5 V 60 4V 40 3.5 V 20 3V 2.8 V VGS = 2.6 V 0 2 1 3 4 6 5 7 8 9 60 40 20 10 2 3 4 5 6 7 8 9 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 15 A TJ = 25°C 0.055 0.045 0.035 0.025 0.015 0.005 3 4 5 6 7 8 9 10 10 0.030 TJ = 25°C 0.025 VGS = 4.5 V 0.020 0.015 VGS = 10 V 0.010 0.005 0 10 20 30 40 50 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 10,000 2.0 VGS = 0 V ID = 10 A VGS = 10 V IDSS, LEAKAGE (nA) 1.8 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.065 2 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 125°C TJ = 25°C 80 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = −55°C VDS ≥ 10 V 5.5 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 100 1.6 1.4 1.2 1.0 TJ = 150°C 1000 TJ = 125°C 0.8 0.6 −50 −25 100 0 25 50 75 100 125 150 175 0 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 25 C, CAPACITANCE (pF) 16 TJ = 25°C VDS = 0 V VGS = 0 V Ciss 800 16 QT 12 Crss Ciss 600 400 Coss 200 Crss 0 10 VGS 0 VDS 5 5 10 15 20 VDS VGS 8 8 QGD QGS 4 4 ID = 30 A TJ = 25°C 0 0 2 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 4 6 8 10 12 14 0 16 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 100 20 IS, SOURCE CURRENT (AMPS) VDS = 10 V ID = 10 A VGS = 10 V tr td(off) 10 td(on) tf 1 18 VGS = 0 V 16 TJ = 25°C 14 12 10 8 6 4 2 0 1 10 100 0 0.2 0.4 0.6 0.8 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 1000 I D, DRAIN CURRENT (AMPS) t, TIME (ns) 12 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTD50N03R SINGLE PULSE VGS = 20 V TC = 25°C 10 ms 100 100 ms 10 1 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 10 ms dc 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 5 100 1.0 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) NTD50N03R 1.0 D = 0.5 0.2 0.1 P(pk) 0.1 0.05 0.02 t1 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 Figure 12. Thermal Response ORDERING INFORMATION Package Shipping † DPAK−3 75 Units / Rail NTD50N03RG DPAK−3 (Pb−Free) 75 Units / Rail NTD50N03RT4 DPAK−3 2500 / Tape & Reel DPAK−3 (Pb−Free) 2500 / Tape & Reel NTD50N03R−1 DPAK−3 Straight Lead 75 Units / Rail NTD50N03R−1G DPAK−3 Straight Lead (Pb−Free) 75 Units / Rail NTD50N03R−35 DPAK−3 Straight Lead Trimmed (3.5 ± 0.15 mm) 75 Units / Rail NTD50N03R−35G DPAK−3 Straight Lead Trimmed (3.5 ± 0.15 mm) (Pb−Free) 75 Units / Rail Order Number NTD50N03R NTD50N03RT4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD50N03R PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D 2 PL 0.13 (0.005) G M T INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DPAK CASE 369D−01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL 0.13 (0.005) DIM A B C D E F G H J K R S V Z T http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− NTD50N03R PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC−01 ISSUE O B V C E R NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. A SEATING PLANE K W F J G H D 3 PL 0.13 (0.005) W DIM A B C D E F G H J K R V W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 8 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTD50N03R/D