Revised February 2005
74AC74 • 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
Features
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
■ ICC reduced by 50%
■ Output source/sink 24 mA
■ ACT74 has TTL-compatible inputs
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Ordering Code:
Order Number
Package
Number
Package Description
74AC74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC74SC_NL
(Note 1)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC74SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC74MTCX_NL
(Note 2)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC74PC
N14A
74ACT74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT74SC_NL
(Note 1)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT74SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74SJX_NL
(Note 2)
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JECED J-STD-020B.
Note 1: “_NL” indicates lead-free product (per JEDEC J-STD-020B).
Note 2: “_NL” indicates lead-free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009920
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74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
November 1988
74AC74 • 74ACT74
Connection Diagram
Pin Descriptions
Pin Names
Description
D1 , D2
Data Inputs
CP1, CP2
Clock Pulse Inputs
CD1, CD2
Direct Clear Inputs
SD1, SD2
Direct Set Inputs
Q1, Q1, Q2, Q2
Outputs
Logic Symbols
IEEE/IEC
Truth Table
(Each Half)
Inputs
Outputs
SD
CD
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
H
H
H
H
H
H
L
H
H
X
L
L
H
H
H
L
X
Q0
Q0
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
LOW-to-HIGH Clock Transition
Q0 (Q0) Previous Q (Q) before LOW-to-HIGH Transition of Clock
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74AC74 • 74ACT74
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74AC74 • 74ACT74
Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
DC Input Voltage (VI)
Supply Voltage (VCC)
20 mA
20 mA
0.5V to VCC 0.5V
DC Output Diode Current (IOK)
VO
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
20 mA
20 mA
0.5V to VCC 0.5V
0V to VCC
0V to VCC
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate ('V/'t)
r50 mA
65qC to 150qC
ACT Devices
VIN from 0.8V to 2.0V
Junction Temperature (TJ)
VCC @ 4.5V, 5.5V
140qC
PDIP
40qC to 85qC
Operating Temperature (TA)
Minimum Input Edge Rate ('V/'t)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
4.5V to 5.5V
Output Voltage (VO)
r50 mA
Storage Temperature (TSTG)
2.0V to 6.0V
ACT
Input Voltage (VI)
DC Output Source
or Sink Current (IO)
AC
125 mV/ns
Note 3: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC
TA
25qC
TA
40qC to 85qC
(V)
Typ
Guaranteed Limits
Minimum HIGH
3.0
1.5
2.1
2.1
Level Input
4.5
2.25
3.15
3.15
Voltage
5.5
2.75
3.85
3.85
Maximum LOW
3.0
1.5
0.9
0.9
Level Input
4.5
2.25
1.35
1.35
1.65
Voltage
5.5
2.75
1.65
Minimum HIGH
3.0
2.99
2.9
2.9
Level Output
4.5
4.49
4.4
4.4
Voltage
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
0.1
0.1
Maximum LOW
Units
Conditions
VOUT
V
VOUT
or VCC 0.1V
V
IOUT
50 PA
V
VIN
VIL or VIH
IOH
12 mA
IOH
24 m
IOH
24 m (Note 4)
0.002
Level Output
4.5
0.001
0.1
0.1
Voltage
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
r 0.1
r 1.0
PA
VI
V
V
50 PA
IOUT
VIN
VIL or VIH
IOL
12 mA
IOL
24 mA
IOL
24 mA (Note 4)
IIN (Note 6)
Maximum Input Leakage Current
5.5
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 5)
5.5
75
mA
VOHD
ICC
Maximum Quiescent
(Note 6)
Supply Current
2.0
20.0
Note 4: All outputs loaded; thresholds on input associated with output under test.
Note 5: Maximum test duration 2.0 ms, one output loaded at a time.
Note 6: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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4
0.1V
V
3.0
5.5
0.1V
or VCC 0.1V
PA
VIN
VCC, GND
1.65V Maximum
3.85V Minimum
VCC
or GND
74AC74 • 74ACT74
DC Electrical Characteristics for ACT
Symbol
Parameter
Minimum HIGH Level
VIH
VIL
VOH
VOL
IIN
TA
(V)
Typ
4.5
1.5
25qC
TA
40qC to 85qC
Guaranteed Limits
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Output Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
5.5
4.86
V
IOUT
50 PA
24 mA (Note 7)
IOUT
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
V
V
V
VIN
VIL or VIH
IOL
24 mA
IOL
r1.0
PA
1.5
mA
0.6
50 PA
24 mA (Note 7)
VI
VCC, GND
VI
VCC 2.1V
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 8)
5.5
75
mA
VOHD
ICC
Maximum Quiescent
Supply Current
5.5
2.0
0.1V
or VCC 0.1V
24 mA
Output Voltage
ICC/Input
V
IOH
0.1
r0.1
or VCC 0.1V
VOUT
4.76
0.1
5.5
V
0.1V
VIL or VIH
0.001
Maximum
Conditions
VOUT
VIN
4.5
Leakage Current
Units
IOH
Maximum LOW Level
Maximum Input
ICCT
VCC
VIN
PA
20.0
1.65V Maximum
3.85V Minimum
VCC
or GND
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 9)
fMAX
tPLH
tPHL
tPLH
tPHL
Min
Typ
TA
40qC to 85qC
CL
Max
Min
50 pF
Units
Max
Maximum Clock
3.3
100
125
95
Frequency
5.0
140
160
125
Propagation Delay
3.3
3.5
8.0
12.0
2.5
13.0
CDn or SDn to Qn or Qn
5.0
2.5
6.0
9.0
2.0
10.0
Propagation Delay
3.3
4.0
10.5
12.0
3.5
13.5
CDn or SDn to Qn or Qn
5.0
3.0
8.0
9.5
2.5
10.5
Propagation Delay
3.3
4.5
8.0
13.5
4.0
16.0
CPn to Qn or Qn
5.0
3.5
6.0
10.0
3.0
10.5
Propagation Delay
3.3
3.5
8.0
14.0
3.5
14.5
CPn to Qn or Qn
5.0
2.5
6.0
10.0
2.5
10.5
MHz
ns
ns
ns
ns
Note 9: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
5
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74AC74 • 74ACT74
AC Operating Requirements for AC
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 10)
tS
tH
tW
trec
40qC to 85qC
TA
CL
Typ
50 pF
Units
Guaranteed Minimum
Set-up Time, HIGH or LOW
3.3
1.5
4.0
4.5
Dn to CPn
5.0
1.0
3.0
3.0
Hold Time, HIGH or LOW
3.3
2.0
0.5
0.5
Dn to CPn
5.0
1.5
0.5
0.5
CPn or CDn or SDn
3.3
3.0
5.5
7.0
Pulse Width
5.0
2.5
4.5
5.0
Recovery Time
3.3
2.5
0
0
CDn or SDn to CP
5.0
2.0
0
0
ns
ns
ns
ns
Note 10: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
AC Electrical Characteristics for ACT
Symbol
Parameter
Maximum Clock
fMAX
Frequency
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
tPLH
Propagation Delay
CPn to Qn or Qn
tPHL
Propagation Delay
CPn to Qn or Qn
VCC
TA
25qC
(V)
CL
50 pF
40qC to 85qC
TA
CL
Max
50 pF
Min
Units
(Note 11)
Min
Typ
Max
5.0
145
210
5.0
3.0
5.5
9.5
2.5
10.5
ns
5.0
3.0
6.0
10.0
3.0
11.5
ns
5.0
4.0
7.5
11.0
4.0
13.0.
ns
5.0
3.5
6.0
10.0
3.0
11.5
ns
125
MHz
Note 11: Voltage Range 5.0 is 5.0V r 0.5V
AC Operating Requirements for ACT
Symbol
Parameter
Set-up Time, HIGH or LOW
tS
Dn to CPn
tH
Hold Time, HIGH or LOW
Dn to CPn
tW
CPn or CDn or SDn
Pulse Width
trec
Recovery Time
CDn or SDn to CP
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
50 pF
Typ
Guaranteed Minimum
5.0
1.0
3.0
3.5
ns
5.0
0.5
1.0
1.0
ns
5.0
3.0
5.0
6.0
ns
5.0
2.5
0
0
ns
Note 12: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
VCC
OPEN
CPD
Power Dissipation Capacitance
35.0
pF
VCC
5.0V
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Units
(Note 12)
6
Conditions
74AC74 • 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
7
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74AC74 • 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74AC74 • 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
9
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74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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10