ispLSI and pLSI 1032E ® ® High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — In-System Programmable (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping Output Routing Pool D7 D6 D5 D4 D3 D2 D1 D0 C7 A0 C6 A2 C5 D Q Logic Array A3 D Q GLB C4 C3 A4 D Q A5 C2 C1 A6 A7 Output Routing Pool Output Routing Pool D Q A1 Global Routing Pool (GRP) B0 B1 B2 B3 B4 B5 B6 B7 C0 CLK Output Routing Pool 0139A(A1)-isp Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032E features 5-Volt in-system programmability and in-system diagnostic capabilities. The ispLSI 1032E device offers non-volatile reprogrammability of the logic, as well as the interconnects to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032E device, but multiplexes four input pins to control in-system programming. A functional superset of the ispLSI and pLSI 1032 architecture, the ispLSI and pLSI 1032E devices add two new global output enable pins. • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms The basic unit of logic on the ispLSI and pLSI 1032E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI and pLSI 1032E devices. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com 1032E_06 1 October 1998 Specifications ispLSI and pLSI 1032E Functional Block Diagram IN 7 IN 6 I/O 51 I/O 50 I/O 49 I/O 48 I/O 55 I/O 54 I/O 53 I/O 52 I/O 59 I/O 58 I/O 57 I/O 56 I/O 63 I/O 62 I/O 61 I/O 60 Figure 1. ispLSI and pLSI 1032E Functional Block Diagram RESET Input Bus Generic Logic Blocks (GLBs) Output Routing Pool (ORP) D7 D6 D5 D4 D3 D2 D1 GOE 1/IN 5 GOE 0/IN 4 D0 I/O 47 I/O 46 I/O 45 I/O 44 C7 C5 A2 C4 Global Routing Pool (GRP) A3 A4 C3 C2 A5 lnput Bus Output Routing Pool (ORP) I/O 8 I/O 9 I/O 10 I/O 11 C6 A1 lnput Bus I/O 4 I/O 5 I/O 6 I/O 7 A0 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 C1 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 A6 I/O 12 I/O 13 I/O 14 I/O 15 I/O 43 I/O 42 I/O 41 I/O 40 C0 A7 *SDI/IN 0 *MODE/IN 1 B0 B1 B2 B3 B4 B5 B6 B7 Clock Distribution Network Output Routing Pool (ORP) Megablock CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 Input Bus Y0 Y1 Y2 Y3 I/O 28 I/O 29 I/O 30 I/O 31 I/O 24 I/O 25 I/O 26 I/O 27 I/O 20 I/O 21 I/O 22 I/O 23 I/O 16 I/O 17 I/O 18 I/O 19 *SDO/IN 2 *SCLK/IN 3 *ispEN/NC *ISP Control Functions for ispLSI 1032E Only The devices also have 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI and pLSI 1032E devices are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI and pLSI 1032E devices). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI and pLSI 1032E device contains four Megablocks. 2 Specifications ispLSI and pLSI 1032E Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions SYMBOL PARAMETER MIN. MAX. UNITS Commercial TA = 0°C to + 70°C 4.75 5.25 V Industrial TA = -40°C to + 85°C 4.5 5.5 V Input Low Voltage 0 0.8 V Input High Voltage 2.0 VCC Supply Voltage VIL VIH Vcc+1 V Table 2-0005/1032E Capacitance (TA=25oC, f=1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS C1 Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) 8 pf VCC = 5.0V, VPIN = 2.0V C2 Y0 Clock Capacitance 15 pf VCC = 5.0V, VPIN = 2.0V Table 2-0006/1032E Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS 20 – Years 10000 – Cycles 100 – Cycles Data Retention ispLSI Erase/Reprogram Cycles pLSI Erase/Reprogram Cycles Table 2-0008/1032E 3 Specifications ispLSI and pLSI 1032E Switching Test Conditions Figure 2. Test Load GND to 3.0V Input Pulse Levels Input Rise and Fall Time 10% to 90% -125 ≤ 2 ns Others ≤ 3 ns Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 5V R1 Device Output See Figure 2 Table 2-0003/1032E 3-state levels are measured 0.5V from steady-state active level. Test Point CL* R2 Output Load Conditions (see Figure 2) TEST CONDITION R1 R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH -0.5V ∞ 390Ω 5pF Active Low to Z at VOL +0.5V 470Ω 390Ω 5pF A B C *CL includes Test Fixture and Probe Capacitance. 0213a Table 2-0004/1032E DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL CONDITION PARAMETER 3 MIN. TYP. MAX. UNITS VOL VOH IIL IIH IIL-isp IIL-PU IOS1 Output Low Voltage IOL= 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA ICC2, 4 Operating Power Supply Current VIL = 0.5V, VIH = 3.0V Commercial – 190 – mA fCLOCK = 1 MHz Industrial – 190 – mA Table 2-0007/1032E 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using eight 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC . 4 Specifications ispLSI and pLSI 1032E External Timing Parameters Over Recommended Operating Conditions 4 PARAMETER tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 1. 2. 3. 4. -125 -100 TEST COND. #2 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns A 2 Data Propagation Delay, Worst Case Path – 10.0 – 12.5 ns 125 – 100 – MHz 91.0 – 71.0 – MHz 167 – 125 – MHz 5.0 – 7.0 – ns A 3 DESCRIPTION 1 Clock Frequency with Internal Feedback MIN. MAX. MIN. MAX. 3 1 tsu2 + tco1 ) UNITS – 4 Clock Frequency with External Feedback ( – 5 Clock Frequency, Max. Toggle – 6 GLB Reg. Setup Time before Clock,4 PT Bypass A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 5.0 – 6.0 ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns – 9 GLB Reg. Setup Time before Clock 6.0 – 8.0 – ns – 10 GLB Reg. Clock to Output Delay – 6.0 – 7.0 ns – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns ( twh 1+ tw1 ) – 10.0 – 13.5 ns 5.0 – 6.5 – ns – 12.0 – 15.0 ns 15 Input to Output Disable – 12.0 – 15.0 ns 16 Global OE Output Enable – 7.0 – 9.0 ns C 17 Global OE Output Disable – 7.0 – 9.0 ns – 18 External Synchronous Clock Pulse Duration, High 3.0 – 4.0 – ns – 19 External Synchronous Clock Pulse Duration, Low 3.0 – 4.0 – ns – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0 – 3.5 – ns – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 – 0.0 – ns A 12 Ext. Reset Pin to Output Delay – 13 Ext. Reset Pulse Duration B 14 Input to Output Enable C B Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. 5 Table 2-0030A/1032E Specifications ispLSI and pLSI 1032E External Timing Parameters Over Recommended Operating Conditions 4 1. 2. 3. 4. #2 DESCRIPTION -90 1 -70 -80 MIN. MAX. MIN. MAX. MIN. MAX. UNITS A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 12.0 – 15.0 ns A 2 Data Propagation Delay, Worst Case Path – 12.5 – 15.0 – 17.5 ns A 3 Clock Frequency with Internal Feedback 3 90.0 – 80.0 – 70.0 – MHz 69.0 – 61.0 – 56.0 – MHz – 4 Clock Frequency with External Feedback ( ( 1 twh + tw1 1 tsu2 + tco1 ) ) – 5 Clock Frequency, Max. Toggle – 6 GLB Reg. Setup Time before Clock,4 PT Bypass A 7 GLB Reg. Clock to Output Delay, ORP Bypass – – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 9 GLB Reg. Setup Time before Clock 8.5 – 10 GLB Reg. Clock to Output Delay – – 11 GLB Reg. Hold Time after Clock 0.0 A 12 Ext. Reset Pin to Output Delay 125 7.5 – 103 NEW 2E-10 DES 0 FOR IGN S tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 TEST COND. – 111 – 100 – MHz – 8.5 – 9.0 – ns 6.0 – 6.5 – 7.0 ns – 0.0 – 0.0 – ns – 10.0 – 11.0 – ns 7.0 – 7.5 – 8.0 ns – 0.0 – 0.0 – ns 13.5 – 14.0 – 15.0 ns – 8.0 – 10.0 – ns 15.0 – 16.5 – 18.0 ns – 15.0 – 16.5 – 18.0 ns – 9.0 – 10.0 – 12.0 ns – 9.0 – 10.0 – 12.0 ns – 13 Ext. Reset Pulse Duration 6.5 B 14 Input to Output Enable C 15 Input to Output Disable USE PARAMETER – B 16 Global OE Output Enable C 17 Global OE Output Disable – 18 External Synchronous Clock Pulse Duration, High 4.0 – 4.5 – 5.0 – ns – 19 External Synchronous Clock Pulse Duration, Low 4.0 – 4.5 – 5.0 – ns – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.5 – 3.5 – 4.0 – ns – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – 0.0 – 0.0 – ns 0.0 Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. 6 Table 2-0030B/1032E Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 PARAM. # 2 -125 DESCRIPTION -100 MIN. MAX. MIN. MAX. UNITS Inputs tiobp tiolat tiosu tioh tioco tior tdin 22 I/O Register Bypass – 0.3 – 0.3 ns 23 I/O Latch Delay – 1.9 – 2.3 ns 24 I/O Register Setup Time before Clock 3.0 – 3.5 – ns 25 I/O Register Hold Time after Clock 0.0 – 0.0 – ns 26 I/O Register Clock to Out Delay – 4.6 – 5.0 ns 27 I/O Register Reset to Out Delay – 4.6 – 5.0 ns 28 Dedicated Input Delay – 2.3 – 2.7 ns 29 GRP Delay, 1 GLB Load – 1.8 – 1.9 ns 30 GRP Delay, 4 GLB Loads – 2.0 – 2.4 ns 31 GRP Delay, 8 GLB Loads – 2.3 – 2.4 ns GRP tgrp1 tgrp4 tgrp8 tgrp16 tgrp32 32 GRP Delay, 16 GLB Loads – 2.8 – 3.0 ns 33 GRP Delay, 32 GLB Loads – 3.8 – 4.2 ns 34 4 Prod.Term Bypass Path Delay (Combinatorial) – 3.9 – 5.3 ns 35 4 Prod. Term Bypass Path Delay (Registered) – 4.0 – 5.3 ns 36 1 Prod.Term/XOR Path Delay – 3.6 – 4.6 ns 37 20 Prod. Term/XOR Path Delay – 5.0 – 5.8 ns 38 XOR Adjacent Path Delay 3 – 5.0 – 6.3 ns 39 GLB Register Bypass Delay – 0.4 – 1.0 ns 40 GLB Register Setup Time before Clock 0.1 – 0.5 – ns 41 GLB Register Hold Time after Clock 4.5 – 5.8 – ns 42 GLB Register Clock to Output Delay – 2.3 – 2.5 ns 43 GLB Register Reset to Output Delay – 4.9 – 6.2 ns 44 GLB Prod.Term Reset to Register Delay – 3.9 – 4.5 ns GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 45 GLB Prod. Term Output Enable to I/O Cell Delay – 5.4 – 7.2 ns 2.9 4.0 3.5 4.7 ns 47 ORP Delay – 1.0 – 1.0 ns 48 ORP Bypass Delay – 0.0 – 0.0 ns 46 GLB Prod. Term Clock Delay ORP torp torpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Table 2-0036A/1032E Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 PARAM. # 2 -70 -80 -90 DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNITS Inputs tiobp tiolat tiosu tioh tioco tior tdin 22 I/O Register Bypass – 0.3 – 0.3 – 0.3 ns 23 I/O Latch Delay – 2.3 – 2.7 – 3.3 ns 24 I/O Register Setup Time before Clock 3.5 – 3.5 – 4.0 – ns 25 I/O Register Hold Time after Clock 0.0 – 0.0 – 0.0 – ns 26 I/O Register Clock to Out Delay – 5.0 – 5.4 – 6.1 ns 27 I/O Register Reset to Out Delay – 5.0 – 5.4 – 6.0 ns 28 Dedicated Input Delay – 2.6 – 2.8 – 2.8 ns 29 GRP Delay, 1 GLB Load – 2.1 – 2.2 – 2.5 ns 30 GRP Delay, 4 GLB Loads – 2.3 – 2.5 – 2.5 ns 31 GRP Delay, 8 GLB Loads – 2.6 – 2.8 – 3.2 ns 3.2 – 3.5 – 4.0 ns 4.4 – 4.8 – 5.6 ns 5.7 – 7.1 – 8.8 ns 6.1 – 6.7 – 7.2 ns 5.6 – 6.6 – 8.3 ns 6.8 – 7.8 – 8.7 ns 7.1 – 8.2 – 9.2 ns ns tgrp1 tgrp4 tgrp8 tgrp16 tgrp32 32 GRP Delay, 16 GLB Loads – 33 GRP Delay, 32 GLB Loads – 34 4 Prod.Term Bypass Path Delay (Combinatorial) – 35 4 Prod. Term Bypass Path Delay (Registered) – 36 1 Prod.Term/XOR Path Delay – 37 20 Prod. Term/XOR Path Delay – 38 XOR Adjacent Path Delay 3 – 39 GLB Register Bypass Delay – 0.4 – 1.3 – 1.6 40 GLB Register Setup Time before Clock 0.2 – 0.5 – 0.5 – ns 41 GLB Register Hold Time after Clock 6.8 – 7.9 – 8.8 – ns 42 GLB Register Clock to Output Delay – 2.9 – 2.9 – 2.9 ns 43 GLB Register Reset to Output Delay – 6.3 – 6.4 – 6.8 ns 44 GLB Prod.Term Reset to Register Delay – 5.1 – 5.5 – 5.8 ns 45 GLB Prod. Term Output Enable to I/O Cell Delay – 7.1 – 8.0 – 9.0 ns 4.1 5.3 4.5 5.8 4.8 6.2 ns – 1.0 – 1.0 – 1.0 ns – 0.0 – – 0.0 ns USE GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 103 NEW 2E-10 DES 0 FOR IGN S GRP 46 GLB Prod. Term Clock Delay ORP torp torpbp 47 ORP Delay 48 ORP Bypass Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 8 0.0 Table 2-0036B/1032E Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 PARAM. # -125 DESCRIPTION -100 MIN. MAX. MIN. MAX. UNITS Outputs tob tsl toen todis tgoe 49 Output Buffer Delay – 1.3 – 2.0 ns 50 Output Buffer Delay, Slew Limited Adder – 9.9 – 10.0 ns 51 I/O Cell OE to Output Enabled – 4.3 – 5.1 ns 52 I/O Cell OE to Output Disabled – 4.3 – 5.1 ns 53 Global OE – 2.7 – 3.9 ns 54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk) 1.4 1.4 1.5 1.5 ns 55 Clk Delay, Y1 or Y2 to Global GLB Clk Line 1.4 1.4 1.5 1.5 ns 56 Clk Delay, Clock GLB to Global GLB Clk Line 0.8 1.8 0.8 1.8 ns 57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line 0.0 0.0 0.0 0.0 ns 58 Clk Delay, Clk GLB to I/O Cell Global Clk Line 0.8 1.8 0.8 1.8 ns – 2.8 – 4.3 ns Clocks tgy0 tgy1/2 tgcp tioy2/3 tiocp Global Reset tgr 59 Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 9 Table 2-0037A/1032E Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 PARAM. # -80 -90 DESCRIPTION -70 MIN. MAX. MIN. MAX. MIN. MAX. UNITS 1.7 – 2.1 – 2.6 ns 10.0 – 10.0 – 10.0 ns 5.3 – 5.7 – 6.2 ns 5.3 – 5.7 – 6.2 ns 3.7 – 4.3 – 5.8 ns 1.4 1.4 1.5 1.5 1.5 1.5 ns 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.4 2.9 2.6 3.1 1.5 1.5 ns 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 1.8 0.8 1.8 0.8 1.8 ns 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 0.0 0.0 0.0 0.0 0.0 0.0 ns 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 1.8 0.8 1.8 0.8 1.8 ns – 4.5 – 4.5 – 4.6 ns 49 Output Buffer Delay – 50 Output Buffer Delay, Slew Limited Adder – 51 I/O Cell OE to Output Enabled – 52 I/O Cell OE to Output Disabled – 53 Global OE – Clocks tgy0 tgy1/2 tgcp tioy2/3 tiocp 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Global Reset tgr 59 Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 10 103 NEW 2E-10 DES 0 FOR IGN S tob tsl toen todis tgoe USE Outputs Table 2-0037B/1032E Specifications ispLSI and pLSI 1032E ispLSI and pLSI 1032E Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In #34 #28 I/O Pin (Input) #59 Comb 4 PT Bypass GLB Reg Bypass ORP Bypass #22 #30 #35 #39 #48 Input D Register Q RST #23 - 27 GRP Loading Delay 20 PT XOR Delays GLB Reg Delay ORP Delay #29, 31 - 33 #36 - 38 I/O Reg Bypass GRP4 Reg 4 PT Bypass D Q #49, 50 #51, 52 #47 RST #59 Reset Clock Distribution Y1,2,3 #55 - 58 #40 - 43 Control RE PTs OE #44 - 46 CK 0491 #54 Y0 #53 GOE 0,1 Derivations of tsu, th and tco from the Product Term Clock 1 tsu = = = 2.2 ns = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) – (#22 + #30 + #46) (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9) th = = = 3.5 ns = Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0) tco = = = 10.9 ns = Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3) Derivations of tsu, th and tco from the Clock GLB 1 tsu = = = 2.9 ns = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) – (#54 + #42 + #56) (0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8) th = = = 2.7 ns = Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#41) – (#22 + #30 + #37) (1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0) tco = = = 5.5 ns = Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3) 1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032E-125. Table 2-0042a/1032E 11 I/O Pin (Output) Specifications ispLSI and pLSI 1032E Maximum GRP Delay vs GLB Loads 6.0 GRP Delay (ns) ispLSI and pLSI 1032E-70 5.0 ispLSI and pLSI 1032E-80 ispLSI and pLSI 1032E-90/100 4.0 ispLSI and pLSI 1032E-125 3.0 2.0 1.0 1 4 8 16 32 GLB Load GRP/GLB/1032E Power Consumption Power consumption in the ispLSI and pLSI 1032E device depends on two primary factors: the speed at which the device is operating, and the number of product terms used. Figure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax 350 ispLSI and pLSI 1032E ICC (mA) 300 250 200 150 100 0 20 40 60 80 100 125 150 fmax (MHz) Notes: Configuration of eight 16-bit counters Typical current at 5V, 25°C I CC can be estimated for the ispLSI and pLSI 1032E using the following equation: I CC (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The I CC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions and the program in the device, the actual I CC should be verified. 0127/1032E 12 Specifications ispLSI and pLSI 1032E Pin Description PLCC PIN NUMBERS NAME 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17, 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18 DESCRIPTION 20, Input/Output Pins - These are the general purpose I/O pins used by the logic 28, array. 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 5, 9 I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 3, 7, 11, 15, GOE 0/IN 43 67 66 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. GOE 1/IN 53 84 87 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. IN 6, IN 7 2, ispEN/NC1,2 23 14 SDI/IN 02 25 16 MODE/IN 12 42 37 SDO/IN 22 44 39 Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high. SCLK/IN 32 61 60 Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated input pin when ispEN is logic high. RESET 24 15 Y0 20 11 Y1 66 65 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Y2 63 62 Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Y3 62 61 Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. GND VCC 1, NC1 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 4, 8, 12, 16, TQFP PIN NUMBERS 19 22, 21, 65 17, 21, 29, 33, 40, 44, 48, 56, 67, 71, 79, 83, 90, 94, 98, 6, 89, 43, 64 18, 22, 30, 34, 41, 45, 53, 57, 68, 72, 80, 84, 91, 95, 3, 7, 19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 4, 8, Dedicated input pins to the device. 10 Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 is also used as one of the two control pins for the isp state machine. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. 13, 38, 12, 64 63, 1, 26, 51, 76, 24, 49, 74, 99, 2, 27, 52, 77, 88 Ground (GND) Vcc 25, No connect. 50, 75, 100 1. NC pins are not to be connected to any ative signals, Vcc or GND. 2. Pins have dual function capability for ispLSI 1032E only. 3. Pins have dual function capability which is software selectable. 13 Table 2-0002A/1032E Specifications ispLSI and pLSI 1032E Pin Configurations I/O 39 I/O 40 I/O 41 I/O 42 GND I/O 43 IN 6 I/O 44 I/O 48 I/O 45 I/O 49 I/O 46 I/O 50 I/O 47 I/O 51 GOE 1/IN 53 I/O 52 11 10 9 I/O 53 I/O 54 I/O 55 I/O 56 ispLSI and pLSI 1032E 84-Pin PLCC Pinout Diagram 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O 57 12 74 I/O 38 I/O 58 13 73 I/O 37 I/O 59 14 72 I/O 36 I/O 60 15 71 I/O 35 I/O 61 16 70 I/O 34 I/O 62 17 69 I/O 33 I/O 63 18 68 I/O 32 IN 7 19 67 GOE 0/IN 43 Y0 20 66 Y1 65 VCC 64 GND 63 Y2 VCC 21 GND 22 1,2ispEN/NC 23 ispLSI 1032E pLSI 1032E RESET 24 Top View 62 Y3 0 25 61 SCLK/IN 32 I/O 0 26 60 I/O 31 I/O 1 27 59 I/O 30 I/O 2 28 58 I/O 29 I/O 3 29 57 I/O 28 I/O 4 30 56 I/O 27 I/O 5 31 55 I/O 26 I/O 6 32 54 I/O 25 2SDI/IN I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 2 GND 2SDO/IN 1 I/O 15 2MODE/IN I/O 14 I/O 13 I/O 12 I/O 11 I/O 9 I/O 10 I/O 8 I/O 7 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 1. NC pins are not to be connected to any active signals, Vcc or GND. 2. Pins have dual function capability for ispLSI 1032E only (except pin 23, which is ispEN only). 3. Pins have dual function capability which is software selectable. 0123-32-isp 14 Specifications ispLSI and pLSI 1032E Pin Configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ispLSI 1032E Top View 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 GOE 0/IN 42 Y1 VCC GND Y2 Y3 SCLK/IN 31 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 NC NC NC NC I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 1MODE/IN1 GND 1SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 VCC GND ispEN RESET 1SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND GOE 1/IN 52 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 NC NC ispLSI 1032E 100-Pin TQFP Pinout Diagram 1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. 0766A-32E-isp 15 Specifications ispLSI and pLSI 1032E Part Number Description (is)pLSI 1032E – XXX X X X Device Family Grade Blank = Commercial I = Industrial Device Number Package J = PLCC T = TQFP Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 90 = 90 MHz fmax 80 = 80 MHz fmax 70 = 70 MHz fmax Power L = Low 0212/1032E ispLSI and pLSI 1032E Ordering Information 7.5 ispLSI 1032E-125LJ 125 7.5 ispLSI 1032E-125LT 100 10 ispLSI 1032E-100LJ 100 10 ispLSI 1032E-100LT 90 10 ispLSI 1032E-90LJ* 84-Pin PLCC 90 10 ispLSI 1032E-90LT* 100-Pin TQFP 80 12 ispLSI 1032E-80LJ* 84-Pin PLCC 80 12 ispLSI 1032E-80LT* 100-Pin TQFP 70 15 ispLSI 1032E-70LJ 84-Pin PLCC ispLSI 1032E-70LT 100-Pin TQFP pLSI 1032E-125LJ 84-Pin PLCC pLSI 1032E-100LJ 84-Pin PLCC pLSI 1032E-90LJ* 84-Pin PLCC pLSI 1032E-80LJ* 84-Pin PLCC pLSI 1032E-70LJ 84-Pin PLCC 15 7.5 100 10 90 10 80 12 70 15 PACKAGE si de al l 70 125 ORDERING NUMBER gn 125 ne w pLSI tpd (ns) SI fo r ispLSI fmax (MHz) pL FAMILY s. COMMERCIAL 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP Table 2-0041A/1032E is *Use ispLSI 1032E-100 for all new designs. se INDUSTRIAL fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 70 15 ispLSI 1032E-70LJI 84-Pin PLCC 70 15 ispLSI 1032E-70LTI 100-Pin TQFP U FAMILY Table 2-0041B/1032E N ot e: ispLSI 16