MICREL MIC2550AYTS

MIC2550A
Micrel, Inc.
MIC2550A
Universal Serial Bus Transceiver
General Description
Features
The MIC2550A is a single-chip transceiver that complies with
the physical layer specifications for Universal Serial Bus
(USB).
The MIC2550A supports full-speed (12Mbps) and low-speed
(1.5Mbps) operation and introduces superior edge rate control to produce crisper eye diagrams. As a result, the task of
passing USB compliance testing is made easier.
A unique, patented, dual supply voltage operation allows the
MIC2550A to reference the system I/F I/O signals to a supply
voltage down to 2.5V while independently powered by the
USB VBUS. This allows the system interface to operate at its
core voltage without addition of buffering logic and also
reduce system operating current.
• Compliant to USB Specification Revision 2.0 for
low-speed (1.5Mbps) and full-speed (12Mbps) operation
• Compliant to IEC-61000-4.2 (Level 2)
• Operation down to 2.5V
• Dual supply voltage operation
• Integrated speed-select termination supply
• Very low power consumption meets USB suspendcurrent requirements
• Small 14-pin TSSOP and 16-pin MLF™ packages
Applications
• Personal digital assistants (PDA)
• Palmtop computers
• Cellular telephones
Ordering Information
Part Number
Standard
Pb-Free
Package
MIC2550ABTS
MIC2550AYTS
14-Pin TSSOP
MIC2550ABML
MIC2550AYML
16-Pin MLF™
System Diagram
System
Supply Voltage
1.5k
MIC2550A
VIF
HIGH
SPEED
VTRM
LOW
SPEED
SPD VBUS
0.47µF
System
Interface
OE#
D+
RCV
D–
VP
D–
VM
GND
VBUS
RS
D+
24Ω
RS
D–
GND
USB
Interface
Connector
24Ω
1µF
SUS
GND
1µF min
10µF max
Cooper Electronics Technologies
41206ESDA SurgX
(See “Applications Information”
for additional suppliers.)
MicroLeadFrame and MLF are trademarks of Amkor Technology.
SurgX is a registered trademark of Cooper Electronics Technologies.
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2005
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M9999-031805
MIC2550A
Micrel, Inc.
VIF 1
NC
VIF
VBUS
NC
Pin Configuration
14 VBUS
SPD 2
13 NC
RCV 3
12 VTRM
SPD
1
12
VTRM
VP 4
11 D+
RCV
2
11
VM 5
10 D–
VP
VM
3
4
10
9
D+
D–
OE#
NC 6
9 OE#
GND 7
8 SUS
16 15 14 13
NC
GND
SUS
NC
5 6 7 8
14-Pin TSSOP (TM)
16-Pin MLF™ (ML)
Pin Description
Pin Name
Pin Number
Pin Number
MIC2550ABTS
MIC2550ABML
VIF
1
15
System Interface Supply Voltage (Input): Determines logic voltage levels for
system interface signaling to logic controller.
SPD
2
1
Speed (Input): Edge rate control. Logic high selects full-speed edge rates.
Logic low selects low-speed edge rates.
RCV
3
2
Receive Data (Output): System interface receive data interface to logic
controller.
VP
4
3
Plus (Input/Output): System interface signal to logic controller. If OE# is
logic 1, VP is a receiver output (+); If OE# is logic 0, VP is a driver input (+).
VM
5
4
Minus (Input/Output): System interface signal to logic controller. If OE# is
logic 1, VM is a receiver output (–); If OE# is logic 0, VM is a driver input (–).
NC
6, 13
5, 8, 13 16
GND
7
6
Ground: Power supply return and signal reference.
SUS
8
7
Suspend (Input): Logic high turns off internal circuits to reduce supply
current.
OE#
9
9
Output Enable (Input): Active low system interface input signal from logic
controller. Logic low causes transceiver to transmit data onto the bus. Logic
high causes the transceiver to receive data from the bus.
D–
10
10
USB Differential Data Line – (Input/Output)
D+
11
11
USB Differential Data Line + (Input/Output)
VTRM
12
12
Termination Supply (Output): 3.3V speed termination resistor supply output.
VBUS
14
14
USB Supply Voltage (Input): Transceiver supply.
M9999-031805
Pin Function
Not internally connected
2
March 2005
MIC2550A
Micrel, Inc.
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 2)
Supply Voltage (VIF) ................................................... +6.5V
Input Voltage (VBUS) ........................ –0.5V(min)/5.5V(max)
Output Current (ID+, ID–) ........................................... ±50mA
Output Current (all others) ....................................... ±15mA
Input Current ............................................................ ±50mA
Storage Temperature (TS) ......................... –65° to +150°C
ESD, Note 3
VBUS, D+, D– ......................................................... ±10kV
All other pins ........................................................... ±2kV
Supply Voltage (VBUS) ................................. 4.0V to 5.25V
Temperature Range (TA) ........................... –40°C to +85°C
Junction Temperature (TJ) ........................................ 160°C
Package Thermal Resistance
TSSOP (θJA) ..................................................... 100°C/W
Electrical Characteristics (Note 8)
TA = 25°C, bold values indicate –40°C ≤ TA ≤ +85°C; typical values at VBUS = 5.0V, VIF = 3.0V; minimum and maximum values at
VBUS = 4.0V to 5.25V, IFV = 2.5V to 3.6V; unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
System and USB Interface DC Characteristics
VBUS
USB Supply Voltage
4.0
5.25
V
VIF
System I/F Supply Voltage
2.5
5.25
V
VIL
Low-Level Input Voltage, Note 4
0.15VIF
V
VIH
High-Level Input Voltage, Note 4
VOH
High-Level Output Voltage, Note 4
IOH = 20µA
VOL
Low-Level Output Voltage, Note 4
IOL = 20µA
IIL
Input Leakage Current, Note 4
Symbol
Parameter
IIF
IVBUS
VTRM
VIF Supply Current
VBUS Supply Current
Termination Voltage
Conditions
Voltage
0.85VIF
V
0.9VIF
V
Min
0.1
V
±5
µA
Typ
Max
Units
SPD
SUS
OE#
Load
1
0
1
1
5
µA
1
0
0
1
5
µA
0
0
1
1
5
µA
0
0
0
VBUS = 5.25V
1
5
µA
0
1
0
VIF = 3.6V
1
0
0
0
0
0
1
0
1
0
0
0
1
5
µA
325
650
µA
40
75
µA
1
800
1100
µA
0
3000
5000
µA
0
1
230
350
µA
0
0
400
700
µA
0
1
0
VBUS = 5.25V
130
200
µA
1
0
0
VIF = 3.6V
7.3
10
mA
0
0
0
3.6
5
mA
3.6
V
f = 6MHz CLOAD
= 50 pF, Note 7
f = 750kHz
CLOAD = 600 pF
Note 7
f = 6MHz CLOAD
= 50 pF, Note 7
f = 750kHz
CLOAD = 600 pF
Note 7
ITRM = 2.5mA
3.0
ESD Protection
IEC-1000-4-2 Air Discharge
10 pulses
±6
kV
(D+, D–,
VBUS only)
10 pulses
±6
kV
March 2005
Contact Discharge
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M9999-031805
MIC2550A
Symbol
Micrel, Inc.
Parameter
Condition
Min
Typ
Max
Units
+10
µA
Transceiver DC Characteristics
ILO
Hi-Z State Data Line Leakage
0V < VBUS < 3.3V, D+, D–, OE# = 1 pins only
–10
VDI
Differential Input Sensitivity
|(D+) – (D–)|, VIN = 0.8V – 2.5V
0.2
VCM
Differential Common-Mode Range
Includes VDI range
0.8
2.5
V
VSE
Single-Ended Receiver Threshold
0.8
2.0
V
Receiver Hysteresis, Note 6
V
200
VOL
Static Output Low, Note 5
OE# = 0, RL = 1.5kΩ to 3.6V
VOH
Static Output High, Note 5
OE# = 0, RL = 15kΩ to GND
VCRS
Output Signal Crossover Voltage
Note 6
CIN
Transceiver Capacitance, Note 6
Pin to GND
ZDRV
Driver Output Resistance
Steady state drive, Note 6
6
CL = 50pF
CL = 600pF
75
CL = 50pF
CL = 600pF
75
T R ÷ TF
mV
0.3
V
2.8
3.6
V
1.3
2.0
V
20
pF
18
Ω
300
ns
ns
300
ns
ns
80
125
%
1.3
2.0
V
Low-Speed Driver Characteristics, Note 7
tR
Transition Rise Time
tF
Transition Fall Time
tR/tF
Rise and Fall Time Matching
VCRS
Output Signal Crossover Voltage
Full-Speed Driver Characteristics, Note 7
tR
Transition Rise Time
CL = 50pF
4
20
ns
tF
Transition Fall Time
CL = 50pF
4
20
ns
tR/tF
Rise and Fall Time Matching
T R ÷ TF
90
111.11
%
VCRS
Output Signal Crossover Voltage
1.3
2.0
V
15
ns
Transceiver Timing, Note 7
tPVZ
OE# to RCVR Tri-state Delay
Figure 1
tPZD
Receiver Tri-state to Transmit Delay
Figure 1
tPDZ
OE# to DRVR Tri-state Delay
Figure 1
tPZV
Driver Tri-state to Receiver Delay
Figure 1
tPLH
V+/V– to D+/D– Propagation Delay
Figure 4
15
ns
tPHL
V+/V– to D+/D– Propagation Delay
Figure 4
15
ns
tPLH
D+/D– to RCV Propagation Delay
Figure 3
15
ns
tPHL
D+/D– to RCV Propagation Delay
Figure 3
15
ns
tPLH
D+/D– to V+/D– Propagation Delay
Figure 3
8
ns
tPHL
D+/D– to V+/D– Propagation Delay
Figure 3
8
ns
15
15
15
Note 1.
Exceeding the absolute maximum rating may damage the device.
Note 2.
The device is not guaranteed to function outside its operating rating.
Note 3.
Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
Note 4.
Applies to the VP, VM, RCV, OE#, SPD, and SUS pins.
Note 5.
Applies to D+, D–.
Note 6.
Not production tested. Guaranteed by design.
Note 7.
Characterized specification(s), but not production tested.
M9999-031805
ns
4
ns
ns
March 2005
MIC2550A
Micrel, Inc.
Timing Diagrams
H
VOE#
L
tPVZ
tPZV
VP
VP/VM
VM
tPZD
VD+
VD+/VD–
VD–
Figure 1. Enable and Disable Times
VD+
Differential 90%
Data
Lines 10%
VD–
VCRS
tR
tF
Figure 2. Rise and Fall Times
Differential VD+
Data
Lines V
D–
tPLH
tPHL
VOH
Output V
OL
VSS
Figure 3. Receiver Propagation Delay D+/D– to RCV, VP, and VM
VOI
Input V
OL
VSS
tPLH
tPHL
Differential VD+
Data
Lines V
D–
Figure 4. Driver Propagation Delay VP and VM to D+/D–
March 2005
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M9999-031805
MIC2550A
Micrel, Inc.
OE# = 0 (Transmit):
Input
Output
VP
VM
D+
D–
RCV
Result
0
0
0
0
X
SE0
0
1
0
1
0
Logic 0
1
0
1
0
1
Logic 1
1
1
1
1
X
Undefined
OE# = 1 (Receive):
Input
Output
D+
D–
VP
VM
RCV
Result
0
0
0
0
X
SE0
0
1
0
1
0
Logic 0
1
0
1
0
1
Logic 1
1
1
1
1
X
Undefined
Note. X = undefined.
Table 1. Truth Table
Test Circuits
Test
Point
Device
Under
Test
500Ω
24Ω
V
50pF
For D+, D–:
V = 0V for tPZH and tPHZ
V = VBUS for tPZL and tPLZ
Figure 5. Load for Enable and Disable Time (D+, D–)
Device
Under
Test
25pF
Figure 6. VP, VM and RCV Load
VTRM
Device
Under
Test
1.5kΩ*
24Ω
15kΩ
CL
CL = 50pF, full speed
CL = 50pF, low speed (minimum timing)
CL = 600pF, low speed (maximum timing)
*1.5k on D– for low speed or D+ for high speed
Figure 7. D+ and D– Load
M9999-031805
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March 2005
MIC2550A
Micrel, Inc.
Block Diagram
SYSTEM I/F
VOLTAGE DOMAIN
VIF
USB VOLTAGE DOMAIN
Regulator
VBUS
VTRM
TO
INTERNAL
CIRCUITS
SPD
D–
D+
OE#
RCV
VP
VM
SUS
GND
March 2005
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M9999-031805
MIC2550A
Micrel, Inc.
Internal 3.3V Source
If the device is self-powered and has 3.3V available, the
circuit in Figure 10 is yet another power supply configuration
option. In this configuration, the internal regulator is disabled
and the 3.3V source and not VBUS powers the entire chip.
Applications Information
The MIC2550A is designed to provide USB connectivity in
mobile systems where system supply voltages are not available to satisfy USB requirements. The MIC2550A can operate down to supply voltages of 2.5V and still meet USB
physical layer specifications. As shown in the system diagram, the MIC2550A takes advantage of USB’s supply
voltage, VBUS, to operate the transceiver. The system voltage, VIF, is used to set the reference voltage used by the
digital I/O lines (VP, VM, RCV, OE#, SPD, and SUS pins)
interfacing to the system. Internal circuitry provides translation between the USB and system voltage domains. VIF will
typically be the main supply voltage rail for the system.
In addition, a 3.3V, 10% termination supply voltage, VTRM, is
provided to support speed selection. A 0.47µF (minimum)
capacitor from VTRM to ground is required to ensure stability.
A 1.5K resistor is required between this pin and the D+ or D–
lines to respectively specify full-speed or low-speed operation.
Power Supply Configurations
VIF /VBUS Switched
When the VBUS input pin is pulled to ground a low impedance
path between VIF and VBUS can cause a high current flow
from VIF to VBUS thereby damaging the MIC2550A. This
issue can arise in systems where VBUS is driven from a power
supply that can be switched off such as in the case of a
desktop PC. Adding a Schottky diode, such as the ZHCS1000
by Zetex, in series with VBUS will prevent any current flow
during this condition. A solution is shown in Figure 8 below.
If the VIF source is current limited to less than 50mA, then
diode D1 is not necessary.
MIC2550
USB Device
Power Controller
VIF
MIC2550A
VIF
VTRM
Figure 10. Powering Chip
from Internal 3.3V Source
Suspend
When the suspend pin (SUS) is high, power consumption is
reduced to a minimum. VTRM is not disabled. RCV, VP and VM
are still functional to enable the device to detect USB activity.
For minimal current consumption in suspend mode, it is
recommended that OE# = 1, and SPD = 0.
Speed
The speed pin (SPD) sets D+/D– output edge rates by increasing or decreasing biasing current sources within the output
drivers. For low speed, SPD = 0. For full speed, SPD = 1. By
setting SPD = 0 during idle periods, in conjunction with suspend
(SUS), the lowest quiescent current can be obtained. However,
designers must provide a 300ns delay between changing SPD
from 0 to 1 and transmission of data at full speed. This delay
ensures the output drivers have arrived at their proper operating
conditions. Failure to do so can result in leading edge distortion
on the first few data bits transmitted.
External ESD Protection
The use of ESD transient protection devices is not required
for operation, but is recommended. We recommend the
following devices or the equivalent:
Cooper Electronics Technologies (www.cooperet.com)
41206ESDA SurgX®
0805ESDA SurgX®
D1
ZHCS1000 or
equivalent
VBUS
VBUS
*(Optional)
1µF min
Littelfuse (www.littlefuse.com)
V0402MHS05
SP0503BAHT
Non-multiplexed Bus
To save pin count for the USB logic controller interface, the
MIC2550A was designed with VP and VM as bidirectional
pins. To interface the MIC2550A with a non-multiplexed data
bus, resistors can be used for low cost isolation as shown in
Figure 11.
Note: *(Optional) See Text - Power Supply Configurations
Figure 8. Solution to VIF /VBUS Switching
I/O Interface Using 3.3V
In systems where the I/O interface utilizes a 3.3V USB
controller, an alternate solution is shown in Figure 9. This
configuration has the advantage over Figure 8, in that no
extra components are needed. Ensure that the load on VTRM
does not exceed 1mA total.
3.3V
USB Logic
Controller
(SIE)
MIC2550
VDD
VIF
VBUS
3.3V
VBUS
VBUS
MIC2550
VP
VP
10k
USB
Controller
VPO
I/O
VP/VM/
VTRM
RCV/OE#
VM
VM
10k
VMO
Figure 9. I/O Interface Using 3.3V
M9999-031805
Figure 11. MIC2550A Interface to
Non-multiplexed Data Bus
8
March 2005
MIC2550A
Micrel, Inc.
PCB Layout Recommendations
Although the USB standard and applications are not based in
an impedance controlled environment, a properly designed
PCB layout is recommended for optimal transceiver performance. The suggested PCB layout hints are as follows:
• Match signal line traces (VP/VM, D+, D–) to
40ps, approximately 1/3 inch if possible. FR-4
PCB material propagation is about 150ps/inch,
so to minimize skew try to keep VP/VM, D+/D–
traces as short as possible.
• For every signal line trace width (w), separate
the signal lines by 1.5–2 widths. Place all other
traces at >2w from all signal line traces.
• Maintain the same number of vias on each
differential trace, keeping traces approximately
at same separation distance along the line.
• Control signal line impedances to ±10%.
• Keep RS as close to the IC as possible, with
equal distance between RS and the IC for both
D+ and D–.
March 2005
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M9999-031805
MIC2550A
Micrel, Inc.
Package Information
4.50 (0.177)
6.4 BSC (0.252)
4.30 (0.169)
DIMENSIONS:
MM (INCH)
0.30 (0.012)
0.19 (0.007)
5.10 (0.200)
4.90 (0.193)
0.20 (0.008)
0.09 (0.003)
1.10 MAX (0.043)
0.65 BSC
(0.026)
1.00 (0.039) REF
8°
0°
0.15 (0.006)
0.05 (0.002)
0.70 (0.028)
0.50 (0.020)
14-Pin TSSOP (TS)
0.42 +0.18
–0.18
0.23 +0.07
–0.05
0.85 +0.15
–0.65
0.01 +0.04
–0.01
3.00BSC
1.60 +0.10
–0.10
0.65 +0.15
–0.65
0.20 REF.
2.75BSC
0.42
PIN 1 ID
+0.18
–0.18
N
16
1
1
0.50 DIA
2
2
2.75BSC 3.00BSC
3
3
1.60 +0.10
–0.10
4
4
12° max
0.42 +0.18
–0.18
SEATING
PLANE
CC
0.23 +0.07
–0.05
4
0.5BSC
0.40 +0.05
–0.05
1.5 REF
BOTTOM VIEW
TOP VIEW
CL
0.5 BSC
SECTION "C-C"
SCALE: NONE
0.01 +0.04
–0.01
1.
2.
3.
4.
DIMENSIONS ARE IN mm.
DIE THICKNESS ALLOWABLE IS 0.305mm MAX.
PACKAGE WARPAGE MAX 0.05mm.
THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.20mm AND 0.25mm FROM TIP.
5. APPLIES ONLY FOR TERMINALS
Rev. 02
16-Pin MLF™ (ML)
M9999-031805
10
March 2005
MIC2550A
Micrel, Inc.
16-Pin MLF™ (ML)
MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2003 Micrel, Incorporated.
March 2005
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M9999-031805