QUAD 4-INPUT OR/NOR GATE FEATURES SY10E101 SY100E101 DESCRIPTION ■ ■ ■ ■ 500ps max. propagation delay Extended 100E VEE range of –4.2V to –5.5V True and complementary outputs Fully compatible with industry standard 10KH, 100K I/O levels ■ Internal 75KΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E101 ■ Available in 28-pin PLCC package The SY10/100E101 are quad 4-input OR/NOR gates designed for use in new, high-performance ECL systems. The E101 features both true and complementary outputs. Q1 D1d 18 Q2 D2c D2b VEE D2a 27 17 28 16 15 Q2 VCC Q1 14 Q1 D1d 3 13 Q0 D1c 4 12 Q0 2 D2a D2b D2c PLCC TOP VIEW J28-1 1 Q2 5 6 7 8 9 10 11 Q2 VCCO D1c Q1 26 D0c D0b D0a D1a D2d D1a D0d D1b VCCO Q3 Q3 25 24 23 22 21 20 19 Q0 D0d D0c Q0 D1b D0b D3a D0a D3b D3c D3d PIN CONFIGURATION BLOCK DIAGRAM D2d D3a D3b D3c Q3 Q3 D3d PIN NAMES Pin Function Dna, Dnb, Dnc, Dnd Data Inputs Q0-Q3 True Outputs Q0-Q3 Inverting Outputs VCCO VCC to Output Rev.: D 1 Amendment: /2 Issue Date: May, 1998 SY10E101 SY100E101 Micrel LOGIC EQUATION Qn = Dna + Dnb + Dnc + Dnd DC ELECTRICAL CHARACTERISTICS VEE = VEE(Min.) to VEE(Max.); VCC = VCCO = GND TA = –40°C Symbol Parameter IIH Input HIGH Current IEE Power Supply Current 10EL 100EL TA = 0°C TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. — — 150 — — 150 — — 150 — — 150 Unit µA mA — — 30 30 36 36 — — 30 30 36 36 — — 30 30 36 36 — — 30 35 36 42 AC ELECTRICAL CHARACTERISTICS VEE = VEE(Min.) to VEE(Max.); VCC = VCCO = GND TA = –40°C Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit tPLH tPHL Propagation Delay to Output D to Q 150 — 550 200 350 500 200 350 500 200 350 500 ps tskew Within-Device Skew(1) Within-Gate Skew(2) — — 50 25 — — — — 50 25 — — — — 50 25 — — — — 50 25 — — ps ps tr tf Rise/Fall Time 20% to 80% 275 — 625 300 380 575 300 380 575 300 380 575 ps NOTES: 1. Within-device skew is defined as identical transitions on similar paths through a device. 2. Within-gate skew is defined as the variation in propagation delays through a single gate when driven from its different inputs. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E101JC J28-1 Commercial SY10E101JCTR J28-1 SY100E101JC SY100E101JCTR Ordering Code Package Type Operating Range SY10E101JI J28-1 Industrial Commercial SY10E101JITR J28-1 Industrial J28-1 Commercial SY100E101JI J28-1 Industrial J28-1 Commercial SY100E101JITR J28-1 Industrial 2 SY10E101 SY100E101 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 3