(÷1, ÷2/3) OR (÷2, ÷4/6) CLOCK GENERATION CHIP FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The V BB output is designed to act as the switching reference for the input of the SY100S838/L under singleended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S838/L functions as a divide by 2 and by 4/6 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1 and by 2/3 clock chip. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S838/Ls in a system. 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input pull-down resistors Available in 20-pin SOIC package PIN CONFIGURATION VCC 20 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 19 18 17 16 15 14 13 12 11 TOP VIEW SOIC Z20-1 1 2 VCC EN ClockWorks™ SY100S838 SY100S838L 3 4 DIVSEL CLK 5 6 7 8 9 10 CLK VBB MR VCC NC F SEL TRUTH TABLE CLK EN MR Function Z L L Divide ZZ H L Hold Q0–3 X X H Reset Q0–3 NOTES: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition PIN NAMES Pin FSEL DIVSEL Q0, Q1 OUTPUTS Q2, Q3 OUTPUTS L L Divide by 2 Divide by 4 L H Divide by 2 Divide by 6 H L Divide by 1 Divide by 2 H H Divide by 1 Divide by 3 Function CLK Differential Clock Inputs FSEL Function Select Input EN Synchronous Enable MR Master Reset VBB Reference Output Q0, Q1 Differential ÷1 or ÷2 Outputs Q2, Q3 Differential ÷2/3 or ÷4/6 Outputs DIVSEL Frequency Select Input Rev.: E 1 Amendment: /1 Issue Date: August, 1998 ClockWorks™ SY100S838 SY100S838L Micrel BLOCK DIAGRAM CLK ÷1 CLK Q0 1 0 ÷2 Q0 Q1 Q1 EN ÷ 2 or ÷3 R Q2 1 0 ÷ 4 or ÷6 MR FSEL Q2 Q3 DIVSEL Q3 DC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IEE Power Supply Current VBB Output Reference Voltage IIH Input High Current NOTE: 1. Parametric values specified at: TA = 0°C 35 50 -1.38 — -1.26 -1.38 — — — 150 — 5 volt Power Supply Range 3 volt Power Supply Range 65 35 — 50 100S838 Series: 100S838L Series 2 65 35 -1.26 -1.38 150 — -4.2V to -5.5V. -3.0V to -3.8V. 50 — — 65 35 -1.26 -1.38 150 — Unit 54 75 mA — -1.26 V — 150 µA ClockWorks™ SY100S838 SY100S838L Micrel AC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit MHz fMAX Maximum Toggle Frequency 1000 — — 1000 — — 1000 — tPLH tPHL Propagation Delay to Output CLK ➝ Output (Diff.) CLK ➝ Output (S.E.) MR ➝ Q 950 900 600 — — — 1150 1200 900 950 900 600 — — — 1150 1200 900 970 920 600 — — — tskew Within-Device Skew(2) Q0 — Q3 — — 50 — — 50 — — 50 — — 50 Part-to-Part Q0 — Q3 (Diff.) — — 200 — — 200 — — 200 — — 200 tS Set-up Time EN ➝ CLK DIVSEL ➝ CLK 300 300 150 — — — 300 300 150 — — — 300 300 150 — — — 300 300 150 — — — ps tH Hold Time CLK ➝ EN CLK ➝ DIVSEL 400 400 150 200 — — 400 400 150 200 — — 400 400 150 200 — — 400 400 150 200 — — ps VPP Minimum Input Swing(3) CLK 250 — — 250 — — 250 — — 250 — — mV CLK (4) — -0.55 (4) — -0.55 (4) — -0.55 (4) — -0.55 V — — 100 — — 100 — — 100 — — 100 ps CLK MR 800 700 — — — — 800 700 — — — — 800 700 — — — — 800 700 — — — — ps Q 280 — 550 280 — 550 280 — 550 280 — 550 ps Range(4) VCMR Common Mode tRR Reset Recovery Time tPW Minimum Pulse Width tr tf Output Rise/Fall Times (20% —80%) — 1000 — — 1170 1050 1220 1000 900 600 — — — 1250 1300 900 ps ps NOTES: 1. Parametric values specified at: 5 volt Power Supply Range 100S838 Series: -4.2V to -5.5V. 3 volt Power Supply Range 100S838L Series -3.0V to -3.8V. 2. Skew is measured between outputs under identical transitions. 3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP (min) and 1.0V. The lower end of the CMR range is dependent on VEE and is equal to VEE +1.65V. TIMING DIAGRAM CLK Q (÷1) Q (÷2) Q (÷3) Q (÷4) Q (÷6) PRODUCT ORDERING CODE Ordering Code Package Type Operating Range VEE Range (V) Ordering Code SY100S838ZC Z20-1 Commercial -4.2 to -5.5 SY100S838ZCTR Z20-1 Commercial SY100S838LZC Z20-1 SY100S838LZCTR Z20-1 Package Type Operating Range VEE Range (V) SY100S838ZI Z20-1 Industrial -4.2 to -5.5 -4.2 to -5.5 SY100S838ZITR Z20-1 Industrial -4.2 to -5.5 Commercial -3.0 to -3.8 SY100S838LZI Z20-1 Industrial -3.0 to -3.8 Commercial -3.0 to -3.8 SY100S838LZITR Z20-1 Industrial -3.0 to -3.8 3 ClockWorks™ SY100S838 SY100S838L Micrel 20 LEAD SOIC .300" WIDE (Z20-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4