ClockWorks™ SY100EL15L ClockWorks™ 3.3V 1:4 CLOCK DISTRIBUTION Micrel SY100EL15L Synergy™ High-Speed Products FEATURES ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under singleended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2. 3.3V power supply 50ps output-to-output skew Low power Synchronous enable/disable Multiplexed clock input 75KΩ internal input pull-down resistors ESD protection of 2000V Available in 16-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM VCC 16 EN SCLK CLK CLK VBB SEL VEE 15 14 13 1 12 11 10 9 0 D Q 1 2 3 4 5 6 7 8 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 SOIC TOP VIEW PIN NAMES Pin TRUTH TABLE Function CLK SCLK SEL EN Q CLK Differential Clock Inputs L X L L L SCLK Synchronous Clock Input H X L L H EN Synchronous Enable X L H L L SEL Clock Select Input X H H L H VBB Reference Output X X X H L* Q0-3 Differential Clock Outputs © 1999 Micrel * On next negative transition of CLK or SCLK Rev.: A 1 Amendment: /0 Issue Date: December 1999 ClockWorks™ SY100EL15L Micrel ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit VEE Power Supply (VCC = 0V) –8.0 to 0 VDC VI Input Voltage (VCC = 0V) 0 to –6.0 VDC IOUT Output Current 50 100 mA –40 to +85 °C –Continuous –Surge TA Operating Temperature Range NOTES: 1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet. 2. Parametric values specified at: 3 volt Power Supply Range 100EL15L Series –3.0V to –3.8V. DC ELECTRICAL CHARACTERISTICS VEE = 3.3V ±10%; VCC = GND(1) TA = –40°C Symbol TA = 0°C TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Typ. Max. Min. Max. Unit Output HIGH Voltage(2) –1085 –880 –1025 –880 –1025 –955 –880 –1025 –880 mV Output LOW Voltage(2) –1830 –1555 –1810 –1620 –1810 –1705 –1620 –1810 –1620 mV Output HIGH Voltage(3) –1095 — –1035 — –1035 — — –1035 — mV VOLA Output LOW Voltage(3) — –1555 — –1610 — — –1610 — –1610 mV VIH Input HIGH Voltage –1165 –880 –1165 –880 –1165 — –880 –1165 –880 mV VIL Input LOW Voltage –1810 –1475 –1810 –1475 –1810 — –1475 –1810 –1475 mV IIH Input High Current — 150 — 150 — — 150 — 150 µA 0.5 –300 — — 0.5 –300 — — 0.5 –300 — — 0.5 –300 — — µA — — 35 — 35 — 25 35 — 38 mA –1.38 –1.26 –1.38 –1.26 –1.38 — –1.26 –1.38 –1.26 V VOH VOL VOHA IIL Parameter Input LOW Current(4) CLK IEE Power Supply Current VBB Output Reference Voltage NOTES: 1. This table replaces the three traditionally seen in ECL 100K data books. Outputs are terminated through a 50Ω resistor to –2.0V. 2. VIN = VIH(Max) or VIL(Min). 3. VIN = VIH(Min) or VIL(Max). 4. VIN = VIL(Max). 2 ClockWorks™ SY100EL15L Micrel AC ELECTRICAL CHARACTERISTICS VEE = 3.3V ±10%; VCC = GND(1) TA = –40°C Symbol TA = 0°C TA = +25°C TA = +85°C Parameter Min. Max. Min. Max. Min. Typ. Max. Min. Max. tPLH tPHL Propagation Delay CLK to Q (Diff) CLK to Q (SE) SCLK to Q 460 410 410 660 710 710 470 420 420 670 720 720 470 420 420 — — — 670 720 720 500 450 470 700 750 750 tskew Part-to-Part Skew(1) Within-Device Skew — — 200 50 — — 200 50 — — — — 200 50 — — 200 50 ps tS Setup Time EN 150 — 150 — 150 — — 150 — ps tH Hold Time EN 400 — 400 — 400 — — 400 — ps VPP Minimum Input Swing CLK 250 — 250 — 250 — — 250 — mV –2.0 –1.8 –0.4 –0.4 –2.1 –1.9 –0.4 –0.4 –2.1 –1.9 — — –0.4 –0.4 –2.1 –1.9 –0.4 –0.4 375 625 325 575 325 — 575 325 575 VCMR tr tf ps Range(2) Common Mode VPP < 500mV VPP ≥ 500mV Output Rise/Fall TimesQ (20% – 80%) Unit mV ps NOTES: 1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 2. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signals are within the VCMR range and the input swing is greater than VPP(Min.) and <1V. The lower end of the VCMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR(Min) will be fixed at 3.3V – |VCMR(Min)|. PRODUCT ORDERING CODE Ordering Code 3 Package Type Operating Range SY100EL15LZC Z16-2 Commercial SY100EL15LZCTR Z16-2 Commercial ClockWorks™ SY100EL15L Micrel 16 LEAD PLASTIC SOIC .150" WIDE (Z16-2) MICREL-SYNERGY TEL + 1 (408) 980-9191 FAX 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 914-7878 WEB http://www.synergysemi.com http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 1999 Micrel Incorporated 4