MITSUBISHI MH64S72QJA-8

MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change w ithout notice.
DESCRIPTION
The MH64S72QJA is 67108864 - word x 72-bit
Sy nchronous DRAM stacked structural module. This
consist of thirty -six industry s t andard 32M x 4
Sy nchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual inline package prov ides any application where high
densities and large of quantities memory are required.
This is a socket-ty pe memory m odule ,suitable f or
easy interchange or addition of module.
FEATURES
Type name
Max.
Frequency
CLK
Access Time
[latch mode]
(CL = 4)
CLK
Access Time
[buffer mode]
(CL = 3)
MH64S72QJA-7
100MHz
6ns
6ns
MH64S72QJA-8
100MHz
6ns
6ns
Utilizes industry standard 32M X 4 Synchronous DRAMs in
TSOP package , industry standard Resister in TSSOP package ,
and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V power supply
LVTTL Interface
4096 refresh cycles every 64ms
APPLICATION
Main memory unit for computers, Microcomputer memory.
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
85pin
1pin
94pin
10pin
95pin
11pin
124pin
40pin
125pin
41pin
168pin
84pin
16/Jun./1999
1
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
1
VSS
43
VSS
85
2
DQ0
44
NC
86
3
DQ1
45
/S2
87
4
DQ2
46
DQMB2
5
DQ3
47
DQMB3
6
VDD
48
PIN NAME
PIN NO.
PIN NAME
VSS
127
VSS
DQ32
128
CKE0
DQ33
129
/S3
88
DQ34
130
DQMB6
89
DQ35
131
DQMB7
NC
90
VDD
132
NC
7
DQ4
49
VDD
91
DQ36
133
VDD
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
DQ39
136
CB6
DQ40
137
CB7
10
DQ7
52
CB2
94
11
DQ8
53
CB3
95
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
REGE
22
CB1
64
VSS
106
CB5
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
VDD
/WE
68
VSS
110
VDD
152
VSS
27
69
DQ24
111
/CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
/S0
72
DQ27
114
/S1
156
DQ59
31
NC
73
VDD
115
/RAS
157
VDD
VSS
158
DQ60
A1
159
DQ61
32
VSS
74
DQ28
116
33
A0
75
DQ29
117
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
38
A10
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VDD
82
SDA
124
VDD
166
SA1
41
42
VDD
CK0
83
84
SCL
VDD
125
126
CK1
167
168
SA2
VDD
NC
NC = No Connection
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
2
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Add
CKE0
/S0-3
DQM0-7
/W
/RAS
/CAS
RCKE0
R/S0-3
RDQM0-7
REGE
Vdd
DQ0
DQ1
DQ32
DQ33
DQ2
DQ3
DQ4
DQ5
D0
D18
DQ34
DQ35
DQ36
DQ37
D9
D27
DQ6
DQ7
D1
D19
DQ38
DQ39
D10
D28
D11
D29
D12
D30
D13
D31
D14
D32
DQ8
DQ9
DQ10
D2
DQ40
DQ41
DQ42
D20
DQ11
DQ12
DQ13
DQ14
DQ15
DQ43
DQ44
D3
DQ45
DQ46
DQ47
D21
DQ16
DQ17
DQ18
DQ19
DQ48
D4
DQ49
DQ50
DQ51
D22
DQ20
DQ21
DQ22
DQ23
DQ52
DQ53
D5
D23
DQ54
DQ55
DQ24
DQ25
DQ56
DQ57
DQ26
DQ27
DQ28
DQ29
D6
D24
DQ58
DQ59
DQ60
DQ61
D15
D33
DQ30
DQ31
D7
D25
DQ62
DQ63
D16
D34
D17
D35
CB0
CB1
CB2
CB4
D8
CB5
CB6
D26
CB3
CB7
From PLL
CK0
CK1 - CK3
RCKE0
R/S0
R/S1
R/S2
R/S3
PLL
RDQM
Terminated
RDQM
D0-35
RDQM
D9-12,D17-21,D26
D0-3,D8,D27-30,D35 RDQM
D13-16,D22-25
RDQM
D4-7,D31-34
RDQM
RDQM
RDQM
MIT-DS-0332-0.0
SERIAL PD
0
1
2
3
4
5
6
7
SCL
D0-1,D18-19
WP
D2-3,D8,D20-21,D26
D4-5,D22-23
D6-7,D24-25
D9-10,D27-28
D11-12,D17,D29-30,D35 VDD
D13-14,D31-32
VSS
D15-16,D33-34
MITSUBISHI
ELECTRIC
SDA
A0
A1
A2
SA0 SA1 SA2
D0 to D35
D0 to D35
16/Jun./1999
3
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM
04
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A10
0B
5
# Module Banks on this assembly
2BANK
02
6
Data Width of this assembly...
x72
48
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
01
10ns
A0
6ns
60
ECC
02
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
SDRAM Access from Clock
tAC for CL=3
11
DIMM Configuration type (Non-parity,Parity,ECC)
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x4
04
14
Error Checking SDRAM data width
x4
04
Minimum Clock Delay,Back to Back Random Column Addresses
1
01
16
Burst Lengths Supported
1/2/4/8/Full page
8F
17
# Banks on Each SDRAM device
4bank
04
18
CAS# Latency
2/3
06
19
CS# Latency
0
01
20
Write Latency
0
01
21
SDRAM Module Attributes
buffered,registered
1F
22
SDRAM Device Attributes:General
Precharge All,Auto precharge
Write1/Read Burst
0E
23
SDRAM Cycle time(2nd highest CAS latency)
-7
10ns
A0
-8
13ns
D0
-7
6ns
60
-8
7ns
70
15
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
26
SDRAM Access form Clock(3rd highest CAS latency)
N/A
00
27
Precharge to Active Minimum
20ns
14
28
Row Active to Row Active Min.
20ns
14
29
RAS to CAS Delay Min
20ns
14
30
Active to Precharge Min
50ns
32
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
4
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
31
Density of each bank on module
256MByte
40
32
Command and Address signal input setup time
2ns
20
33
Command and Address signal input hold time
1ns
10
34
Data signal input setup time
2ns
20
35
Data signal input hold time
1ns
10
36-61
Superset Information (may be used in future)
option
00
62
SPD Revision
rev 1.2A
12
63
Checksum for bytes 0-62
Check sum for -7
61
Check sum for -8
A1
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufactures Part Number
91-92
93-94
MH64S72QJA-7
4D483634533732514A412D37202020202020
MH64S72QJA-8
4D483634533732514A412D38202020202020
Revision Code
PCB revision
rrrr
Manufacturing date
year/week code
yyww
serial number
ssssssss
95-98
Assembly Serial Number
99-125
Manufacture Specific Data
option
00
126
Intetl specification frequency
100MHz
64
127
Intel specification CAS# Latency support
128+
Unused storage locations
MIT-DS-0332-0.0
CL=2/3,AP,CK0
open
MITSUBISHI
ELECTRIC
8F
00
16/Jun./1999
5
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0 - 3
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/W
Input
Combination of /RAS,/CAS,/W defines basic commands.
CK0
A0-11
Input
BA0-1
Input
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
MIT-DS-0332-0.0
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-10.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
the bank to which a command is applied.BA must be set
with ACT,PRE,READ,WRITE commands
Input/Output Data In and Data out are referenced to the rising edge
of CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
Output
Register enable:When REGE is low,All control signals and
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
MITSUBISHI
ELECTRIC
16/Jun./1999
6
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH64S72QJA provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Ref resh Option @ref resh command
A10
Precharge Option @precharge or read/write command
def ine basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.Firs t output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
7
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
Deselect
DESEL
No Operation
CKE CKE
n-1
n
X
NOP
H
H
ACT
Single Bank Precharge
Precharge All Bank
/S
/RAS /CAS /WE
X
X
H
L
X
H
X
H
H
X
L
L
PRE
PREA
H
H
X
X
L
L
Column Address Entry
& Write
WRITE
H
X
Column Address Entry
& Write with AutoPrecharge
WRITEA
H
Column Address Entry
& Read
READ
Column Address Entry
& Read with Auto
Precharge
BA0,1 A11
A10
A0-9
X
H
X
X
X
X
X
X
X
H
H
V
V
V
V
L
L
H
H
L
L
V
X
X
X
L
H
X
X
L
H
L
L
V
V
L
V
X
L
H
L
L
V
V
H
V
H
X
L
H
L
H
V
V
L
V
READA
H
X
L
H
L
H
V
V
H
V
Auto-Refresh
Self-Refresh Entry
REFA
REFS
L
L
X
H
L
L
L
H
H
X
H
L
X
X
X
X
X
X
L
X
X
REFSX
H
L
H
L
L
Self-Refresh Exit
H
H
L
L
H
X
X
X
X
V*1
Row Adress Entry &
Bank Activate
Mode Register Set
MRS
H
X
H
L
L
X
H
L
X
X
L
X
X
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
8
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State
/S
IDLE
H
L
L
L
L
ROW ACTIVE
H
H
H
L
L
L
L
H
H
L
H
Address
/WE
X
X
H
X
BA
L
X
H
BA,CA,A10
BA,RA
L
L
H
L
L
L
L
L
H
X
L
X
H
H
X
H
L
H
H
L
BA
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
L
H
H
L
L
L
READ
/RAS /CAS
X
X
H
NOP
PRE/PREA
X
L
L
L
H
X
X
X
Mode-Add
X
L
H
H
H
L
H
H
L
L
H
L
H
NOP
ILLEGAL*2
REFA
NOP*4
Auto-Refresh*5
MRS
Mode Register Set*5
DESEL
NOP
NOP
TBST
NOP
READ/READA
BA,RA
L
NOP
TBST
READ/WRITE ILLEGAL*2
Bank Active,Latch RA
ACT
Op-Code,
Mode-Add
X
L
H
DESEL
BA,A10
X
H
L
Action
Command
Op-Code,
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
Begin Write,Latch CA,
WRITEA
Determine Auto-Precharge
Bank Active/ILLEGAL*2
ACT
PRE/PREA
BA,A10
X
NOP
REFA
Precharge/Precharge All
ILLEGAL
MRS
ILLEGAL
DESEL
NOP(Continue Burst to END)
X
NOP
NOP(Continue Burst to END)
BA
TBST
Terminate Burst
BA,CA,A10
Terminate Burst,Latch CA,
READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L
H
L
L
L
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3
ACT
BA,RA
Bank Active/ILLEGAL*2
BA,A10
X
Op-Code,
PRE/PREA
REFA
MRS
Terminate Burst,Precharge
ILLEGAL
ILLEGAL
Mode-Add
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
9
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
WRITE
H
L
/RAS /CAS
X
X
/WE
X
Address
H
H
H
X
X
H
H
L
BA
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
Command
Action
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
TBST
Terminate Burst
Terminate Burst,Latch CA,
READ/READA Begin Read,Determine AutoPrecharge*3
WRITE/
WRITEA
L
L
L
Begin Write,Determine AutoPrecharge*3
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
H
L
H
H
L
L
L
H
L
L
L
L
READ with
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
AUTO
L
H
H
H
X
NOP
NOP(Continue Burst to END)
PRECHARGE
L
L
H
L
H
BA
BA,CA,A10
TBST
H
H
L
L
H
L
L
BA,CA,A10
L
L
L
H
H
H
L
L
L
L
WRITE with
L
BA,RA
BA,A10
ACT
Terminate Burst,Latch CA,
PRE/PREA
X
Op-Code,
Mode-Add
BA,RA
BA,A10
REFA
ILLEGAL
MRS
ILLEGAL
ILLEGAL
READ/READA ILLEGAL
WRITE/
WRITEA
ACT
Bank Active/ILLEGAL*2
ILLEGAL*2
L
L
H
L
L
L
Op-Code,
Mode-Add
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
AUTO
L
H
H
H
X
NOP
NOP(Continue Burst to END)
PRECHARGE
L
L
H
L
H
BA
BA,CA,A10
TBST
H
H
L
L
H
L
L
BA,CA,A10
L
L
L
H
H
H
BA,RA
BA,A10
MIT-DS-0332-0.0
L
L
L
L
L
L
L
H
L
L
X
X
PRE/PREA
REFA
ILLEGAL
MRS
ILLEGAL
ILLEGAL
ILLEGAL
READ/READA ILLEGAL
WRITE/
WRITEA
ACT
PRE/PREA
REFA
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
MRS
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
16/Jun./1999
10
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
X
X
PRE -
H
CHARGING
L
H
L
/WE
Command
Address
Action
X
X
DESEL
NOP(Idle after tRP)
H
H
X
NOP
NOP(Idle after tRP)
H
L
L
X
BA
L
H
H
L
L
H
H
BA,RA
ACT
L
L
L
L
BA,A10
X
PRE/PREA
L
H
L
L
L
L
L
ROW
H
X
X
X
X
DESEL
NOP(Row Active after tRCD
ACTIVATING
L
H
H
H
X
NOP
NOP(Row Active after tRCD
L
L
H
L
X
BA
BA,CA,A10
TBST
H
H
L
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
H
PRE/PREA
REFA
ILLEGAL*2
L
L
H
BA,A10
L
L
L
L
L
L
L
H
BA,CA,A10
Op-Code,
Mode-Add
Op-Code,
REFA
NOP*4(Idle after tRP)
ILLEGAL
MRS
ILLEGAL
MRS
Mode-Add
H
X
X
X
X
COVERING
L
L
H
H
H
H
H
L
X
BA
L
H
L
X
BA,CA,A10
L
H
H
H
L
BA,RA
L
L
L
L
L
L
H
X
L
L
L
L
ILLEGAL*2
ILLEGAL*2
READ/WRITE ILLEGAL*2
X
WRITE RE-
MIT-DS-0332-0.0
ILLEGAL*2
TBST
READ/WRITE ILLEGAL*2
DESEL
NOP
TBST
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL*2
READ/WRITE ILLEGAL*2
BA,A10
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
ACT
PRE/PREA
ILLEGAL*2
ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
16/Jun./1999
11
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
/WE
RE-
H
X
X
X
X
DESEL
NOP(Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP(Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP(Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP(Idle after tRSC)
SETTING
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
Address
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
Action
READ/WRITE ILLEGAL
READ/WRITE ILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address , CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle s tate.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
12
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE for CKE
Current State
CKE
n-1
CKE
n
/S
SELF -
H
X
X
X
REFRESH*1
L
H
H
L
H
L
/RAS /CAS
/WE
Add
Action
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh(Idle after tRC)
L
H
H
H
X
Exit Self-Refresh(Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
ALL BANKS
H
H
X
X
X
X
X
Refer to Function Truth Table
IDLE*2
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CK0 Suspend at Next Cycle*3
listed above
L
H
X
X
X
X
X
Exit CK0 Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
13
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before s tarting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode regis ter.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
regis ter(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
BA0 BA1 A11 A10 A9
A8
A7 A6
A5
A4 A3
A2
A1 A0
/RAS
/CAS
0
0
0
0
0
WM
0
LTMODE
BT
BL
/WE
V
BA0,1 A11-0
CL
000
LATENCY
MODE
WRITE
MODE
/CAS LATENCY
R
001
010
R
2
011
100
3
R
101
110
R
R
111
R
0
1
MIT-DS-0332-0.0
BURST
SINGLE BIT
BURST
LENGTH
BL
BT= 0
000
001
1
BT= 1
1
2
4
2
4
8
R
8
R
R
R
R
R
FP
R
010
011
100
101
110
111
BURST
TYPE
0
1
SEQUENTIAL
INTERLEAVED
R:Reserved for Future Us e
FP: Full Page
MITSUBISHI
ELECTRIC
16/Jun./1999
14
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK
Command
Read
Write
Y
Y
Address
Q0
DQ
CL= 3
BL= 4
/CAS Latency
Q1
Q2
Q3
D0
D1
D2
D3
Burst Length
Burst Length
Burst Type
Initial Address BL
Column Addressing
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Interleaved
Sequential
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
15
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
ABSOLUTE M AXIMUM RATINGS
Symbol
Parameter
Condition
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ 4.6
V
VO
Output Voltage
with respect to Vss
-0.5 ~ 4.6
V
IO
Output Current
50
mA
Pd
Power Dissipation
40
W
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-45 ~ 100
°C
Ta=25°C
RECOM M ENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VIH
High-Level Input Voltage all inputs
2.0
Vdd+0.3
VIL
Low-Level Input Voltage all inputs
-0.3
0.8
V
V
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Parameter
Symbol
Test Condition
CI(A) Input Capacitance, address pin
VI = Vs s
CI(C) Input Capacitance, control pin
f=1MHz
Input Capacitance, CK0 pin
CI(K)
CI/O
Input Capacitance, I/O pin
MIT-DS-0332-0.0
Vi=25mVrm s
MITSUBISHI
ELECTRIC
Limits(max.)
Unit
20
20
pF
pF
14
pF
22
pF
16/Jun./1999
16
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Parameter
Symbol
Icc1
Icc2N
Icc2NS
Icc2P
Icc2PS
Icc3N
Icc3NS
Icc3P
Icc3PS
Icc4
Icc5
Icc6
Test Condition
operating current, single bank tRC=min.tCLK=min, BL=1, CL=3
precharge standby current in
Non Power down mode
precharge standby current in
Power down mode
active standby current in Non
Power down mode
active standby current in
Power down mode
burst current
auto-refresh current
self-refresh current
(Note1)
tCLK=min,CKE=H,/CS > Vcc-0.2V,VIH > Vcc-0.2V,VIL < 0.2V
(Note1)
CLK=L & CKE=H,/CS > Vcc-0.2V,VIH > Vcc-0.2V,VIL < 0.2V
all input signals are fixed.
(Note1)
tCLK=min,CKE=L,/CS > Vcc-0.2V
(Note1)
CLK=L,CKE=L,/CS > Vcc-0.2V
CKE=H,tCLK=min.
(Note1)
(Note1)
CKE=H,CLK=L
(Note1)
CKE=L,tCLK=min.
(Note1)
CKE=L,CLK=L
(Note1)
tCLK=min, BL=4, CL=3, all banks active(discrete)
(Note1)
tRC=min, tCLK=min
(Note1)
CKE <0.2V
(Note1)
Limits(max)
Unit
-7
-8
3059 3059 mA
1349 1349 mA
333 333 mA
701 701 mA
82
82 mA
1709 1709 mA
945 945 mA
809 809 mA
225 225 mA
3059 3059 mA
4229 4229 mA
82
82 mA
Note)
1.Icc(max) is specif ied at the output open condition.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Test Condition
Parameter
VOH(DC) High-Level Output Voltage(DC)
VOL(DC) Low-Level Output Voltage(DC)
IOZ
Off-stare Output Current
Ii
Input Current
MIT-DS-0332-0.0
IOH=-2mA
IOL=2mA
Q floating VO=0 ~ Vdd
VIH=0 ~ Vdd+0.3V
MITSUBISHI
ELECTRIC
Limits
Unit
Min. Max.
2.4
V
0.4 V
-10
-20
10 uA
20 uA
16/Jun./1999
17
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIM ING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
LATCH MODE
Limits
-7
Min. Max.
Symbol Parameter
tCLK
CK cycle tim e
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tCCD
tRSC
tSRX
tREF
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active tim e
Row Precharge time
Write Recovery tim e
Act to Act Deley time
Col to Col Delay time
Mode Register Set Cycle tim e
Self Refresh Exit tim e
Refresh Interval tim e
CL=3
CL=4
10
10
3
3
1
13
10
3
10
2
1
70
20
50
20
20
20
10
20
10
70
20
50
100k
1.4V
Signal
1.4V
10
100k
20
20
20
10
20
10
64
MITSUBISHI
ELECTRIC
3
1
2
1
CK
MIT-DS-0332-0.0
-8
Min. Max.
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
16/Jun./1999
18
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Limits
-7
-8
Min. Max.
Min. Max.
Symbol Parameter
tCLK
CK cycle tim e
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tCCD
tRSC
tSRX
tREF
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active tim e
Row Precharge time
Write Recovery tim e
Act to Act Deley time
Col to Col Delay time
Mode Register Set Cycle tim e
Self Refresh Exit tim e
Refresh Interval tim e
CL=2
CL=3
10
13
10
10
3
3
1
7
3
3
1
7
10
0
70
20
50
20
20
20
10
20
10
100k
10
0
70
20
50
100k
20
20
20
10
20
10
64
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
LATCH MODE
Limits
-8
-7
Min. Max. Min. Max.
Symbol Parameter
tAC
tOH
tOLZ
tOHZ
Access time from CK
CL=3
CL=4
Output Hold tim e
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
6
6
7
6
Unit Note
ns
ns
3
3
ns
0
0
ns
3
6
3
6
*1
ns
NOTE)
1.If clock rising time is longer than 1ns,(tr /2-0.5ns) should be added to the parameter.
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
19
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Limits
-7
Min. Max.
Symbol Parameter
tAC
tOH
tOLZ
tOHZ
CL=2
CL=3
Access time from CK
Output Hold tim e
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
-8
Min.
6
6
Unit Note
Max.
7
6
ns
ns
3
3
ns
0
0
ns
3
6
3
6
*1
ns
NOTE)
1.If clock rising time is longer than 1ns,(tr /2-0.5ns) should be added to the parameter.
Output Load Condition
VTT =1.4V
CK
1.4V
50Ω
VREF =1.4V
DQ
1.4V
VOUT
50pF
Output Timing
Measurement
Ref erence Point
1.4V
CK
DQ
1.4V
tAC
MIT-DS-0332-0.0
tOH
tOHZ
MITSUBISHI
ELECTRIC
16/Jun./1999
20
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (single bank)
1
0
2
3
5
4
7
6
BL=4,Buffer mode(REGE="L")
9
8
11
10
12
13
15
14
17
16
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
Y
A0-8
X
A10
X
X
A9,11
X
X
BA0,1
0
X
0
0
0
Y
0
REGE
D0
DQ
ACT#0
D0
WRITE#0
D0
D0
D0
PRE#0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
21
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (dual bank)
1
0
3
2
5
4
7
6
BL=4,Buffer mode(REGE="L")
9
8
11
10
13
12
15
14
17
16
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-8
X
X
A10
X
A9,11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
D1
D1
0
1
2
Y
0
REGE
D0
DQ
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D1
D1
PRE#0
WRITE#1
D0
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
22
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (single bank)
1
0
2
3
5
4
7
6
BL=4,Lacth mode(REGE="H")
9
8
11
10
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
A0-8
X
Y
X
A10
X
X
A9,11
X
X
BA0,1
0
0
0
0
Y
0
REGE
DQ
D0
ACT#0
WRITE#0
D0
D0
D0
PRE#0
D0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
23
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (dual bank)
1
0
3
2
5
4
7
6
BL=4,Latch mode(REGE="H")
9
8
11
10
13
12
15
14
17
16
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-8
X
X
A10
X
A9,11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
0
D0
D1
1
2
Y
0
REGE
D0
DQ
ACT#0
WRITE#0
ACT#1
D0
D0
D1
D1
PRE#0
WRITE#1
D1
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
24
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BL=4,CL=3,Buffer mode(REGE="L")
READ CYCLE (single bank)
1
0
2
3
5
4
7
6
9
8
11
10
12
13
14
15
17
16
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-8
X
Y
X
A10
X
X
A9,11
X
X
BA0,1
0
0
0
0
Y
0
REGE
CL=3
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Q0
ACT#0
Q0
READ#0
READ to PRE ≥ BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
25
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (dual bank)
1
0
3
2
4
5
BL=4,CL=3,Buffer mode(REGE="L")
7
6
9
8
11
10
13
12
15
14
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-8
X
X
A10
X
A9,11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
Q1
Q1
Q1
Y
0
REGE
CL=3
DQ
CL=3
Q0
ACT#0
READ#0
ACT#1
Q0
Q0
Q0
PRE#0
READ#1
Q1
Q0
READ#0
ACT#0
PRE#1 ACT#2
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
26
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (single bank)
1
0
2
3
5
4
7
6
BL=4, CL=3,Latch mode(REGE="H")
9
8
11
10
12
13
14
15
17
16
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =3
A0-8
X
Y
X
A10
X
X
A9,11
X
X
BA0,1
0
0
0
0
Y
0
REGE
CL=3
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Q0
ACT#0
Q0
READ#0
READ to PRE ≥ BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
27
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (dual bank)
1
0
3
2
4
5
BL=4,CL=3,Latch mode(REGE="H")
7
6
9
8
11
10
13
12
15
14
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =3
A0-8
X
X
A10
X
A9,11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
Q1
Q1
Q1
Y
0
REGE
CL=3
DQ
CL=3
Q0
ACT#0
READ#0
ACT#1
Q0
Q0
Q0
PRE#0
READ#1
Q1
Q0
READ#0
ACT#0
PRE#1 ACT#2
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
28
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
0
1
2
4
3
6
5
8
7
BL=4,Buffer mode(REGE="L")
10
9
11
12
14
13
16
15
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
/CAS
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-8
X
X
Y
Y
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
1
0
X
1
Y
X
Y
0
0
1
1
D1
D0
D0
REGE
DQ
D0
ACT#0
ACT#1
D0
D0
D0
WRITE#0 with
AutoPrecharge
D1
D1
D1
ACT#0
WRITE#1 with
AutoPrecharge
D0
WRITE#0
ACT#1
D0
D1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
29
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
0
1
2
4
3
6
5
8
7
BL=4,Latch mode(REGE="H")
10
9
12
11
14
13
16
15
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
/CAS
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-8
X
X
Y
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
1
Y
0
X
1
Y
0
0
X
Y
1
1
REGE
D0
DQ
ACT#0
ACT#1
D0
D0
WRITE#0 with
AutoPrecharge
D0
D1
D1
D1
D1
ACT#0
WRITE#1 with
AutoPrecharge
D0
D0
WRITE#0
ACT#1
D0
D0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
30
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
0
1
2
4
3
5
6
8
7
BL=4,Buffer mode(REGE="L")
10
9
12
11
14
13
16
15
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
/CAS
tRCD
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =2
A0-8
X
X
Y
Y
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
1
0
X
1
Y
0
0
X
Y
1
1
REGE
CL=3
CL=3
Q0
DQ
ACT#0
ACT#1
READ#0 with
Auto-Precharge
Q0
Q0
CL=3
Q0
Q1
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
31
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
0
1
2
4
3
5
6
8
7
BL=4,Latch mode(REGE="H")
10
9
12
11
14
13
16
15
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =3
A0-8
X
X
Y
Y
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
1
0
X
1
Y
0
0
X
Y
1
1
REGE
CL=3
CL=3
Q0
DQ
ACT#0
ACT#1
READ#0 with
Auto-Precharge
Q0
Q0
CL=3
Q0
Q1
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
32
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
1
0
3
2
5
4
7
6
9
8
BL=4,Buffer mode(REGE="L")
11
10
12
13
15
14
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
D0
DQ
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
33
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
1
0
3
2
5
4
7
6
9
8
BL=4,Latch mode(REGE="H")
11
10
12
13
15
14
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
D0
DQ
ACT#0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
34
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
1
0
3
2
4
5
7
6
9
8
BL=4,Buffer mode(REGE="L")
11
10
13
12
14
15
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
CL=3
DQ
Q0
ACT#0
READ#0
ACT#1
CL=3
CL=3
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
35
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
1
0
3
2
4
5
7
6
9
8
BL=4,Latch mode(REGE="H")
11
10
13
12
14
15
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
CL=3
CL=3
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
36
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
0
1
2
4
3
6
5
8
7
BL=4,Buffer mode(REGE="L")
10
9
12
11
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
0
0
0
1
0
REGE
CL=3
D0
DQ
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0
READ#0
WRITE#0 WRITE#0 WRITE#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
37
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
0
1
2
4
3
6
5
8
7
BL=4,Latch mode(REGE="H")
10
9
12
11
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
0
0
0
1
0
REGE
CL=3
D0
DQ
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0
READ#0
WRITE#0 WRITE#0 WRITE#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
38
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
1
0
3
2
4
5
7
6
BL=4,Buffer mode(REGE="L")
9
8
11
10
12
13
14
15
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
REGE
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
DQ
ACT#0
READ#0
WRITE#0
READ#0 READ#0 READ#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
39
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
1
0
3
2
4
5
7
6
BL=4,Latch mode(REGE="H")
9
8
11
10
12
13
15
14
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
REGE
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
DQ
ACT#0
READ#0
WRITE#0
READ#0 READ#0 READ#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
40
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
0
1
2
4
3
6
5
8
7
BL=4,Buffer mode(REGE="L")
10
9
11
12
13
14
16
15
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
X
Y
A10
X
X
X
A9,11
X
X
X
BA0,1
0
1
0
D0
REGE
Y
D0
D0
D0
X
1
0
D1
D1
1
1
Y
1
D1
D1
D1
DQ
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
41
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
0
1
2
4
3
6
5
8
7
BL=4,Latch mode(REGE="H")
10
9
11
12
13
14
16
15
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
Y
A0-8
X
X
Y
A10
X
X
X
A9,11
X
X
X
BA0,1
0
1
0
D0
REGE
D0
D0
X
1
0
1
D0
D1
D1
1
Y
1
D1
D1
D1
DQ
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
42
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
0
2
1
4
3
5
6
8
7
BL=4,Buffer mode(REGE="L")
10
9
11
12
13
14
16
15
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
X
X
A10
X
X
X
A9,11
X
X
X
BA0,1
0
1
A0-8
Y
Y
0
Q0
REGE
X
1
0
1
Q0
Q0
Q0
1
Q1
Y
1
Q1
DQ
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
43
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
0
2
1
4
3
5
6
8
7
BL=4,Latch mode(REGE="H")
10
9
11
12
13
14
16
15
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-8
X
X
Y
Y
A10
X
X
X
A9,11
X
X
X
BA0,1
0
1
0
Q0
REGE
X
1
0
1
Q0
Q0
Q0
1
Q1
Y
1
Q1
DQ
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
44
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
17
16
CLK
/CS
tRSC
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
M
A0-8
X
A10
X
A9,11
X
0
BA0,1
0
Y
0
D0
REGE
D0
D0
D0
DQ
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ACT#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
45
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
11
10
13
12
14
15
16
17
CLK
/CS
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
0
D0
REGE
D0
D0
D0
DQ
Auto-Refresh
ACT#0
Before Auto-Refresh,
all banks must be idle state.
After tRC from Auto-Refresh,
all banks are idle state.
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
46
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
CLK can be stopped
tRC
/CS
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
REGE
DQ
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
47
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask @BL=4
0
2
1
4
3
6
5
BL=4,Buffer mode(REGE="L")
8
7
9
10
12
11
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
D0
REGE
D0
D0
D0
masked
D0
D0
D0
DQ
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
48
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask @BL=4
0
2
1
4
3
6
5
BL=4,Latch mode(REGE="H")
8
7
10
9
12
11
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
D0
REGE
D0
D0
D0
masked
D0
D0
D0
DQ
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
49
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask @BL=4 CL=3
0
2
1
4
3
5
6
BL=4,Buffer mode(REGE="L")
8
7
10
9
12
11
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=2
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
Q0
REGE
Q0
Q0
Q0
masked
Q0
Q0
Q0
DQ
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
50
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask @BL=4 CL=3
0
2
1
4
3
5
6
BL=4,Latch mode(REGE="H")
8
7
10
9
12
11
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=3
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
Q0
REGE
Q0
Q0
Q0
masked
Q0
Q0
Q0
DQ
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
51
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Power Down
0
1
2
3
4
5
6
8
7
10
9
11
12
13
14
15
16
17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
REGE
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
52
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend @BL=4 CL=3
1
0
2
3
5
4
BL=4,Buffer mode(REGE="L")
7
6
9
8
11
10
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
0
0
D0
REGE
D0
D0
D0
Q0
Q0
Q0
Q0
DQ
ACT#0
READ#0
WRITE#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
53
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend @BL=4 CL=3
1
0
2
3
5
4
BL=4,Latch mode(REGE="H")
7
6
9
8
11
10
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
0
0
D0
REGE
D0
D0
D0
Q0
Q0
Q0
Q0
DQ
ACT#0
READ#0
WRITE#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
54
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35
3
8.89
6.35
11.43
1.27
6.35
36.83
24.495
3
54.61
42.18
127.35
44.45
6.5
Max
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
55
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or ci rcuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
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reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
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Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
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5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
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the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
56