SAMSUNG KM6164002

PRELIMINARY
CMOS SRAM
KM6164002, KM6164002E, KM6164002I
PACKAGE DIMENSIONS
44-SOJ-400
Units : Inches (millimeters)
#23
9.40±0.25
0.370±0.010
10.16
0.400
#44
11.18±0.12
0.440±0.005
0.20 +0.10
-0.05
0.008 +0.004
-0.002
#22
#1
28.98 MAX
1.141
25.58±0.12
1.125±0.005
(
1.19
)
0.047
0.69 MIN
0.027
3.76
0.148MAX
0.10
MAX
0.004
+0.10
( 0.95 )
0.0375
0.43 -0.05
0.017 +0.004
-0.002
+0.10
1.27
0.050
0.71 -0.05
0.028 +0.004
-0.002
-9-
1.27
( 0.050 )
Rev 2.0
June -1997
PRELIMINARY
CMOS SRAM
KM6164002, KM6164002E, KM6164002I
TIMING WAVE FORM OF WRITE CYCLE(4)(UB, LB Controlled)
tWC
ADD
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDW
High-Z
Data In
tDH
Data Valid
tBLZ
tWHZ(6)
High-Z
Data Out
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE going low ; A write ends at
the earliest transition CS going high or WE going high. t WP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS, or WE going high.
6. If OE. CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not
be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
LB
UB
H
X
X*
X
X
L
H
H
X
X
L
X
X
H
H
L
H
L
H
L
H
L
L
L
X
I/O Pin
Mode
Supply Current
I/O1~I/O8
I/O9~I/O16
Not Select
High-Z
High-Z
ISB, ISB1
Output Disable
High-Z
High-Z
ICC
DOUT
High-Z
Read
High-Z
DOUT
L
L
DOUT
DOUT
L
H
DIN
High-Z
H
L
High-Z
DIN
L
L
DIN
DIN
Write
ICC
ICC
* NOTE : X means Don't Care.
-8-
Rev 2.0
June -1997
PRELIMINARY
CMOS SRAM
KM6164002, KM6164002E, KM6164002I
TIMING WAVE FORM OF WRITE CYCLE(2)(OE=Low Fixed)
tWC
ADD
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tWP1(2)
tAS(4)
tOH
WE
tDW
Data In
High-Z
tDH
Data Valid
tWHZ(6)
tOW
(10)
(9)
High-Z
Data Out
TIMING WAVE FORM OF WRITE CYCLE(3)(CS=Controlled)
tWC
ADD
tWR(5)
tAW
tCW(3)
CS
tBW
UB, LB
tWP(2)
tAS(4)
WE
tDW
Data In
High-Z
Data Valid
tLZ
Data Out
tDH
tWHZ(6)
High-Z
High-Z(8)
-7-
Rev 2.0
June -1997
PRELIMINARY
CMOS SRAM
KM6164002, KM6164002E, KM6164002I
TIMING WAVE FORM OF READ CYCLE(2)(WE=VIH)
tRC
ADD
tAA
tCO
tHZ(3,4,5)
tBA
tBHZ(3,4,5)
CS
UB, LB
tOHZ
tBLZ(4,5)
tOE
OE
tOLZ
tOH
tLZ(4,5)
Data Valid
Data Out
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels.
4. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ (Min.) both for a given device and from device to device.
5. Transition is measured ±200§Æ from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
TIMING WAVE FORM OF WRITE CYCLE(1)(OE=Clock)
tWC
ADD
tAW
tWR(5)
OE
tCW(3)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDW
Data In
High-Z
tDH
Data Valid
tOHZ(6)
High-Z(8)
Data Out
-6-
Rev 2.0
June -1997
PRELIMINARY
CMOS SRAM
KM6164002, KM6164002E, KM6164002I
WRITE CYCLE
Parameter
Symbol
KM6164002-20
KM6164002-25
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
20
-
25
-
§À
Chip Select to End of Write
tCW
15
-
17
-
§À
Address Set-up Time
tAS
0
-
0
-
§À
Address Valid to End of Write
tAW
15
-
17
-
§À
Write Pulse Width(OE High)
tWP
15
-
17
-
§À
Write Pulse Width(OE Low)
tWP1
20
-
25
-
§À
UB, LB Valid to End of Write
tBW
15
-
17
-
ns
Write Recovery Time
tWR
0
-
0
-
§À
Write to Output High-Z
tWHZ
0
8
0
8
§À
Data to Write Time Overlap
tDW
10
-
12
-
§À
Data Hold from Write Time
tDH
0
-
0
-
§À
End Write to Output Low-Z
tOW
3
-
4
-
§À
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE(1)(Address Controlled, CS=OE=UB=LB=VIL, WE=VIH)
tRC
ADD
tAA
tOH
Data Out
Previous Data Valid
Data Valid
-5-
Rev 2.0
June -1997
PRELIMINARY
CMOS SRAM
KM6164002, KM6164002E, KM6164002I
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3§À
Input and Output timing Reference Levels
1.5V
Output Loads
See below
NOTE: Above test conditions are also applied at extended and industrial temperature ranges .
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
+5.0V
480Ω
480Ω
DOUT
255Ω
DOUT
255Ω
30pF*
5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter
Symbol
KM6164002-20
KM6164002-25
Min
Max
Min
Max
Unit
Read Cycle Time
tRC
20
-
25
-
§À
Address Access Time
tAA
-
20
-
25
§À
Chip Select to Output
tCO
-
20
-
25
§À
Output Enable to Valid Output
tOE
-
10
-
12
§À
UB, LB Access Time
tBA
-
10
-
12
ns
Chip Enable to Low-Z Output
tLZ
5
-
5
-
§À
Output Enable to Low-Z Output
tOLZ
0
-
0
-
§À
UB, LB Enable to Low-Z Output
tBLZ
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
7
0
8
§À
Output Disable to High-Z Output
tOHZ
0
7
0
8
§À
UB, LB Disable to High-Z Output
tBHZ
0
7
0
8
ns
Output Hold from Address Change
tOH
4
-
5
-
§À
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
-4-
Rev 2.0
June -1997
PRELIMINARY
CMOS SRAM
KM6164002, KM6164002E, KM6164002I
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Rating
Unit
VIN, VOUT
-0.5 to 7.0
V
Voltage on VCC Supply Relative to VSS
VCC
-0.5 to 7.0
V
Power Dissipation
PD
1.0
W
TSTG
-65 to 150
°C
Commercial
TA
0 to 70
°C
Extended
TA
-25 to 85
°C
Industrial
TA
-40 to 85
°C
Voltage on Any Pin Relative to VSS
Storage Temperature
Operating Temperature
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and functional operation of the device at these at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input Low Voltage
VIH
2.2
-
VCC+0.5**
V
Input Low Voltage
VIL
-0.5*
-
0.8
V
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
* VIL(Min) = -2.0V a.c(Pulse Width ≤10ns) for I≤20§Ì
** VIH(Max) = V CC + 2.0V a.c (Pulse Width ≤10ns) for I≤20§Ì
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Min
Max
Unit
Input Leakage Current
Parameter
ILI
VIN = VSS to VCC
-2
2
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT = VSS to VCC
-2
2
µA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA
20ns
-
240
25ns
-
220
§Ì
ISB
Min. Cycle, CS=VIH
-
60
§Ì
ISB1
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-
10
§Ì
Output Low Voltage Level
VOL
IOL=8mA
-
0.4
V
Output High Voltage Level
VOH
IOH=-4mA
2.4
-
V
-
3.95
V
Standby Current
Symbol
Test Conditions
VOH1*
IOH1=-0.1mA
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
* VCC=5.0V±5% Temp. = 25°C
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
Test Conditions
MIN
Max
Unit
CI/O
VI/O=0V
-
8
pF
CIN
VIN=0V
-
6
pF
* NOTE : Capacitance is sampled and not 100% tested.
-3-
Rev 2.0
June -1997
PRELIMINARY
CMOS SRAM
KM6164002, KM6164002E, KM6164002I
256K x 16 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
Fast Access Time 20,25§À(Max.)
Low Power Dissipation
Standby (TTL)
: 60§Ì(Max.)
CMOS) : 10§Ì(Max.)
Operating KM6164002 - 20 : 240§Ì(Max.)
KM6164002 - 25 : 220§Ì(Max.)
Single 5.0V±10% Power Supply
TTL Compatible Inputs and Outputs
I/O Compatible with 3.3V Device
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Center Power/Ground Pin Configuration
Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16
Standard Pin Configuration
KM6164002J : 44-SOJ-400
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
The KM6164002 is a 4,194,304-bit high-speed Static Random
Access Memory organized as 262,144 words by 16 bits. The
KM6164002 uses 16 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG's advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for use
in high-density high-speed system applications. The
KM6164002 is packaged in a 400mil 44-pin plastic SOJ.
PIN CONFIGURATION (Top View)
A0
1
44 A17
A1
2
43 A16
A2
3
42 A15
A3
4
41 OE
Commercial Temp.
A4
5
40 UB
Extended Temp.
CS
6
39 LB
I/O1
7
38 I/O16
I/O2
8
37 I/O15
I/O3
9
ORDERING INFORMATION
KM6164002 -20/25
KM6164002E -20/25
KM6164002I -20/25
Industrial Temp.
I/O4 10
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
Row Select
Clk Gen.
Pre-Charge Circuit
36 I/O14
SOJ
34 Vss
Vss 12
33 Vcc
I/O5 13
32 I/O12
I/O6 14
31 I/O11
I/O7 15
30 I/O10
I/O8 16
29 I/O9
WE 17
28 N.C
A5 18
27 A14
A6 19
26 A13
A7 20
25 A12
A8 21
24 A11
A9 22
23 A10
Memory Array
1048 Rows
256x16 Columns
I/O1 ~ I/O8
Data
Cont.
I/O9 ~ I/O16
Data
Cont.
Pin Name
Gen.
CLK
WE
Write Enable
I/O Circuit &
Column Select
35 I/O13
Vcc 11
PIN FUNCTION
A0 - A17
A5 A9 A10 A11 A14 A15 A16 A17
WE
OE
-2-
Address Inputs
CS
Chip Select
OE
Output Enable
LB
Lower-byte Control(I/O1~I/O8)
UB
Upper-byte Control(I/O9~I/O16)
I/O1 ~ I/O16
UB
LB
CS
Pin Function
Data Inputs/Outputs
VCC
Power(+5.0V)
VSS
Ground
Rev 2.0
June -1997
KM6164002, KM6164002E, KM6164002I
PRELIMINARY
CMOS SRAM
Document Title
64Kx16 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial, Extended and Industrial Temperature Range.
Revision History
Rev No.
History
Draft Data
Remark
Rev. 0.0
Initial release with Preliminary.
Jun. 1th, 1991
Preliminary
Rev. 1.0
Release to final Data Sheet.
1.1. Delete Preliminary
Oct. 4th, 1993
Final
Rev. 2.0
2.1.Delete Low power product with Data Retention Mode.
2.1.1. Delete Data Retention Characteristics
2.2.Add Industrial and Extended Temperature Range parts with the
same parameters as Commercial Temperature Range parts.
2.2.1 Add KM6164002I for Industrial Temperature Range.
2.2.2.Add KM6164002E for Extended Temperature Range.
2.2.3.Add ordering information.
2.2.4. Add the condition for operating at Industrial and Extended
Temperature Range.
2.3.Add timing diagram to define tWP1 as ″(Timing Wave Form of
Write Cycle(OE=Low fixed)″
2.4.Delete 35ns part.
Jun. 17th, 1997
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
June -1997