Ordering number: EN 3584B Silicon-gate CMOS LSI LC7215, 7215F, 7215FM MW/LW PLL Frequency Synthesizers Package Dimensions Overview The LC7215, LC7215F and LC7215FM are phase-locked-loop frequency synthesizer LSIs that provide accurate reference frequencies over the MW and LW bands, making them ideally suited for AM tuners. unit : mm 3003A-DIP14 [LC7215, 7215F] Features . PLL frequency synthesizer LSIs for MW and LW bands. . Reference frequencies of 1, 5, 9 and 10 kHz. . On-chip transistor for the low-pass filter amplifier. . Single output pin (CMOS output) . Controller clock output pin. . Time-base output pin. . All devices can be used for double conversion demodulation. . The LC7215F and 7215FM have expanded input frequency ranges. LC7215 LC7215F/FM 0.5 to 13 MHz : (DIP14) 0.5 to 20 MHz : (DIP14/MFP14S) SANYO : DIP14 unit : mm 3111-MFP14S [LC7215FM] SANYO : MFP14S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN D2597HA(II)/1291JN/7200JN No.3584-1/7 LC7215, 7215F, 7215FM Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Values in parentheses are for the LC7215F and LC7215FM. Parameter Symbol Maximum supply voltage VDD max Input voltage Conditions Ratings VDD VIN1 All input pins VIN2 CE, CL, DATA Unit –0.3 to +6.5 V –0.3 to VDD +0.3 V (Note) –0.3 to +6.5 V Output current IOUT AOUT 0 to 5 Output voltage VOUT1 AOUT –0.3 to +15 V VOUT2 SYC, TB –0.3 to +6.5 V VOUT3 All output pins except VOUT1 and VOUT2 Pd max Ta % 85°C Allowable power dissipation mA –0.3 to VDD +0.3 V 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Note: Voltage that is applied to the resistors when resistors totaling at least 10 kΩ are connected to a pin in series. Allowable Operating Conditions at VSS = 0 V Values in parentheses are for the LC7215F and LC7215FM. Parameter Supply voltage High-level input voltage Low-level input voltage Output voltage Symbol VDD1 VDD2 VIH VIL VOUT1 VOUT2 fIN2 Conditions VDD VDD (Crystal OSC oscillation guaranteed) CE, CL, DATA CE, CL, DATA AOUT SYC, TB PIN: Sine wave, capacitive coupling VDD1, *S = 1 PIN: Sine wave, capacitive coupling VDD1, *S = 0 X’tal XIN, XOUT: CI % 30 Ω fIN1 Input frequency Oscillation guaranteed crystal oscillator VIN1 Input amplitude VIN2 Power supply — PIN: Square wave, capacity connection VDD1, *S = 1 PIN: Square wave, capacity connection VDD1, *S = 0 VDD, VSS: A capacitor of at least 1000 pF must be inserted. min (4.5)3.0 3.0 2.0 0 max (5.5)5.5 5.5 VDD1 0.5 13 5.5 Unit V V V V V V (2.3)2.3 (20)13 MHz 0.5 2.5 MHz 12.00 MHz 100 1000 mVrms 100 1000 mVrms 8.00 1000 typ 11.16 pF No.3584-2/7 LC7215, 7215F, 7215FM Electrical Characteristics within the allowable operating ranges Values in parentheses are for LC7215F and LC7215FM. Parameter High-level input currents Low-level input currents Symbol IIH1 IIH2 IIH3 IIH4 IIL1 IIL2 IIL3 IIL4 Conditions XIN: VI = VDD PIN: VI = VDD CE, CL, DATA: AIN: VI = VDD XIN: VI = VSS PIN: VI = VSS CE, CL, DATA: AIN: VI = VSS 0.01 VI = VSS VOH1 DOUT: IO = 1 mA VOH2 PDOUT: IO = 0.5 mA Output off-state leakage currents Tristate output High-level off-state leakage current Tristate output Low-level off-state leakage current VOL1 VOL2 VOL4 VOL5 IOFF1 IOFF2 DOUT: IO = –1 mA PDOUT: IO = –0.5 mA SYC, TB: IO = 0.5 mA AOUT: IO = 1 mA SYC, TB: VO = VDD AOUT: VO = 13 V IOFFH PDOUT: VO = VDD IOFFL PDOUT: VO = VSS High-level output voltage VOH3 XOUT: IO = –0.1 mA Low-level output voltage VOL3 XOUT: IO = 0.1 mA VDD: fIN1 = 13 MHz, *S = 1 (High speed) (Note 1) fIN1 = 20 MHz, *S = 1 (High speed) (Note 1) VDD: fIN1 = 2.5 MHz, *S = 0 (Low speed) (Note 1) VDD: VDD = 5.5 V, *O = 0, P = 1 (Note 2) VDD = 4.5 V, *O = 0, P = 1 (Note 2) VDD = 3.0 V, *O = 0, P = 1 (Note 2) IDD1 Supply current IDD2 IDD3 typ VI = VDD High-level output voltages Low-level output voltages min 0.01 max 20 40 3.0 1.0 20 40 3.0 1.0 VDD –1.0 VDD –1.0 Unit µA µA µA µA µA µA µA µA V V 1.0 1.0 1.0 1.0 3.0 5.0 V V V V µA µA 0.01 1.0 nA 0.01 1.0 nA VDD –1.0 V 1.2 0.7 0.4 1.0 V 10 mA (12) mA 5 mA 2.0 1.5 1.0 mA mA mA * S, O and P are serial control bits. Note 1. VIN1 = VIN2 = 100 mVms. The 11.16 MHz crystal is connected to XIN and XOUT. All other inputs are connected to VSS and all other outputs are open. 2. The 11.16 MHz crystal is connected to XIN and XOUT. All other inputs are connected to VDD and all other outputs are open. (Backup mode when PLL is halted.) Pin Assignment No.3584-3/7 LC7215, 7215F, 7215FM Block Diagram Pin Description Name XIN, XOUT PIN VDD, VSS DATA, CL, CE DOUT AIN, AOUT PDOUT TB SYC Description 11.16 MHz crystal oscillator connection, feedback resistance built-in Local oscillator signal input Power supply Data input Single bit data output Low-pass filter amplifier Charge pump output 8 Hz time-base output 60 kHz controller clock output No.3584-4/7 LC7215, 7215F, 7215FM Data Input Internal data Input MSB first (1) A to N: Divider data Example: Division by 12,420 (2) O, P: Mode selection Mode O P DOUT TB NOR1 0 0 T 8 Hz Normal operation (with PLL operating) Operation NOR2 0 1 T 8 Hz Normal operation (backup when PLL is halted) TEST1 1 0 (Device test mode) TEST2 1 1 (Device test mode) (3) Q, R: Reference frequency selection Q R Reference frequency 0 0 9 kHz 0 1 10 kHz 1 0 1 kHz 1 1 5 kHz (4) S: Programmable divider input sensitivity switch S = 1: for High speed S = 0: for Low speed (5) T: Output to DOUT T = 1: DOUT = 1 T = 0: DOUT = 0 No.3584-5/7 LC7215, 7215F, 7215FM Data Input Timing VIH = 2.0 to VDD, VIL = 0 to 0.5 V X’tal = 8.00 to 11.16 (typ) to 12.00 MHz Data latch: Rising edge of CL Item Enable setup time Symbol 11.16 MHz crystal Other crystal frequencies tES At least 12 µs At least 2 × (1/fXtal × 62) Enable hold time tEH ↑ ↑ Data setup time tSU ↑ ↑ Data hold time tHD ↑ ↑ Clock Low-level time tLO ↑ ↑ Clock High-level time tHI ↑ ↑ Rise time tR 1 µs or less 1 µs or less Fall time tF ↑ ↑ Effective value 1/2 of the value shown at left No.3584-6/7 LC7215, 7215F, 7215FM (1) Sample Application Circuit (2) Double-conversion Receiver No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No.3584-7/7