Ordering number : EN*5422 CMOS LSI LC82220 Motion JPEG Decoder LSI Preliminaly Overview Package Dimensions The LC82220 is a single-chip JPEG decoder designed for wide range of digital video playback applications including amusement systems, video games and PC JPEG playback cards. The LC82220 is capable of decoding JPEG bitstreams of SIF resolution with a picture rate of 30 frames/sec. The digital video output can be formatted for NTSC, PAL, SECAM, or any other optional video standard. The complete decoding function is realised with the LC82220, a standard 8-bit or 16-bit microcontroller and a bank of DRAM. A typical memory configuration is a single 128 k × 16 or 256 k × 16 DRAM. The LC82220 also supports efficient video display functions such as scroll and overlay. unit: mm 3182-QFP128E [LC82220] Functions • • • • • • • • • • • • • Support for JPEG format Real-time decoding of motion-JPEG with rate of 30 frames/sec Lowest solution cost for amusement, game, PC systems Support for YUV 4:1:1 color format YUV or RGB digital video outputs compatible with optional video format Programmable picture and display window format Support for trick display: scrolling, overlaying Standard 8/16-bit microcontroller interface with DMA support for compressed data input Support SOI and EOI markers Direct connect to video DAC Direct connect to 2 M or 4 M DRAM as bit and frame buffers Two Q-tables included High-speed processing by fixed Huffman tables SANYO: QIP128E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 62096HA (OT) No. 5422-1/6 LC82220 Block Diagram Pin Assignment No. 5422-2/6 LC82220 Pin Functions Pin No. Symbol 1 VDD I/O Function 2 ZCTLINT O Control bus interrupt request (open drain output) 3 ZCTLCS I Control bus select 4 ZCTLRD I Control bus read or R/W select 5 ZCTLWR I Control bus write or Data strobe 6 ZCTLRDY O Control bus ready (tristate output) 7 TEST3 I Test pin 8 TEST4 I Test pin +5 V power supply 9 CTLA5 I 10 CTLA4 I 11 CTLA3 I 12 CTLA2 I 13 CTLA1 I 14 CTLA0 I 15 CTLCPU I 16 VDD 17 VSS 18 CTLD7 I/O 19 CTLD6 I/O 20 CTLD5 I/O 21 CTLD4 I/O 22 CTLD3 I/O 23 CTLD2 I/O 24 CTLD1 I/O 25 CTLD0 I/O 26 TEST0 I Test pin 27 ZRESET I Hardware reset 28 CLKSEL0 I 29 CLKSEL1 I Clock divisor setting CLKSEL1:0 = 00: no divisor, 01: clock divided by 2, 10: clock divided by 3 30 CLK I System (decode) clock input (CMOS level input) 31 TEST1 I Test pin 32 VDD 33 VSS 34 ZCDCS/ZCDACK I Code bus select or Code bus DMA acknowledge 35 ZCDINT/ZCDREQ O Code bus interrupt or Code bus DMA request 36 ZCDWR I Code bus data write signal 37 ZCDRDY O Code bus ready (tristate output) 38 CCD15 I 39 CCD14 I 40 CCD13 I 41 CCD12 I 42 CCD11 I 43 CCD10 I 44 CCD9 I 45 CCD8 I 46 CCD7 I 47 CCD6 I 48 VSS 49 VDD 50 CCD5 I 51 CCD4 I 52 CCD3 I 53 CCD2 I 54 CCD1 I 55 CCD0 I Control bus address Control bus CPU type selection +5 V power supply Ground Control bus data +5 V power supply Ground Code bus data Ground +5 V power supply Code bus data Continued on next page. No. 5422-3/6 LC82220 Continued from preceding page. Pin No. Symbol I/O 56 DB7 O Function 57 DB6 O 58 DB5 O 59 DB4 O 60 DB3 O 61 DB2 O 62 DB1 O 63 DB0 O 64 VSS 65 VDD 66 ZBLANK O 67 ZPXEN I Pixel data enable signal 68 PXCLK I Pixel clock Pixel data bus B (V) Ground +5V power supply Blanking signal 69 ZVSYNC I Vertical synchronizing signal 70 ZHSYNC I Horizontal synchronizing signal 71 DG7 O 72 DG6 O 73 DG5 O 74 DG4 O 75 DG3 O 76 DG2 O 77 DG1 O 78 DG0 O 79 TEST2 I 80 VDD 81 VSS 82 DR7 O 83 DR6 O 84 DR5 O 85 DR4 O 86 DR3 O 87 DR2 O 88 DR1 O 89 DR0 O 90 VSS 91 ZOE O Memory output enable 92 ZWEL O Memory write enable (L) 93 ZRAS O Row address strobe 94 ZCASL O Column address strobe (L) 95 ZWEH/ZCASH O Memory write enable (H)/column address strobe (H) 96 VDD 97 VSS 98 MD15 I/O I/O Pixel data bus G (U) Test pin +5 V power supply Ground Pixel data bus R (Y) Ground +5 V power supply*1 Ground 99 MD14 100 MD13 I/O 101 MD12 I/O 102 MD11 I/O 103 MD10 I/O 104 VDD 105 VSS 106 MD9 I/O 107 MD8 I/O 108 MD7 I/O 109 MD6 I/O 110 MD5 I/O 111 MD4 I/O Frame memory interface data bus +5 V power supply Ground Frame memory interface data bus Continued on next page. No. 5422-4/6 LC82220 Continued from preceding page. Pin No. Symbol 112 VSS I/O Function Ground 113 VDD 114 MD3 I/O +5 V power supply 115 MD2 I/O 116 MD1 I/O 117 MD0 I/O 118 VSS 119 MA8 O 120 MA7 O 121 MA6 O 122 MA5 O 123 MA4 O 124 MA3 O 125 MA2 O 126 MA1 O 127 MA0 O 128 VSS Frame memory interface data bus Ground Frame memory address signals Ground System Configuration Example 1. Separate code bus type This is a system in which the code and system busses are separated. The coded data input does not load down the system bus. No. 5422-5/6 LC82220 2. Shared code bus type This is a system in which code bus and the system bus are connected. Coded data is written by the CPU, or alternatively, data can be written using the DMA controller. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5422-6/6