Edge710
500 MHz Pin Electronics Driver,
Window Comparator, and Load
EDGE HIGH-PERFORMANCE PRODUCTS
Description
Features
The Edge710 is a totally monolithic ATE pin electronics
solution manufactured in a high-performance
complementary bipolar process. In Automatic Test
Equipment (ATE) applications, the Edge710 incorporates
a driver, a load, and a window comparator suitable for
very fast bidirectional channels in VLSI, Mixed-Signal, and
Memory test systems.
•
•
•
•
•
•
•
•
The three-statable driver is capable of generating 9V swings
over a 12V range. In addition, 13V super voltage may be
obtained under certain operating conditions. Separate
rise and fall edge adjustments support both high speed
and low speed applications, and allow for superior rise
and fall time matching. An input power down mode allows
extremely low leakage current in HiZ.
Fully Integrated Three-Statable Driver, Window
Comparator, and Dynamic Active Load
12V Driver, Load, Compare Range
13V Super Voltage Capable
± 35 mA Programmable Load
Comparator Input Tracking >6V/ns
Leakage (L+D+C) < 1 µA (normal mode)
Leakage (L+D+C) < 25 nA (IPD mode)
Small footprint (52 pin MQFP)
Functional Block Diagram
The load supports programmable source and sink currents
of ± 35 mA over a 12V range, or it can be completely
disabled. The source current, sink current, and
commutating voltage are all independently set. In addition,
the load is configurable and may be used as a
programmable voltage clamp.
BIAS
DVH
RADJ
DHI
DHI*
DOUT
DVR_EN
The window comparator spans a 12V common mode
range, tracks input signals with edge rates greater than 6
V/ns, and passes sub-ns pulses. An input power down
mode allows for extremely low leakage measurements.
DVR_EN*
FADJ
DVL
IPD_D
QA*
The inclusion of all pin electronics building blocks into a
52 lead MQFP (10 mm body w/ internal heat spreader)
offers a highly integrated solution that is traditionally
implemented with multiple integrated circuits or discretes.
CVA
QA
PECL
VINP
IPD_C
QB
CVB
QB*
VCC
1KΩ
Applications
ISC_IN
BRIDGE_SC
VCM_IN
VCM_OUT_A
•
•
•
•
VLSI Test Equipment
Mixed-Signal Test Equipment
Memory Testers (Bidirectional Channels)
ASIC Verifiers
LOAD
VCM_OUT_B
1KΩ
BRIDGE_SK
ISK_IN
LD_EN
LD_EN*
VEE
Revision 2 / December 1, 2000
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description
Pin Name
Pin #
Description
Driver
DOUT
30
Driver Output.
DHI/DHI*
12, 13
Wide voltage differential input digital pins which determine the driver high or
low level.
DVR_EN/DVR_EN*
14, 15
Wide voltage differential input digital pins which control the driver being active
or in a high impedance state.
DVH, DVL
20, 19
High impedance analog voltage inputs which determine the driver high and low
level.
DVH_CAP
24
Op amp compensation pin. A 100 pF capacitor should be connected to DVH.
DVL_CAP
25
Op amp compensation pin. A 100 pF capacitor should be connected to DVL.
RADJ, FADJ
17, 16
BIAS
18
Analog current input which sets an internal bias current.
IPD_D
34
TTL driver input power down control which slows the driver down and reduces
the driver HiZ leakage current.
VINP
33
Analog voltage input to the positive input of comparators.
CVA, CVB
50, 51
Analog inputs which set the comparator thresholds.
QA/QA*
QB/QB*
6, 5
10, 11
Differential ECL (or PECL) digital outputs of comparators A and B.
IPD_C
35
TTL input power down input which slows the comparator down, but
significantly reduces the VINP bias current.
PECL
7, 8
LOAD
38
LD_EN/LD_EN*
2, 3
VCM_IN
44
ISC_IN, ISK_IN
48, 45
VCM_CAP
43
Commutating buffer op amp compensation pin.
VCM_OUT_A
VCM_OUT_B
42
41
Commutating voltage pins.
BRIDGE_SC
BRIDGE_SK
40
39
Diode bridge connections to the output bridge that bypass the internal current
sources.
Input currents which determine the driver transition times.
Comparator
Unbuffered power supply level for the comparator output stages which
establishes either ECL or PECL digital levels.
Load
2000 Semtech Corp.
Load Output.
Wide voltage differential inputs which activate and disable the load.
High impedance analog voltage input that programs the commutating voltage.
Analog current inputs which program the load source and sink currents.
Should be connected to external voltage or current source through minimum
500 Ω series resistors.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description (continued)
Pin Name
Pin #
Description
Power Supplies,
Miscellaneous
CATHODE
ANODE
27
26
Terminals of the on-chip thermal diode string.
VCC
4, 31, 32, 49
Positive power supply level.
VEE
1, 28, 29, 52
Negative power supply level.
GND
9, 21, 22, 36,
37, 46, 47
Device Ground.
N/C
23
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BRIDGE_SC
BRIDGE_SK
LOAD
GND
GND
IPD_C
IPD_D
VINP
VCC
VCC
DOUT
VEE
VEE
CATHODE
3
ANODE
DVH_CAP
DVL_CAP
52 MQFP
10 mm X 10 mm
Top Side
DVR_EN
DVR_EN*
FADJ
RADJ
BIAS
DVL
DVH
GND
GND
N/C
VEE
LD_EN
LD_EN*
VCC
QA*
QA
PECL
PECL
GND
QB
QB*
DHI
DHI*
VCM_OUT_A
VCM_OUT_B
VEE
CVB
CVA
VCC
ISC_IN
GND
GND
ISK_IN
VCM_IN
VCM_CAP
No connect.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description
Driver
Driver Levels
Introduction
DVH and DVL are high input impedance voltage controlled
inputs which establish the driver levels of a logical "1" and
"0" respectively.
The driver will force DOUT to one of three states:
Driver Level Buffer Compensation
1. DVH (Drive High)
2. DVL (Drive Low)
3. HiZ (High Impedance).
Both driver digital control inputs (DHI / DHI*, DRV_EN /
DRV_EN*) are "Flex Inputs" - wide voltage differential inputs
capable of receiving ECL, TTL, CMOS, or custom level
signals. Single-ended operation is supported by
connecting the inverting input to the appropriate DC
threshold level.
Drive Enable
The drive enable (DRV_EN / DRV_EN*) inputs control
whether the driver is forcing a voltage, or is placed in a
high-impedance state. If DRV_EN is more positive than
DRV_EN*, the output will force either DVH or DVL,
depending on the driver data input. If DRV_EN is more
negative that DRV_EN*, the output goes into a high
impedance state.
DVH_CAP and DVL_CAP are op amp compensation pins
for the high and low level on-chip buffers. Each pin requires
a 0.01 µF chip capacitor (with good high frequency
characteristics) connected to ground. A tight layout with
minimal distance between the pin and the capacitor is
recommended.
Driver Bias
The BIAS pin is an analog current input which establishes
an on-chip bias current, from which other currents are
generated. This current, to some degree, also establishes
the overall power consumption and performance of the
chip. Ideally, an external current source would be used to
minimize any part-to-part performance variation within a
test system. However, a precision external resistor tied to
a large positive voltage is acceptable. (See figure below.)
The optimal BIAS current is a function of the RADJ and
FADJ settings, and cannot be set independently.
Do NOT leave DRV_EN / DRV_EN* floating.
The established bias current follows the equation:
Driver Data
BIAS = (VCC - 0.7) / (Rext + 1.5).
The driver data inputs (DHI / DHI*) determine whether the
driver output is forcing a high or a low. If DHI is more
positive than DHI*, the driver will force DVH when the
driver is active. If DHI is more negative than DHI*, the
driver will force DVL when active.
VCC
REXT
Do NOT leave DHI / DHI* floating.
BIAS
Driver Enable
Driver Data
DOUT
DRV_EN > DRV_EN*
DHI > DHI*
DVH
DRV_EN > DRV_EN*
DHI < DHI*
DVL
DRV_EN < DRV_EN*
X
HiZ
1.5K
Table 1. Driver Control Truth Table
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
Driver Slew Rate Adjustment
Load
The driver rising and falling transition times are
independently adjustable. The RADJ and FADJ pins are
analog current inputs which establish the driver rise and
fall times.
The load is capable of sourcing and sinking at least 35
mA dynamically, or being placed into a high impedance
state. The load may also be configured with separate
commutating voltage to act as a programmable voltage
clamp. In addition, the load may act as a 50Ω
transmission line termination.
Ideally, an external current source would be used for RADJ
and FADJ. However, for most applications (where the rise
and fall times are fixed), precision external resistors to a
positive voltage are acceptable. The currents into RADJ
and FADJ follow the equation:
RADJ, FADJ = (VCC - 0.7) / (Rext + 1.5).
RADJ (FADJ)
Load Enable
The load enable input determines whether the load is active
or in high impedance. If LD_EN is more positive than
LD_EN*, the load is active and is capable of sourcing and
sinking currents. If LD_EN is more negative than LD_EN*,
the load is placed into a high impedance state.
LD_EN / LD_EN* are "Flex In" - wide voltage differential
inputs capable of receiving ECL, TTL, CMOS, or custom
levels. Single-ended operation is supported by connecting
the inverting input to the appropriate DC threshold level.
1.5KΩ
Do NOT leave LD_EN / LD_EN* floating.
Rise/Fall
Adjust Current
Commutating Voltage
Input Power Down
IPD_D is a TTL compatible input which affects both the
driver speed as well as high impedance leakage. With
IPD_D = 0, the driver functions normally. With IPD_D =
1, the driver is in IPD mode, where it still functions,
although with slower rise and fall times, but with an
extremely low HiZ leakage current.
VCM_IN is a high input impedance analog voltage input
which sets the commutating voltage of the load. If LOAD
is more positive than VCM_IN, the bridge will sink current
from the DUT into the load. If LOAD is more negative than
VCM_IN, the load will source current from the load into
the DUT.
Do not leave IPD_D floating !! If IPD_D is not used,
connect it to ground.
DUT
VCM_IN
DUT
VCM_IN
LOAD < VCM_IN
LOAD > VCM_IN
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
Source and Sink Current Levels
Commutating Voltage Compensation
The amount of current that the diode bridge can source
and sink is adjustable from 0 mA to 35 mA. The source
and sink levels are separate and independent.
The VCM_CAP pin is an op amp compensation node that
requires a fixed .01 µF chip capacitor (with good high
frequency characteristics) to ground. This capacitor is
used to compensate an internal node on the on-chip buffer
for the commutating voltage input.
ISC_IN and ISK_IN are current controlled inputs whose
voltage level is held very close to ground (<100 mV
variation) over the entire legal current input range.
There is a nominal gain of 20 between the ISC_IN current
and the bridge source current.
ISOURCE = 20 * ISC_IN
There is a nominal gain of –20 between the ISK_IN current
and the bridge sink current.
ISINK = –20 * ISK_IN
Because the inversion creates a 180˚ phase shift between
ISK_IN and ISINK, there is a tendency toward instability.
A minimum of 500 W of external series resistance should
be used between an external voltage or current source
and the ISC_IN and ISK_IN pins to ensure stability. Stray
capacitance at the ISK_IN pin should be kept to a
minimum. PCB layout should minimize coupling between
ISK_IN and LOAD.
Caution: The ISKIN and ISCIN inputs are designed for
positive current between 0 mA and 1.75 mA flowing into
the part. Care should be taken to insure that current is
never required to flow out of the part on these two nodes.
I_SOURCE
Split Load
The VCM_OUT_A is the actual commutating voltage
generated by the on-chip buffer. VCM_OUT_A is also
connected to the upper half of the diode bridge, and is
responsible for sinking the programmed source current
when the load is sinking current from the DUT.
VCM_OUT_B is connected to the lower half of the diode
bridge, and is responsible for providing the sink current
when the load is sourcing current to the DUT.
VCM_OUT_B does NOT have an on-chip buffer. To
configure the load as a standard active diode bridge,
connect VCM_OUT_A and VCM_OUT_B together off-chip.
Or, to configure the load as a split load, an external buffer
must be used for VCM_OUT_B.
External Bridge Connections
Access to the top and bottom of the diode bridge is granted
through a 1 KW resistor. Pins BRIDGE_SC and BRIDGE_SK
allow external current sources to be used instead of the
internal I_SOURCE and I_SINK sources. These external
pins are useful when extremely accurate source and sink
currents are required for low current operation.
1KΩ
BRIDGE_SC
VCM_IN
LOAD
1KΩ
BRIDGE_SK
I_SINK
VCM_OUT_A
VCM_OUT_B
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
Window Comparator
Two comparators are connected on-chip to form a window
comparator to determine whether the DUT is high, low, or
in an indeterminant state. VINP is tied to the positive
inputs of both comparators.
The power supply driving the PECL pin must be capable of
sourcing all the current flowing out of the QA/QA* and QB/
QB* open emitter outputs.
The selection of either comparator A or B for the DUT high
versus the DUT low is arbitrary. However, because the
positive input is used on both comparators, the comparator
used to detect DUT low will have an inversion at it digital
outputs.
Comparator Input Protection
The figure below shows the correct polarity for the
comparator connections.
Thermal Monitor
VINP connect to over-voltage diodes connected to the
positive and negative power supplies. These diodes are
sized to handle up to 100 mA current.
An on-chip thermal diode string of five diodes in series
exists (see figure below). This string allows accurate die
temperature measurements.
QA*
CVA
QA
ANODE
IPD_C
VINP
Bias Current
PECL
QB
QB*
CVB
Temperature Coefficient = –9 mV / ˚C
Thresholds
CVA and CVB are the two comparator threshold levels.
These inputs are high impedance voltage controlled inputs
that determine at which VINP voltage the comparators
will change output states.
PECL Level Capability
PECL is the power supply level for the output stage of the
comparators. When connected to ground, the comparator
outputs will be standard ECL outputs. However, by making
PECL more positive, QA / QA* and QB / QB* will track
PECL and also become more positive.
CATHODE
An external bias current of 100 µA is injected through the
string, and the measured voltage corresponds to a specific
junction temperature with the following equation:
Tj[°C] = {(ANODE - CATHODE)/5 – .7752} / (–.0018).
By raising these voltage levels, the comparators may
connect directly with CMOS ICs.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Application Information
Super Voltage Operation
Extremely Low Leakage Usage
The Edge710 may be used to generate a super voltage
level up to 13V at the driver output. To generate this high
voltage, an analog input mux may be used to switch
between the normal high and low drive levels, and a super
voltage level.
The Edge710 is capable of supporting total load + drive
+ comparator leakage ≤ ~15 nA. This low leakage mode
may be very useful during PMU operation if the pin
electronics are not isolated by a relay, thus eliminating
the need for 1 relay per pin.
DVH
To realize this low leakage, the following conditions must
be met:
A
Y
B
1. IPD_D = 1 (place the driver in "power down" mode)
2. IPD_C = 1 (place the comparator in "power down"
mode)
3. CVA, CVB ≥ VINP (program the comparator
thresholds ≥ any expected voltage at the comparator
inputs.)
S/V
710
D_OUT
S/V SELECT
B
Y
DVL
A
Certain Power Supply conditions must be met to support
this functionality.
2000 Semtech Corp.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Package Information
4
D
0.25
4X
C
A–B
D
D2
PIN Descriptions
D
3
A
3
E
4
E2
B
3
e
SEE DETAIL "A"
TOP VIEW
7
5
D1
D
O
E1
O
C
Z
5
7
2
Z
4X
0.20
5
C
7
A–B
D
E
BOTTOM VIEW
2000 Semtech Corp.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Package Information (continued)
0.40 MIN.
˚
0 MIN.
e
A2
–
0.10 S
0.13 / 0.30 R.
0.13
R. MIN.
–A, B, D–
C
GAGE PLANE
3
0.25
C
A1
DETAIL "A"
˚
0–7
L
1.60 REF.
DETAIL "B"
8
SEE DETAIL "B"
˚
12 – 16
ccc
M C A–B S D S
WITH LEAD FINISH
b
1.41 REF.
A
H
2
12 0.13 / 0.23
0.13 / 0.17
0.076
C
b
1
˚
12 – 16
BASE METAL
SECTION C-C
Notes:
1.
All dimensions and tolerances conform to ANSI Y14.5-1982.
2.
Datum plane -H- located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting
line.
3.
Datums A-B and -D- to be determined where centerline
between leads exits plastic body at datum plane -H-.
4.
To be determined at seating plane -C-.
5.
Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254 mm per side.
Dimensions D1 and E1 do include mold mismatch and
are determined at datum plan -H-.
6.
“N” is the total # of terminals.
7.
Package top dimensions are smaller than bottom
dimensions by 0.20 mm, and top of package will not
overhang bottom of package.
8.
Dimension b does not include dambar protrusion.
Allowable dambar protrusion shall be 0.08 mm total in
excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower
radius or the foot.
9.
All dimensions are in millimeters.
10. Maximum allowable die thickness to be assembled
in this package family is 0.635 millimeters.
11. This drawing conforms to JEDEC registered outline MS-108.
12. These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
2000 Semtech Corp.
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JEDEC Variation
(all dimensions in millimeters)
Symbol
Min
A
Nom
Max
Note Comments
2.15
2.35
Height above PCB
A1
0.10
0.15
0.25
PCB Clearance
A2
1.95
2.00
2.10
Body Thickness
D
13.20 BSC
4
D1
10.00 BSC
5
D2
7.80 REF
ZD
1.10 REF
E
13.20 BSC
4
E1
10.00 BSC
5
Body Width
E2
7.80 REF
ZE
1.10 REF
6
Pin Count
L
0.73
0.88
N
52
e
0.65
b
0.22
b1
0.22
aaa
1.03
Lead Pitch
0.38
0.30
Body Length
8
0.33
0.12
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Recommended Operating Conditions
Parameter
Symbol
Min
Max
Units
Positive Power Supply
VCC
9.0
15.5
V
Negative Power Supply
VEE
-8.0
-4.2
V
VCC - VEE
13.2
20.5
V
Comparator Output Supply
PECL
0
5.0
V
Analog Inputs
Driver High Level
DVH
VEE + 3.5
VCC - 2.9
V
Driver Low Level
DVL
VEE + 2.9
VCC - 3.5
V
DVH, DVL
VEE + 3.5
VCC - 2.0
V
RADJ, FADJ
.4
1.3
mA
BIAS
.6
1.25
mA
ISC_IN, ISK_IN
0
1.65
mA
CVA, CVB
VEE + 3.5
VCC - 3.5
V
+70
oC
+125
oC
Total Analog Supply
Super Voltage Levels
Slew Rate Adjustments
Chip Bias
Source, Sink Currents
Comparator Thresholds
Ambient Operating Temperature
TA
Junction Temperature
TJ
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
VCC (relative to GND)
VCC
0
16.5
V
VEE (relative to GND)
VEE
-10
0
V
21.0
V
Total Power Supply
VCC - VEE
Digital Input Voltages
DHI(*), DVR_EN(*), LD_EN(*)
VEE
+7.0
V
Analog Input Voltages
CVA, CVB, DVH, DVL, VCM_IN
VEE
VCC
V
Analog Input Currents
ISC_IN, ISK_IN
0
3.0
mA
Digital Output Currents
QA/QA*, QB/QB*
0
50
mA
Iout
-40
+40
mA
DVH - DVL
0
13
V
CVA(B) - VINP
-13
+13
V
Ambient Operating Temperature
TA
-50
+125
oC
Storage Temperature
TS
-65
+150
oC
Junction Temperature
TJ
+150
oC
TSOL
+260
oC
Driver Output Current
Driver Swing
Comparator Input Voltage
Soldering Temperature
(5 seconds, .25" from the pin)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these, or any other conditions beyond
those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device
reliability.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics
Parameter
Symbol
Min
Commutating Voltage
Programmable Range
Offset Voltage
VCM_IN_A Current In
Diff Voltage Range
VCM_IN
VCM_OUT_A - VCM_IN
Iin
LOAD - VCM_OUT_A
VEE + 3.5
-100
-100
-10
Load Output
Output Voltage Range
Output Current Range
V - LOAD
I - LOAD
Typ
Max
Units
VCC - 3.5
+100
+100
+10
V
mV
µA
V
VEE + 3.5
-35
VCC - 3.5
+35
V
mA
LD_EN, LD_EN*
LD_EN - LD_EN*
Iin
-2.0
±0.25
-100
+5.0
±4.0
+100
V
V
µA
Source Current
Input Current
ISC_IN Voltage
Current Gain
ISC_IN
V_ISC_IN
I_SOURCE/ ISC_IN
0
-100
18.2
0
20
2.0
+100
21.8
mA
mV
Sink Current
Input Current
ISK_IN Voltage
Current Gain
ISK_IN
V_ISK_IN
I_SINK/ ISK_IN
0
-100
18.2
0
20
2.0
+100
21.8
mA
mV
Actual - Programmed
Actual - Programmed
-1µA - 1%
-50
+1µA + 1%
+50
µA
µA
Ibias
-100
+100
nA
VCC
V
2.0
KΩ
1% + 1
1% + 1
+50
+50
+50
+50
+50
+50
+50
µA
µA
µA
µA
µA
µA
µA
µA
µA
LOAD Circuit
Load Enable
Input Voltage Range
Differential Input Swing
Input Current
Load Linearity
0 mA <= Output < 5 mA
5 mA <= Output < 35 mA
HiZ Leakage Current
HiZ Compliance
5
0
VEE + .5
Source/Sink Bridge Resistance
(measured @ I = 500 µA)
Source/Sink Error
Cal Points
Test Point
20 µA / 30 µA
30 µA / 130 µA
130 µA / 500 µA
500 µA / 750 µA
750 µA / 1 mA
1 mA / 1.2 mA
1.2 mA / 1.4 mA
1.4 mA / 1.6 mA
1.6 mA / 1.8 mA
25 µA
80 µA
315 µA
625 µA
875 µA
1.1 mA
1.3 mA
1.5 mA
1.7 mA
.5
-(1% + 1)
-(1% + 1)
-50
-50
-50
-50
-50
-50
-50
1.0
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
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EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Units
V_INP Leakage (IPD = 0)
@ +8V
@ +5V
@ -2V
@ -4V
I_BIAS
I_BIAS
I_BIAS
I_BIAS
-2
-1
-1
-1
±1 <
+2
+1
+1
+1
µA
µA
µA
µA
V_INP Leakage (IPD = 1)
@ VEE + 3.5V
@ VCC - 3.5V
I_BIAS
I_BIAS
-250
-250
±100 <
±100 <
+250
+250
nA
nA
Vos
Vos
-10
-10
+10
+10
mV
mV
CVA, CVB
VEE + 2.9
VCC - 2.9
V
I_BIAS CVA(B)
-50
+50
µA
V_INP
VEE + 3.5
VCC - 3.5
V
Input Diffierential Range
V_INP - CVA(B)
-12
+8
V
Differential Output Swing
|QA - QA*|, |QB - QB*|
400
QA, QA*, QB, QB*
QA, QA*, QB, QB*
PECL - 1.3
PECL - 1.8
ICC
IEE
120
-200
COMPARATOR Circuit
Offset Voltage (Note 1)
IPD_C = 0
IPD_C = 1
Threshold Voltage
Threshold Input Current
Input Voltage Range
Common Mode Output (Note 2)
Logical 1
Logical 0
mV
PECL - 1.13
PECL - 1.64
PECL - 0.9
PECL - 1.4
V
V
180
-160
mA
mA
POWER SUPPLIES
Power Supply Consumption
(Note 3)
Positive Supply
Negative Supply
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
Note 1: This parameter is guaranteed by characterization. It is tested in production against ± 100 mV
limits.
Note 2: Tested at PECL = 0V, PECL = +4V.
Note 3: No Load Conditions.
2000 Semtech Corp.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics (continued)
Parameter
Symbol
Min
DV H
DV L
DV H, DV L
DV H - DV L
I _in
R A DJ, F A DJ
BIA S
V EE + 3.5
V EE + 2.9
V EE + 3.5
0
– 50
0.4
.6
I max
R out
I bias
I bias
DC "Hig h" A c c urac y
Offset V olt ag e
Gain ( Not e 2)
Linearit y ( -2V t o +7V )
Linearit y ( @ -3V , @ +8V )
Typ
Max
Units
V C C - 2.9
V C C - 3.5
V C C - 2.0
9.0
+50
1.3
1.25
V
V
V
V
µA
mA
mA
-35
0.5
– 250
–5
+35
3.0
+250
+5
mA
Ω
nA
nA
DV H - DOUT
∆DV H/ ∆DOUT
DV H - DOUT
DV H - DOUT
– 100
.985
-10
-15
+100
1.0
+10
+15
mV
V/ V
mV
mV
DC "Low " A c c urac y
Offset V olt ag e
Gain ( Not e 3)
Linearit y ( -3V t o +6V )
Linearit y ( @ -4V , @ +7V )
DV L - DOUT
∆DV L/ ∆DOUT
DV L - DOUT
DV L - DOUT
– 100
.985
– 10
– 15
+100
1.0
+10
+15
mV
V/ V
mV
mV
Dig it al I nput s
I nput V olt ag e R ang e
Different ial I nput Sw ing
I nput C urrent
DHI ( *) , DV R _EN( *)
I nput - I nput *
I in
– 2.0
±0.25
– 350
+5.0
±4.0
+350
V
V
µA
DRIVER Circuit
A nalog I nput s
Hig h Lev el
Low Lev el
Super V olt ag e Lev els
Driv er Sw ing
I nput C urrent
Slew R at e A dj ust ment s
C hip B ias C urrent
Driv er Out put
DC Out put C urrent
Out put I mpedanc e ( @ ±25 mA )
HiZ Leak ag e ( I P D_D = 0)
HiZ Leak ag e ( I P D_D = 1) ( Not e 1)
Note 1:
Note 2:
Note 3:
0.6
This parameter is guaranteed by characterization. It is tested in production against ± 200 nA
limits.
Gain is computed from 2 points: DVH = –1V, +4V.
Gain is computed from 2 points: DVL = –1V, +4V.
2000 Semtech Corp.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
AC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
LOAD Circuit
Propagation Delay
Inhibit to Iout
Iout to Inhibit
Output Capacitance
Load Active
Load Off
Tpd_on
Tpd_off
3
<.8
Cout
Cout
ns
ns
3.5
2.0
pF
pF
COMPARATOR Circuit
Propagation Delay
Tpd
1.5
Input Slew Rate Tracking
IPD_C = 0
IPD_C = 1
Input Capacitance
Digital Output Rise and Fall Times
(20% - 80%)
ns
6.0
25
V/ns
mV/ns
Cin
2.0
pF
Tr, Tr
250
ps
Minimum Pulse Width
1.0
ns
DRIVER Circuit
Propagation Delay
Data to Output
Enable to HiZ
Enable to Output Active
Tpd
Tpd
Tpd
1.5
1.5
1.5
ns
ns
ns
Rise/Fall Times
800 mV (20% - 80%)
3V (10% - 90%)
5V (10% - 90%)
Tr/Tf
Tr/Tf
Tr/Tf
500
800
1.0
ps
ps
ns
Fmax
800 mV
3V
5V
Fmax
Fmax
Fmax
600
400
200
MHz
MHz
MHz
800
1.2
2.4
ps
ns
ns
2.0
pF
Minimum Pulse Width
800 mV
3V
5V
Output Capacitance
Cout
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
2000 Semtech Corp.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Ordering Information
Model Number
Package
E710AHF
52 Lead MQFP (10 mm x 10 mm Body)
with Internal Heat Spreader
D710
Die Form
EVM710AHF
Edge710 Evaluation Board
Contact Information
Semtech Corporation
Edge High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
2000 Semtech Corp.
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