74ACT273 OCTAL D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 190 MHz ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The ACT273 is a high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. M (Micro Package) B (Plastic Package) ORDER CODES : 74ACT273B 74ACT273M 74ACT273T T (TSSOP Package) Information signals applied to D inputs are transfered to the Q output on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independentely of the other inputs . The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS May 1999 1/11 74ACT273 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 CLEAR Asyncronous Master Reset (Active LOW) NAME AND FUNCT ION 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 Flip-Flop Outpus 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs 11 CLOCK Clock Input (LOW-to-HIGH, EdgeTriggered) 10 GND Ground (0V) 20 VCC Positive Supply Voltage TRUTH TABLE INPUTS OUT PUT S CL EAR D CLO CK Q L X X L H L L H H H H X Qn X:Don’t Care LOGIC DIAGRAMS Thislogic diagram has notbe used to esimate propagation delays 2/11 F UNCTIO N CLEAR NO CHANGE 74ACT273 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA DC VCC or Ground Current ± 400 mA ICC orIGND Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Value Unit 4.5 to 5.5 V V VI Input Voltage 0 to VCC VO Output Voltage 0 to VCC Top dt/dv Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) -40 to +85 8 V o C ns/V 1) VIN from 0.8 V to 2.0 V 3/11 74ACT273 DC SPECIFICATIONS Symb ol Parameter Test Co nditions VIH High Level Input Voltage 4.5 5.5 VIL Low Level Input Voltage 4.5 5.5 VOH High Level Output Voltage 4.5 5.5 Low Level Output Voltage T yp. 2.0 1.5 2.0 2.0 1.5 2.0 VO = 0.1 V or VCC - 0.1 V VI(*) = VIH or VIL Max. Min. Max. V 1.5 0.8 0.8 1.5 0.8 0.8 IO=-50 µA 4.4 4.49 4.4 IO=-50 µA 5.4 5.49 5.4 V V 3.86 IO=-24 mA 4.86 4.5 IO=50 µA 0.001 0.1 0.1 IO=50 mA 0.001 0.1 0.1 IO=24 mA 0.36 0.44 IO=24 mA 0.36 0.44 ±0.1 ±1 µA 1.5 mA 40 µA 5.5 5.5 Input Leakage Current Min. IO=-24 mA 4.5 II VO = 0.1 V or VCC - 0.1 V Un it -40 to 85 o C 5.5 4.5 VOL Valu e T A = 25 oC V CC (V) 5.5 (*) VI = VIH or VIL 3.76 4.76 VI = VCC orGND ICCT Max ICC /Input 5.5 VI = VCC -2.1V ICC Quiescent Supply Current 5.5 VI = VCC orGND IOLD Dynamic Output Current (note 1, 2) 5.5 VOLD = 1.65 V max 75 mA VOHD = 3.85 V min -75 mA IOHD 1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. 4/11 0.6 V 4 74ACT273 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns) Symb ol Parameter T est Con ditio n V CC (V) tPLH tPHL tPLH tPHL twL Propagation Delay Time CK to Q 5.0(*) Propagation Delay Time CLR to Q (*) CLR pulse Width, LOW 5.0 Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 1.5 6.5 8.5 1.5 9.0 1.5 9.5 ns 7.0 9.0 (*) 1.5 4.0 4.0 ns (*) ns 5.0 1.5 Un it tw CK pulse Width 5.0 1.0 4.0 4.0 ts Setup Time Q to CK HIGH or LOW 5.0(*) 1.0 3.5 3.5 th Hold Time Q to CK HIGH or LOW 5.0(*) -0.5 1.5 1.5 (*) 0.5 3.0 3.0 tREM Recovery Time CLR to CK 5.0 fMAX Maximum Clock Frequency 5.0(*) 125 190 110 ns ns ns ns MHz (*) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditions CIN Input Capacitance 5.0 CPD Power Dissipation Capacitance (note 1) 5.0 Valu e T A = 25 oC V CC (V) Min. fIN = 10 MHz T yp. Max. Un it -40 to 85 o C Min. Max. 4 pF 32 pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n(per circuit) 5/11 74ACT273 TEST CIRCUIT CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74ACT273 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle) 7/11 74ACT273 Plastic DIP-20 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.053 P001J 8/11 74ACT273 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 9/11 74ACT273 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e E1 PIN 1 IDENTIFICATION 1 L E c D 10/11 MAX. 74ACT273 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com . 11/11