74VHCT74A DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX =160 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74VHCT74A is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transfered to the Q OUTPUT during the positive going transition of SOP TSSOP ORDER CODES PACKAGE T UBE T& R SOP 74VHCT74AM 74VHCT74AMTR TSSOP 74VHCT74ATTR the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS March 2000 1/10 74VHCT74A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 13 1CLR, 2CLR Asyncronous Reset Direct Input NAME AND FUNCT ION 2, 12 1D, 2D Data Input 3, 11 1CK, 2CK Clock Input (LOW-to-HIGH, EdgeTriggered) 4, 10 1PR, 2PR Asyncronous Set - Direct Input 5, 9 1Q, 2Q True Flip-Flop Outputs 6, 8 1Q, 2Q Complement Flip-Flop Outputs 7 GND Ground (0V) 14 VCC Positive Supply Voltage TRUTH TABLE INPUTS OUT PUT S CLR PR D CK L H X H L X Q X L H CLEAR X H L PRESET X H H L H L L X H H L H H H H L H H X Qn Qn X:Don’t Care LOGIC DIAGRAM Thislogic diagram has notbe used to estimate propagation delays 2/10 F UNCTION Q NO CHANGE 74VHCT74A ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (see note 1) -0.5 to +7.0 V VO DC Output Voltage (see note 2) -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA ICC or IGND DC VCC or Ground Current Tstg TL Storage Temperature -65 to +150 o 300 o Lead Temperature (10 sec) C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) VCC=0 2) High or Low State RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Valu e Unit 4.5 to 5.5 V VI Input Voltage 0 to 5.5 V VO Output Voltage (see note 1) 0 to 5.5 V VO Output Voltage (see note 2) Top Operating Temperature dt/dv 0 to VCC V o -40 to +85 Input Rise and Fall Time (see note 3) (V CC = 5.0 ± 0.5V) C 0 to 20 ns/V 1) VCC=0 2) High or Low State 3)VIN from0.8V to 2 V DC SPECIFICATIONS Symb ol Parameter T est Cond ition s Min. 2 VIH High Level Input Voltage 4.5 to 5.5 VIL Low Level Input Voltage 4.5 to 5.5 VOH High Level Output Voltage VOL Low Level Output Voltage Value T A = 25 o C V CC (V) Typ . Un it -40 to 85 o C Max. Min . 0.8 4.5 I O =-50 µA 4.4 4.5 IO=-8 mA 3.94 4.5 I O=50 µA 4.5 Max. 2 4.5 V 0.8 4.4 V 3.8 0.0 V 0.1 0.1 IO=8 mA 0.36 0.44 V 0 to 5.5 VI = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current 5.5 VI = VCC or GND 2 20 µA ∆ICC Additional Worst Case Supply Current 5.5 One Input at 3.4V, other input at VCC or GND 1.35 1.5 mA IOPD Output Leakage Current 0 VOUT = 5.5V 0.5 5.0 µA II Input Leakage Current 3/10 74VHCT74A AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter tPLH tPHL Propagation Delay Time CK to Q or Q 5.0(*) 5.0(*) 15 50 Value T A = 25 o C Min. Typ . Max. 5.8 7.8 6.3 8.8 tPLH tPHL Propagation Delay Time PR or CLR to Q or Q 5.0(*) 5.0(*) 15 50 7.6 8.1 CK Pulse Width HIGH or LOW 5.0 V CC (V) tw tw PR or CLR Pulse Width LOW Test Co ndition CL (pF ) 10.4 11.4 (*) (*) 5.0 (*) Un it -40 to 85 o C Min . Max. 1.0 9.0 1.0 10.0 1.0 1.0 12.0 13.0 5.0 5.0 5.0 5.0 ts Setup Time D to CK HIGH or LOW 5.0 5.0 5.0 th Hold Time D to CK HIGH or LOW 5.0(*) 0.0 0.0 tREM Removal Time CLR or PR to CK 5.0(*) 3.5 3.5 fMAX Maximum Clock Frequency 5.0(*) 5.0(*) 15 50 100 80 160 140 80 65 ns ns ns ns ns ns ns MHz (*) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symb ol Parameter T est Cond ition s Value o T A = 25 C Min. C IN Input Capacitance CPD Power Dissipation Capacitance (note 1) -40 to 85 C Typ . Max. 4 10 10.5 Un it o Min . Max. 10 pF pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/2 (per Gate) 4/10 74VHCT74A TEST CIRCUIT CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 5/10 74VHCT74A WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 6/10 74VHCT74A WAVEFORM 3: REMOVAL TIMES (f=1MHz; 50% duty cycle) WAVEFORM 4: PULSE WIDTH 7/10 74VHCT74A SO-14 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 (max.) P013G 8/10 74VHCT74A TSSOP14 MECHANICAL DATA mm DIM. MIN. inch TYP. A MAX. MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 9/10 74VHCT74A Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 10/10