STLVD111 PROGRAMMABLE LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK DRIVER ■ ■ ■ ■ ■ ■ ■ ■ ■ 100ps PART-TO PART SKEW 50ps BANK SKEW DIFFERENTIAL DESIGN MEETS LVDS SPEC. FOR DRIVER OUTPUTS AND RECEIVER INPUTS REFERENCE VOLTAGE AVAILABLE OUTPUT VBB LOW VOLTAGE VCC RANGE OF 2.375V TO 2.625V HIGH SIGNALLING RATE CAPABILITY (EXCEEDS 622MHz) SUPPORT OPEN, SHORT AND TERMINATED INPUT FAIL-SAFE (LOW OUTPUT STATE) PROGRAMMABLE DRIVERS POWER OFF CONTROL DESCRIPTION The STLVD111 is a low skew programmable 1 to 10 differential LVDS driver, designed for clock distribution. The select signal is fanned out to 10 identical differential outputs. The STLVD111 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input. The STLVD111 is specifically designed, modelled and TQFP32 produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device. The STLVD111 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can take advantage of the device’s performance to distribute low skew clocks across the backplane or the board. ORDERING CODES Type Temperature Range Package Comments STLVD111BF STLVD111BFR -40 to 85 °C -40 to 85 °C TQFP32 (Tray) TQFP32 (Tape & Reel) 250 parts per Tray 2400 parts per reel December 2002 1/12 STLVD111 PIN CONFIGURATION PIN DESCRIPTION PlN N° SYMBOL 1 CK 2 3 4 SI CLK0 CLK0 VBB Control Register Serial IN/CLK_SEL Differential Input Differential Input Output Reference Voltage CLK1 CLK1 EN GND Q9 Q9 Q8 Q8 Q7 Q7 VCC Differential Input Differential Input Device Enable/Program Ground Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Supply Voltage Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 GND Q2 Q2 Q1 Q1 Q0 Q0 VCC Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Ground Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Supply Voltage 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2/12 NAME AND FUNCTION Control Register Clock STLVD111 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.3 to 2.8 V VI Input Voltage -0.2 to (VCC+0.2) V VO Output Voltage -0.2 to (VCC+0.2) V IOSD Driver Short Circuit Current ESD Electrostatic Discharge (HBM 1.5KΩ, 100pF) Continuous >2 KV Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. THERMAL DATA Symbol RTj-c Parameter Value Unit 13 °C/W Thermal Resistance Junction-Case RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min TYP Max Unit 2.375 2.625 V VCC Supply Voltage VIC Receiver Common Mode Input Voltage 0.5(VID) 2-0.5(VID) V TA Operating Free-Air Temperature Range -40 85 °C TJ Operating Junction Temperature -40 105 °C DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified (Note 1, 2) Value Symbol VOD ∆VOD VOS ∆VOS IOS Parameter Test Conditions Output Differential Voltage (Fig. 2) VOD Magnitude Change RL = 100 Ω Offset Voltage -40 ≤ TA ≤ 85°C Unit Min. Typ. Max. 400 500 600 mV 30 mV 1.05 1.15 1.25 V 30 V 15 30 mA 7 15 VOS Magnitude Change Output Short Circuit Current VO = 0V VOD = 0V NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. NOTE 2: All typical values are given for VCC = 2.5V and TA = 25°C unless otherwise stated. RECEIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified (Note 1, 2) Value Symbol Parameter Test Conditions Unit Min. VIDH Input Threshold High VIDL Input Threshold Low IIN Input Current Typ. Max. 100 -100 mV mV VI = 0V 42 100 VI = 0VCC 2 10 µA NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. NOTE 2: All typical values are given for VCC = 2.5V and TA = 25°C unless otherwise stated. 3/12 STLVD111 DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified (Note 1, 2) Value Symbol Parameter Test Conditions VBB Output Reference Voltage VCC = 2.5 V ICCD Power Supply Current All driver enabled and loaded CIN Input Capacitance VI = 0V to VCC COUT Typ. Max. 1.15 1.25 1.35 V 125 160 mA Output Capacitance VIH Logic Input High Threshold VIL Logic Input Low Threshold VCC = 2.5 V Logic Input Current VCC = 2.5 V, II Unit Min. VCC = 2.5 V 5 pF 5 pF 2 V VIN = VCC or GND 0.8 V ±10 µA NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. NOTE 2: All typical values are given for VCC = 2.5V and TA = 25°C unless otherwise stated. LVDS TIMING CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified (Note 4) Value Symbol Parameter Test Conditions Unit Min. tTLH, tTHL Transition Time RL = 100 Ω, CL = 5 pF, Fig. 5, 6) tPHL, tPLH Propagation Delay Time (Fig. 5, 6) fMAX tSKEW Maximum Input Frequency Bank Skew Part to Part Skew Pulse Skew 700 (Fig. 1) (Fig. 2) (Fig. 3) Typ. Max. 220 300 ps 2 2.5 ns 900 MHz 50 100 50 ps NOTE 4: Generator waveforms for all test conditions: f=1MHz, ZO = 50 Ω (unless otherwise specified). CONTROL REGISTER TIMING CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, EN=H, unless otherwise specified (Figure 4) Value Symbol fMAX Test Conditions Unit Min. Typ. 100 150 Max. (Fig. 7) ts Maximum Frequency of Shift Register Clock to SI Setup Time (Fig. 7) 2 ns th Clock to SI Hold Time (Fig. 7) 1.5 ns Enable to Clock Removal Time (Fig. 7) 1.5 ns Minimum Clock Pulse Width (Fig. 7) trem tW 4/12 Parameter 3 MHz ns STLVD111 SPECIFICATION OF CONTROL REGISTER The STLVD111 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose is to enable or power of each output clock channel and to select the clock input. The STLVD111 provides two working modality: PROGRAMMED MODE (EN=1) The shift register have a serial input to load the working configuration. Once the configuration is loaded with 11 clock pulse, another clock pulse load the configuration into the control register. The first bit on the serial input line enables the outputs Q9 and Q9, the second bit enables the outputs Q8 and Q8 and so on. The last bit is the clock selection bit. To restart the configuration of the shift register a reset of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register shift register can be configured on time after each reset. STANDARD MODE (EN=0) In Standard Mode the STLVD111 isn’t programmable, all the clock outputs are enabled. The LVDS clock input is selected from Clock 0 or Clock 1 with the SI pin as shown in the Truth Table below. TRUTH TABLE OF STATE MACHINE INPUTS EN SI CK OUTPUT L L L H X X H L All Output Enabled, Clock 0 selected, Control Register disabled All Output Enabled, Clock 1 selected, Control Register disabled First stage stores "L", other stages store the data of previous stage H H First stage stores "H", other stages store the data of previous stage L X Reset of the state machine, Shift register and Control Register SERIAL INPUT SEQUENCE BIT#10 BIT#9 BIT#8 BIT#7 BIT#6 BIT#5 BIT#4 BIT#3 BIT#2 BIT#1 BIT#0 CLK_SEL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 TRUTH TABLE OF THE CONTROL REGISTER BIT#10 BIT#(0-9) Qn(0-9) L H X H H L Clock 0 Clock 1 Qn Output Disabled TRUTH TABLE CK EN SI CLK 0 CLK 0 CLK 1 CLK 1 Q (0-9) Q(0-9) L L L L L L L L L L L L All drivers enable L L L H H H L H Open X X X H L Open X X X X X X L H Open X X X H L Open L H L L H L H L H H L H 5/12 STLVD111 LOGIC DIAGRAM 6/12 STLVD111 Figure 1 : BANK SKEW - tsk(b) Figure 2 : PART TO PART SKEW - tsk(PP) Figure 3 : PULSE SKEW - tsk(P) tsk(b): BANKSKEW is the magnitude of the time difference between outputs with a single driving input terminal tsk(pp): PART TO PART SKEW is the magnitude of the difference in propagation delay times between any specific terminals of two devices when both devices operate with the same input signals, the same supply voltages, and the same temperature, and have identical packages and test circuits. tsk(b): PULSE SKEW is the magnitude of the time difference between the high to low and low to high propagation delay times at an output. 7/12 STLVD111 Figure 4 : VOLTAGE AND CURRENT DEFINITION Figure 5 : TEST CIRCUIT AND VOLTAGE DEFINITION FOR THE DIFFERENTIAL OUTPUT SIGNAL 8/12 STLVD111 Figure 6 : DIFFERENTIAL RECEIVER TO DRIVE PROPAGATION DELAY AND DRIVE TRANSITION TIME WAVEFORMS Figure 7 : SET-UP, HOLD AND THE REMOVAL TIME, MAXIMUM FREQUENCY, MINIMUM PULSE WIDTH WAVEFORMS 9/12 STLVD111 TQFP32 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.6 A1 0.05 A2 1.35 B 0.30 C 0.09 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.015 0.018 0.20 0.0035 0.0079 D 9.00 0.354 D1 7.00 0.276 D3 5.60 0.220 E 0.80 0.031 E 9.00 0.354 E1 7.00 0.276 E3 5.60 0.220 L 0.45 0.60 L1 0.75 0.018 0.024 1.00 K 0˚ 0.030 0.039 3.5˚ 7˚ 0˚ 3.5˚ 7˚ D A D1 A2 D3 24 A1 17 25 16 0.10mm .004 B E E1 B E3 Seating Plane 9 32 8 1 C L L1 e K TQFP32 0060661/C 10/12 STLVD111 Tape & Reel TQFP32 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 9.5 9.7 0.374 0.382 Bo 9.5 9.7 0.374 0.382 Ko 2.1 2.3 0.083 0.091 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 11/12 STLVD111 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 12/12