SAMSUNG K1S6416BCC-I

K1S6416BCC
UtRAM
Document Title
4Mx16 bit Page Mode Uni-Transistor Random Access Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial Draft
- Design Target
November 3, 2004
Preliminary
1.0
Finalize
April 06, 2005
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
4M x 16 bit Page Mode Uni-Transistor CMOS RAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The K1S6416BCC is fabricated by SAMSUNG′s advanced
CMOS technology using one transistor memory cell. The device
supports 4 page read operation and Industrial temperature
range. The device supports dual chip selection for user interface. The device also supports internal Temperature Compensated Self Refresh mode for the standby power saving at room
temperature range.
Process Technology: CMOS
Organization: 4M x16 bit
Power Supply Voltage: 1.7~2.0V
Three State Outputs
Compatible with Low Power SRAM
• Support 4 page read mode
• Package Type: TBD
PRODUCT FAMILY
Product Family
Operating Temp.
Vcc Range
Speed
(tRC)
K1S6416BCC-I
Industrial(-40~85°C)
1.7~2.0V
70ns
Power Dissipation
Standby
(ISB1, Max.)
120µA(< 40°C)
Operating
(ICC2, Max.)
PKG Type
40mA
TBD
180µA(< 85°C)
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Clk gen.
Precharge circuit.
VCC
VCCQ
VSS
Row
Addresses
TBD
I/O1~I/O8
Row
select
Data
cont
Memory array
I/O Circuit
Column select
Data
cont
I/O9~I/O16
Data
cont
Column Addresses
CS1
CS2
OE
Control Logic
WE
UB
LB
Name
Function
CS1,CS2 Chip Select Inputs
Name
Vcc/V
CCQ2)
Function
Power Supply(core / I/O)
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O9~16)
A0~A21
Address Inputs
I/O1~I/O16 Data Inputs/Outputs
LB
Lower Byte(I/O1~8)
NC
No Connection1)
1) Reserved for future use
2) VCC and VCCQ should be the same level
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min. and VCCQ min.=1.7V) for a minimum 200µs with CS1=high.or CS2=low.
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)
Min. 200µs
VCC
≈
VCCQ(Min)
VCCQ
≈
VCC(Min)
≈
CS1
≈ ≈
CS2
Power Up Mode
Normal Operation
POWER UP(1)
1. After VCC reaches VCC(Min.) and VCCQ(Min.), wait 200µs with CS1 high. Then the device gets into the normal operation.
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)
VCC
≈
CS2
≈ ≈
CS1
≈
VCCQ(Min)
VCCQ
Min. 200µs
≈
VCC(Min)
Power Up Mode
Normal Operation
POWER UP(2)
1. After VCC reaches VCC(Min.) and VCCQ(Min.), wait 200µs with CS2 low. Then the device gets into the normal operation.
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
FUNCTIONAL DESCRIPTION
CS1
CS2
H
X
X1)
L
1)
OE
1)
WE
LB
UB
I/O1~8
I/O9~16
Mode
Power
1)
1)
X
X
High-Z
High-Z
Deselected
Standby
X1)
X1)
X1)
X1)
High-Z
High-Z
Deselected
Standby
1)
1)
X
H
H
High-Z
High-Z
Deselected
Standby
X
1)
1)
X
X
X1)
X
L
H
H
H
L
X
L
H
H
H
X1)
L
L
H
L
H
L
L
H
L
H
H
L
H
L
H
L
H
X1)
L
L
H
X1)
L
L
H
X1)
L
High-Z
High-Z
Output Disabled
Active
High-Z
High-Z
Output Disabled
Active
H
Dout
High-Z
Lower Byte Read
Active
L
High-Z
Dout
Upper Byte Read
Active
L
L
Dout
Dout
Word Read
Active
L
H
Din
High-Z
Lower Byte Write
Active
H
L
High-Z
Din
Upper Byte Write
Active
L
L
Din
Din
Word Write
Active
1)
1. X means don′t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
Ratings
Unit
VIN, VOUT
-0.2 to VCCQ+0.3V
V
VCC
-0.2 to 2.5V
V
PD
1.0
W
TSTG
-65 to 150
°C
TA
-40 to 85
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
PRODUCT LIST
Industrial Temperature Product(-40~85°C)
Part Name
Function
K1S6416BCC
70ns, 1.85V
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
1.7
1.85
2.0
V
Ground
Vss
0
0
0
V
Input high voltage
VIH
0.8 x VCCQ
-
VCCQ+0.22)
V
Input low voltage
VIL
-0.23)
-
0.4
V
Max
Unit
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: VCCQ+1.0V in case of pulse width ≤20ns.
3. Undershoot: -1.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Item
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=Vss to VCCQ
Test Conditions
-1
-
1
µA
Output leakage current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH,
VIO=Vss to VCCQ
-1
-
1
µA
Average operating current
ICC2
Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1=VIL,
CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIH or VIL
-
-
40
mA
Output low voltage
VOL
IOL=0.1mA
-
-
0.2
V
Output high voltage
VOH
IOH=-0.1mA
1.4
-
-
V
-
-
120
µA
ISB11)
Other inputs=0~VCCQ
1) CS1≥VCCQ-0.2V, CS2≥VCCQ-0.2V(CS1
controlled) or
2) 0V ≤ CS2 ≤ 0.2V(CS2 controlled)
< 40°C
Standby Current(CMOS)
< 85°C
-
-
180
µA
Symbol
1. Standby mode is supposed to be set up after at least one active operation.after power up.
ISB1 is measured after 60ms from the time when standby mode is set up.
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
Vt=0.5 x VCCQ
AC Output Load Circuit
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
50Ω
Input pulse level: 0.2 to VCCQ-0.2V
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x VCCQ
Output load (See right): CL=30pF
Dout
Z0=50Ω
30pF
AC CHARACTERISTICS (Vcc=VCCQ=1.7~2.0V, TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Common
Read
Write
Units
70ns
Max
CS High Pulse Width
tCSHP
10
-
ns
Address Access Time
tAA
-
70
ns
Chip Select to Output
tCO
-
70
ns
Output Enable to Valid Output
tOE
-
35
ns
UB, LB Access Time
tBA
-
70
ns
Chip Select to Low-Z Output
tLZ
10
-
ns
UB, LB Enable to Low-Z Output
tBLZ
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
ns
Chip Disable to High-Z Output
tHZ
0
25
ns
UB, LB Disable to High-Z Output
tBHZ
0
25
ns
Output Disable to High-Z Output
tOHZ
0
25
ns
Output Hold from Address Change
tOH
3
-
ns
Page Cycle
tPC
25
-
ns
Page Access Time
tPA
-
20
ns
Write Cycle Time
tWC
70
-
ns
Chip Select to End of Write
tCW
60
-
ns
Address Set-up Time
tAS
0
-
ns
Address Valid to End of Write
tAW
60
-
ns
UB, LB Valid to End of Write
tBW
60
-
ns
Write Pulse Width
tWP
551)
-
ns
WE High Pulse Width
tWHP
5
-
ns
Write Recovery Time
tWR
0
-
ns
Write to Output High-Z
tWHZ
0
25
ns
Data to Write Time Overlap
tDW
30
-
ns
Data Hold from Write Time
tDH
0
-
ns
End Write to Output Low-Z
tOW
5
-
ns
1. tWP(min)=70ns for continuous write operation over 50 times.
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH)
tRC
Address
tAA
tCSHP
tOH
tCO
CS1
CS2
tCHZ
tBA
UB, LB
tBHZ
tOE
OE
Data out
tOLZ
tBLZ
tLZ
High-Z
tOHZ
Data Valid
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
A21~A2
Valid
Address
A1~A0
Valid
Address
Valid
Address
tAA
Valid
Address
Valid
Address
tPC
CS1
CS2
tHZ
tCO
OE
DQ15~DQ0
tOHZ
tPA
tOE
High Z
Data
Valid
Data
Valid
Data
Valid
Data
Valid
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
tWC
Address
tAW
tCW
tCSHP
tWR
tWR
tAW
tCW
CS1
CS2
tBW
tBW
UB, LB
tWHP
tWP
WE
tAS
tAS
tDH
tDW
Data Valid
tDH
tDW
Data Valid
Data in
tWHZ
Data out
tWP
tWHZ
tOW
Data Undefined
tOW
Data Undefined
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tAS
tWR
tCW
CS1
tAW
CS2
tBW
UB, LB
tWP
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS
tWR
tCW
CS1
tAW
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
tWR
tCW
CS1
tAW
CS2
tBW
UB, LB
tAS
tWP
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
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Revision 1.0
April 2005
K1S6416BCC
UtRAM
PACKAGE DIMENSION
TBD
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Revision 1.0
April 2005