Ordering number : ENN*7275 CMOS IC LC723461W, 723462W Ultralow-Voltage ETR Controller with On-Chip LCD Driver Preliminary Overview • • • • Function • Continued on next page. Package Dimensions unit: mm 3190A-SQFP64 [LC723461W, 723462W] 48 0.5 12.0 10.0 33 32 10.0 12.0 49 64 17 1 16 (0.5) 0.15 0.18 (1.5) (1.25) 0.1 • Program memory (ROM): — 4096 × 16 bits (8K bytes) : LC723461 — 6144 × 16 bits (12K bytes): LC723462 • Data memory (RAM): — 256 × 4 bits: LC723461 — 512 × 4 bits: LC723462 • Cycle time: 40 µs (all 1-word instructions) at 75kHz crystal oscillation • Stack: 8 levels • LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive) • Interrupts: Two external interrupts Timer interrupts (1, 5, 10, and 50 ms) • A/D converter: Four input channels (8-bit chopper A/D converter. The reference voltage can be switched using the ADCHG instruction.) • Input ports: 8 ports (of which three can be switched for use as A/D converter input and one can be switched for use as IF counter input.) • Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are open-drain ports) • I/O ports: 19 ports (of which 8 can be switched for use as LCD ports and as mask options, of which 3 can be 1.7max The LC723461W and LC723462W are ultralow-voltage electronic tuning microcontrollers that include a PLL that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. This IC includes an on-chip DC-DC converter that can easily create the power supply voltages needed for electronic tuning and contribute to reducing end product costs. This IC is optimal for portable audio equipment that must operate from a single battery. switched for use as serial I/O ports) Can be switched for CMOS output/open-drain outputs. Serial I/O: One system (LC723462) PLL: Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz Input frequencies: FM band: 10 to 250 MHz AM band (high): 2 to 20 MHz AM band (low): 0.5 to 10 MHz Input sensitivity: FM band: 35 mVrms (10 mVrms at 130 MHz), 50 mVrms (130 to 250 MHz) AM band (high, low): 35 mVrms IF count: HCTR input pin: 0.4 to 12 MHz (HCTR can be switched to function as a general-purpose input port.) SANYO: SQFP64 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 12503RM (OT) No. 7275-1/13 LC723461W, 723462W Continued from preceding page. • External reset input: During CPU and PLL operations, instruction execution is started from location 0. • Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied. • Halt mode: The controller-operating clock is stopped. • Backup mode: The crystal oscillator is stopped. • Static power-on function: Backup state is cleared with the PF port • Beep tone: 1.5 and 3.1 kHz • Built-in DC-DC converter: For LCD and A/D converter use (3 V) • • • • • Can also be used for TU + B creation by using a secondary coil. (The DC-DC converter voltage step-up operation can be stopped with the DCDCC instruction.) Built-in remaining battery life verification function: Converts the VDD pin level through AD converter. Memory retention voltage: 0.5 V or higher Dedicated memory power supply: The RAM retention time has been increased by the provision of a dedicated memory power supply. Package: SQFP-64 (0.5-mm pitch) VDD power supply: 0.9 to 1.8 V XIN TEST1 EO VSS AM IN FMIN VDD HCTR /PM0 BRES COMC COM1 COM2 COM3 COM4 S1 S2 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 4 I 46 I 45 5 44 6 43 7 8 O 9 10 11 12 42 LC723461W/3462W SQFP-64 15 40 39 38 I/O I/O 13 14 41 I/O O 37 36 35 I I/O I/O 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13/PH 0 S14/PH 1 S15/PH 2 S16/PH 3 S17/PG0 S18/PG1 INT0/PD0 DAC/PD1 BEEP/PE0 ADI3/PF2 ADI1/PF1 ADI0/PF0 SI1/PK3 SI0/PK2 SCK1/PK1 VREF VSS VDDRAM VDC3 VDC1 S20/PG3 S19/PG2 XOUT PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 PD3 PD2 IN T1/P D *: The VDD pin can also function as ADI2 A/D converter input. No. 7275-2/13 LC723461W, 723462W Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings Unit VDD1 max VDD –0.3 to +3.0 V VDD2 max VDDRAM –0.3 to +4.0 V VDD3 max VDC3 VIN1 Input voltage VIN2 Output voltage Output current Allowable power dissipation –0.3 to +4.0 V FMIN, AMIN –0.3 to VDD1 +0.3 V PA, PC, PD, PF, PK, PG, PH, BRES –0.3 to VDD1 +0.3 V –0.3 to +7 V VOUT1 PE VOUT2 PB, PC, PD, PG, PH –0.3 to VDD1 +0.3 V VOUT3 VDC1, EO –0.3 to VDD4 +0.3 V VOUT4 COM1 to COM4, S1 to S20 –0.3 to VDD4 +0.3 IOUT1 PC, PD, PG, PH, EO 0 to 3 mA V IOUT2 PB 0 to 1 mA IOUT3 PE 0 to 2 mA IOUT4 S1 to S20 IOUT5 COM1 to COM4 Pdmax Ta = –10 to +60°C 300 µA 3 mA 100 mW Operating temperature Topr –10 to +60 °C Storage temperature Tstg –45 to +125 °C Allowable Operating Ranges at Ta = –10 to +60°C, VDD = 0.9 to 1.8 V Parameter Symbol Supply voltage VREF input voltage Input high-level voltage Input low-level voltage Input amplitude Input voltage range Input frequency Conditions Ratings min typ max VDD1 Voltage applied to the VDD pin 0.9 1.3 1.8 VDD2 Voltage applied to the VDDRAM pin 2.7 3.0 3.3 VDD3 Voltage applied to the VDC3 pin (See note.) VDD4 Memory retention voltage VREF1 The voltage input to the VREF pin (See note.) 2.7 Unit V 0.5 0.66 V VIH1 Ports PC, PD, PG, PH, and PK 0.7 VDD1 VDD1 V VIH2 Port PA 0.8 VDD1 VDD1 V VIH3 Port PF 0.8 VDD1 VDD1 V VIH4 Port BRES 0.6 VDD1 VDD1 V VIL1 Ports PC, PD, PG, PH, and PK 0 0.3 VDD1 V VIL2 Port PA 0 0.2 VDD1 V VIL3 Port PF 0 0.2 VDD1 V VIL4 Port BRES 0 0.2 VDD1 VIN1 XIN 0.5 0.6 Vrms VIN2 FMIN, AMIN: VDD1 = 0.9 to 1.8 V 0.035 0.35 Vrms VIN3 FMIN: VDD1 = 0.9 to 1.8 V 0.05 0.35 Vrms VIN4 ADI0, ADI1, VDD, ADI3 0.035 0.35 Vrms VIN4 ADI0, ADI1, ADI3, VDD1 FIN1 XIN: CI ≤ 35 kΩ 0 70 VDD3 75 V V 80 kHz MHz FIN2 FMIN: VIN2, VDD1 = 0.9 to 1.8 V 10 130 FIN3 FMIN: VIN3, VDD1 = 0.9 to 1.8 V 130 250 MHz FIN4 AMIN(L): VIN2, VDD1 = 0.9 to 1.8 V 2 20 MHz FIN5 AMIN(H): VIN2, VDD1 = 0.9 to 1.8 V 0.5 10 MHz FIN6 HCTR: VIN4, VDD1 = 0.9 to 1.8 V 0.4 12 MHz Note: VDD3 R = 240 kΩ VREF When 0.66 V DZD2.0X No. 7275-3/13 LC723461W, 723462W Electrical Characteristics within allowable operating conditions Parameter Input high-level current Input low-level current Input floating voltage Pull-down resistor values Hysteresis Symbol Conditions IIH1 XIN: VDD1 = 1.3 V IIH2 FMIN, AMIN, HCTR: VDD1 = 1.3 V IIH3 Output off leakage current VDC3 current Unit max 3 3 µA 4 µA IIH4 PA (without pull-down resistors), the PC, PD, PG, and PH ports, and BRES, PK: VDD1 = 1.3 V 3 µA IIL1 XIN: VDD1 = VSS –3 µA IIL2 FMIN, AMIN, HCTR: VDD1 = VSS IIL3 –20 µA Port PF: VDD1 = VSS –4 µA IIL4 PA (without pull-down resistors), the PC, PD, PG, and PH ports, and BRES, PK: VDD1 = VSS –3 µA VIF PA (with pull-down resistors) RPD1 PA (with pull-down resistors), VDD1 = 1.3 V RPD2 TEST1 (with pull-down resistor), VDD1 = 1.3 V VH BRES –3 8 µA Port PF: VDD1 = 1.3 V –8 0.05 VDD1 75 100 200 10 0.1 VDD1 kΩ 0.2 VDD1 VDD1 – 0.7 VDD V kΩ V VDD1 – 0.3 VDD V VOH1 PB: IO = 1 mA VOH2 PC, PD, PG and PH: IO = 1 mA VDD1 – 0.3 VDD1 V VOH3 EO: IO = 500 µA VDD3 – 0.3 VDD3 V VOH4 XOUT: IO = 200 µA VDD1 – 0.3 VDD1 V VOH5 S1 to S20: IO = 20 µA VDD3 –1 V VOH6 COM1, COM2, COM3, COM4: IO = 100 µA VDD3 –1 V VOH7 VDC1: IO = 1 mA VDD3 –1 VOL1 PB: IO = –50 µA 0.3 VDD1 VOL2 VOL3 V 0.7 VDD1 V PC, PD, PG, PH: IO = –1 mA 0.3 VDD1 V EO: IO = –500 µA 0.3 VDD3 V VOL4 XOUT: IO = –200 µA 0.3 VDD1 V VOL5 S1 to S20: IO = –20 µA VDD3 –2 V VOL6 COM1, COM2, COM3, COM4: IO = –100 µA VDD3 –2 V 0.6 VDD1 V VOL7 PE: IO = 2 mA VOL8 VDC1: IO = 1 mA IOFF1 Ports PB, PC, PD, PG and EO IOFF2 Port PE A/D converter error Current drain typ 20 Output high-level voltage Output low-level voltage Ratings min 1 V –3 +3 µA nA –100 +100 When the reference voltage is 2.7 V: ADI0, ADI1, VDD1, ADI3. Ta = 25°C –1 +1 LSB When the reference voltage is 2.0 V: ADI0, ADI1, VDD1, ADI3. Ta = 25°C Note: Linearity is maintained in the converted data. –1 +1 LSB IDD1 VDD1 = 1.3 V: FIN2 130 MHz, Ta = 25°C IDD3 VDD1 = 1.3 V: In HALT mode, Ta = 25°C *1 IDD4 VDD1 = 1.8 V, with the oscillator stopped, Ta = 25°C *2 IDC31 Vdd3 = 2.7 V: Halt mode, Ta = 25°C 2 mA 0.1 mA 1 µA 100 µA Note*: The halt mode current drain is due to 20 instructions being executed every 125 ms. No. 7275-4/13 LC723461W, 723462W *1. Halt and PLL STOP mode current test circuit 7 pF A *2. Backup mode current test circuit 7 pF 75 kHz 75 kHz XOUT XOUT VDD RES XIN 7 pF A XIN 7 pF PA, PF VDC3 VDC3 VSS FMIN AMIN HCTR VDD RES COMC TEST1 With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected. Enter halt mode by software command. The state where CPU operation is stopped with the crystal oscillator unstopped. VSS FMIN AMIN HCTR 3V COMC TEST1 With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected. Enter backup mode by software command. The state where the crystal oscillator is stopped. No. 7275-5/13 LC723461W, 723462W Block Diagram DIVIDER XIN REFERENCE DIVIDER PHASE DETECTOR SYSTEM CLOCK GENERATOR XOUT 1/2 FMIN 1/16,1/17 EO PROGRAMMBLE DIVIDER AMIN 1/2 1/8 VSS PLL DATA LATCH PLL CONTROL S1 LCDA/B VDC3 VADJ VDC1 HCTR RES 1/2 SCK1/PK1 SO1/PK2 SI1/PK3 S12 RAM 256×4bits (LC723461) 512×4bits (LC723462) PA0 PA1 PA2 PA3 INT0/PD0 INT1/PD1 PD2 PD3 LCPA/B P-ON RESET TEST1 PC0 PC1 PC2 PC3 UNIVERSAL COUNTER (20bits) * COMC PB0 PB1 PB2 PB3 LCD 80 PORT DRIVER SEG 4 LA 7 Clock Control BUS DRIVER * DATA LATCH / ADDRESS DECODER DATA LATCH BANK BUS DRIVER ROM 4k×16bits (LC723461) 6K×16bits (LC723462) 14 BUS DRIVER ADDRESS COUNTER DATA LATCH STACK 14 S17/PG0 S18/PG1 S19/PG2 S20/PG3 DATA LATCH / BUS DRIVER INSTRUCTION DECODER SKIP ADDRESS DECODER / / BUS CONTROL BUS DRIVER DATA LATCH S13/PH0 S14/PH1 S15/PH2 S16/PH3 JMP CAL RETURN INTERRUPT RESET BANK CF BEEP TONE / BUS DRIVER DATA LATCH SIO / BUS DRIVER ALU / BUS DRIVER JUDGE LATCH A DATA LATCH PE0/BEEP MPX MPX PE1/DAC DAC LATCH B VDD MPX TIMER 0 MPX (6bits) DATA LATCH / DATA BUS BUS DRIVER PF0/ADI0 PF1/ADI1 PF2/ADI3 No. 7275-6/13 LC723461W, 723462W Pin Functions Pin No. Pin I/O Function 64 XIN I 1 XOUT O 63 TEST1 I IC testing. This pin must be connected to ground. I Special-purpose ports for key return signal input designed with a low threshold voltage. When a key matrix is formed in combination with port PB, simultaneous multiple key presses with up to 3 keys can be detected. The pull-down resistors are set up for all four pins at the same time with the IOS instruction. This setting cannot be specified for individual pins. In backup mode, these pins go to the input disabled state, and the pull-down resistors are disabled after a reset. 5 PA0 4 PA1 3 PA2 2 PA3 I/O circuit 75 kHz oscillator connections — Input with built-in pull-down resistor Unbalanced CMOS push-pull 9 PB0 8 PB1 7 PB2 6 PB3 O Unbalanced CMOS outputs. Since these outputs are unbalanced, no diodes are required to prevent short circuits due to simultaneous multiple key presses. These outputs go to the high-impedance output state in backup mode. After a reset, they go to the high-impedance output state and remain in that state until an output instruction (OUT, SPB, or RPB) is executed. CMOS push-pull/ N-ch open-drain 13 PC0 12 PC1 11 PC2 18 PC3 17 INT1/PD0 PD0, PD1 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5) is used for switching the general-purpose I/O port function, and these ports can be set to input or output in 1-bit units. (0: input, 1: output) 16 INT0/PD1 In backup mode they go to the input disabled high-impedance state. 15 PD2 After a reset, they switch to the general-purpose input port function. 14 PD3 19 BEEP/PE0 18 DAC/PE1 General-purpose I/O ports. Note that there is a mask option that allows these pins to be used as n-channel open drain ports. I/O O General-purpose output ports. Note that PE0 has a shared function as the BEEP output, and that PE1 has a shared function as a D/A converter output port. Since these ports are open drain ports, a resistor must be inserted between each port and VDD. At reset, they are set to the general-purpose output port function .The BEEP instruction is used to switch the BEEP/PE0 port between the general-purpose output port and the BEEP output functions. A BEEP instruction with b2 = 0 will set the BEEP/PE0 port to function as a general-purpose output port. If b2 is set to 1, the instruction will select the BEEP output function. Bits b0 and b1 switch the frequency of the BEEP output. This IC supports two BEEP frequencies. N-ch open-drain *: When the PE0 port is set to function as the BEEP output, executing an output instruction for PE0 will only change the value of the internal output latch; it will have no effect on the output. The DAC instruction is used to switch the DAC/PE1 port between the general-purpose output port and DAC output functions. These ports go to the high-impedance state in backup mode. That state is maintained until an output instruction, a BEEP instruction, or a DAC instruction is executed. 25 SCK1/PK1 24 SO1/PK2 23 SI1/PK3 I/O Shared function pins used as either general-purpose I/O ports or a serial I/O port. Note that there is a mask option that allows these pins to be used as n-channel open drain ports. When used as general-purpose I/O ports, the I/O direction can be switched in single pin units with the IOS instruction. The IOS instruction is used to switch the function between the general-purpose I/O port and the serial I/O port function. CMOS push-pull/ N-ch open-drain In backup mode, these pins go to the input disabled high-impedance state. After a reset, the general-purpose input port function is selected. Continued on next page. No. 7275-7/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin 22 PF0/ADI0 21 PF1/ADI1 20 PF2/ADI3 I/O I Function I/O circuit General-purpose input and A/D converter input shared function ports. The IOS instruction is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched in a units, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. CMOS input/analog input *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 8-bit successive approximation type converter, and features a conversion time of 0.64 ms. Note that the full-scale A/D converter voltage (FFH) is VDC3/2.0 V. LCD driver segment output and general-purpose I/O shared function ports. CMOS push-pull The IOS instruction is used for switching between the segment output and generalpurpose I/O functions and between input and output for the general-purpose I/O port function. 31 PG3/S20 32 PG2/S19 33 PG1/S18 34 PG0/S17 O 35 PH3/S16 36 PH2/S15 37 PH1/S14 38 PH0/S13 • When used as segment output ports The segment output port is selected with the IOS instruction (Pwn = 8). b0 to b3 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3) The segment output port is selected with the IOS instruction (Pwn = 9). b0 to b3 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3) • When used as general-purpose I/O ports The IOS instruction is used to select input or output. Note that the mode can be set in a bit units. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3 0: Input 1: Output Note that there is a mask option that allows these pins to be used as n-channel open drain ports. *2 In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. Although the general-purpose port/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function. CMOS push-pull LCD driver segment output pins. 39 to 50 A 1/4-duty 1/2-bias drive technique is used. S12 to S1 O The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level. 51 COM4 52 COM3 53 COM2 54 COM1 LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. O The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level. Continued on next page. No. 7275-8/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin I/O Function I/O circuit System reset input. 56 RES I In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. 28 VDDRAMVADJ I RAM backup power supply. Connected to the VDC3 voltage through a diode. 30 VDC1 O Output for the 3 V step-up circuit clock. Outputs 1/2 the AM local oscillator frequency in AM reception mode, and 1/256 the FM local oscillator or 75 kHz in FM reception mode. 29 VDC3 I Voltage stepped up by the DC-DC converter (3 V) May also be used to input an equivalent voltage. VDC3 reference voltage input. 26 VREF I When 0.7 V is input, the VDC3 voltage will be 3 V. The VDC3 sample-to-sample variations can be held to ±3% by attaching an external metal-film resistor and a zener diode. LCD driver intermediate potential output. 55 COMC O The COM waveform must be stabilized by attaching an external capacitor of about 0.1 µF. CMOS amplifier input FM VCO (local oscillator) input. 59 FMIN I This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. AM VCO (local oscillator) input. CMOS amplifier input This pin and the bandwidth are selected with the PLL instruction CW1. 60 AMIN I CW1 b1, b0 1 1 Input pins Bandwidth FMIN (L) 0.5 to 10 MHz (MW, LW) The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. General-purpose input and universal counter input shared-function port. The IOS instruction is used to switch between the general-purpose input port and the universal counter input functions. • When performing frequency measurements, select the HCTR frequency measurement mode and the measurement time with the UCS instruction (b3 = 0, b2 = 0), and start the count with the UCC instruction. UCS b3, b2 57 HCTR I Input pins Measurement mode 0 0 HCTR Frequency measurement 0 1 — 1 0 — UCS b1, b0 CMOS amplifier input Measurement time 0 0 1 ms 0 1 4 ms 1 0 8 ms 1 1 32 ms The CNTEND flag is set when the count completes. Since this circuit operates as an AC amplifier in this mode, the input signal must be capacitor coupled. When used as a general-purpose input, the input data is acquired with the INR instruction. Input is disabled in backup mode, halt mode, during a reset, and in PLL stop mode. Note that after a reset, the universal counter input port function will be selected. Continued on next page. No. 7275-9/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin I/O Function I/O circuit CMOS push-pull 62 EO O Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output,and the pin is set to the high-impedance state when the frequencies match. This output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode. 61 VSS 27 VSS 58 VDD Power supply pin. — This pin must be connected to ground. This pin must be connected to ground. — This pin must be connected to VDD. Supports A/D converter. Note*: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up output mode with an IOS instruction. No. 7275-10/13 LC723461W, 723462W LC723461W/723462W Series Instruction Set Terminology Instruction group ADDR b C DH DL I M N Rn Pn PW r ( ), [ ] M (DH, DL) Mnemonic Subtraction instructions Addition instructions AD Operand 1st 2nd r M Function Add M to r Operations function r ← (r) + (M) Instruction format f e d c b a 0 1 0 0 0 0 9 8 DH 7 6 5 DL 4 3 2 1 0 r ADS r M Add M to r, then skip if carry r ← (r) + (M), skip if carry 0 1 0 0 0 1 DH DL r AC r M Add M to r with carry r ← (r) + (M) + C 0 1 0 0 1 0 DH DL r ACS r M Add M to r with carry, then skip if carry r ← (r) + (M) + C skip if carry 0 1 0 0 1 1 DH DL r AI M I Add I to M M ← (M) + I 0 1 0 1 0 0 DH DL I AIS M I Add I to M, then skip if carry M ← (M) + I, skip if carry 0 1 0 1 0 1 DH DL I AIC M I Add I to M with carry M ← (M) + I + C 0 1 0 1 1 0 DH DL I Add I to M with carry, then skip if carry M ← (M) + I + C, skip if carry 0 1 0 1 1 1 DH DL I AICS M I SU r M Subtract M from r r ← (r) – (M) 0 1 1 0 0 0 DH DL r Subtract M from r, then skip if borrow r ← (r) – (M), skip if borrow 0 1 1 0 0 1 DH DL r SUS r M SB r M Subtract M from r with borrow r ← (r) – (M) – b 0 1 1 0 1 0 DH DL r r ← (r) – (M) – b, skip if borrow SBS r M Subtract M from r with borrow, then skip if borrow 0 1 1 0 1 1 DH DL r SI M I Subtract I from M M ← (M) – I 0 1 1 1 0 0 DH DL I Subtract I from M, then skip if borrow M ← (M) – I, skip if borrow 0 1 1 1 0 1 DH DL I SIS M I SIB M I Subtract I from M with borrow M ← (M) – I – b 0 1 1 1 1 0 DH DL I M I Subtract I from M with borrow, then skip if borrow M ← (M) – I – b, skip if borrow 0 1 1 1 1 1 DH DL I SIBS Comparison instructions : Program memory address : Borrow : Carry : Data memory address High (Row address) [2 bits] : Data memory address Low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Resister number [4 bits] : Port number [4 bits] : Port control word number [4 bits] : General register (One of the addresses from 00H to 0FH of BANK0) : Contents of register or memory : Data memory specified by DH, DL SEQ r M Skip if r equal to M (r) – (M), skip if zero 0 0 0 1 0 0 DH DL r SEQI M I Skip if M equal to I (M) – I, skip if zero 0 0 0 1 1 0 DH DL I SNEI M I Skip if M not equal to I (M) – I, skip if not zero 0 0 0 0 0 1 DH DL I (r) – (M), skip if not borrow 0 0 0 1 1 0 DH DL r SGE r M Skip if r is greater than or equal to M SGEI M I Skip if M is greater than equal to I (M) – I, skip if not borrow 0 0 0 1 1 1 DH DL I SLEI M I Skip if M is less than I (M) – I, skip if borrow 0 0 0 0 1 1 DH DL I Continued on next page. No. 7275-11/13 LC723461W, 723462W Hardware control instructions Status register instructions Jump and subroutine call instructions Bit test instructions Transfer instructions Logic operation instructions Instruction group Continued from preceding page. Mnemonic Operand 1st 2nd AND r M ANDI M I OR r M Instruction format f e d c b a r ← (r) AND (M) 0 0 1 0 0 0 DH DL AND I with M M ← (M) AND I 0 0 1 0 0 1 DH DL I OR M with r r ← (r) OR (M) 0 0 1 0 1 0 DH DL r AND M with r 9 8 7 6 5 4 3 2 1 M I OR I with M M ← (M) OR I 0 0 1 0 1 1 DH DL I r M Exclusive OR M with r r ← (r) XOR (M) 0 0 1 1 0 0 DH DL r EXLI M I Exclusive OR M with M M ← (M) XOR I 0 0 1 1 1 0 DH DL I 0 0 0 0 0 0 SHR r carry (r) Shift r right with carry 0 0 1 1 1 0 r LD r M Load M to r r ← (M) 1 1 0 1 0 0 DH DL r ST M r Store r to M M ← (r) 1 1 0 1 0 1 DH DL r MVRD r M Move M to destination M referring to r in the same row [DH, Rn] ← (M) 1 1 0 1 1 0 DH DL r MVRS M r Move source M referring to r to M in the same row M ← [DH, Rn] 1 1 0 1 1 1 DH DL r MVSR M1 M2 Move M to M in the same row [DH, DL1] ← [DH, DL2] 1 1 1 0 0 0 DH DL1 DL2 MVI M I Move I to M M←I 1 1 1 0 0 1 DH DL I if M (N) = all 1, then skip 1 1 1 1 0 0 DH DL N if M (N) = all 0, then skip 1 1 1 1 0 1 DH DL N Jump to the address PC ← ADDR 1 0 0 ADDR (13 bits) Call subroutine PC ← ADDR Stack ← (PC) + 1 1 0 1 ADDR (13 bits) Return from subroutine PC ← Stack 0 0 0 0 0 0 0 0 1 0 0 0 Return from interrupt PC ← Stack, BANK ← Stack, CARRY ← Stack 0 0 0 0 0 0 0 0 1 0 0 1 TMT M N Test M bits, then skip if all bits specified are true TMF M N Test M bits, then skip if all bits specified are false JMP CAL ADDR ADDR RT RTI SS SWR N Set status register (Status W-reg) N ← 1 1 1 1 1 1 1 1 1 0 0 0 SWR N RS SWR N Reset status register (Status W-reg) N ← 0 1 1 1 1 1 1 1 1 0 0 1 SWR N 1 1 1 1 1 1 1 0 1 SRR N TST SRR N Test status register true If (Status R-reg) N = all 1, 1 then skip TSF SRR N Test status register false If (Status R-reg) N = all 0, 1 then skip 1 1 1 1 1 1 1 1 0 SRR N TUL N Test Unlock F/F If Unlock F/F (N) = All 0, then skip 0 0 0 0 0 0 0 1 1 0 N Load M to PLL register PLL reg ← PLL data 1 1 1 1 1 0 SIO reg ← I1, I2 0 0 0 0 0 0 0 1 PLL M SIO I1 0 DH 1 DL r I1 I2 UCS I Set I to UCCW1 UCCW1 ← I 0 0 0 0 0 0 0 0 0 0 0 1 I UCC I Set I to UCCW2 UCCW2 ← I 0 0 0 0 0 0 0 0 0 0 1 0 I BEEP I Beep control BEEP reg ← I 0 0 0 0 0 0 0 0 0 1 1 0 I DZC I Dead zone control DZC reg ← I 0 0 0 0 0 0 0 0 1 0 1 1 I TMS I Set timer register Timer reg ← I 0 0 0 0 0 0 0 0 1 1 0 0 N Set port control word IOS reg PWn ← N 1 1 1 1 1 1 1 0 DA converter control DAC reg ← DAC data 0 0 0 0 0 0 0 0 Pn Input port data to M M ← (Pn) 1 1 1 0 1 0 DH DL Pn IOS PWn I M PWn 0 0 1 I N 1 I OUT M Pn Output contents of M to port P1n ← M 1 1 1 0 1 1 DH DL Pn INR M Pn Input register/port data to M M ← (Pn) 0 0 1 1 1 0 DH DL Pn SPB P1n N Set port1 bits (Pn)N ← 1 0 0 0 0 0 0 1 0 Pn N RPB P1n N Reset port1 bits (Pn)N ← 0 0 0 0 0 0 0 1 1 Pn N 1 1 1 1 1 1 0 0 Pn N 1 1 1 1 1 1 0 1 Pn N 0 0 0 0 0 0 0 0 TPT P1n N Test port1 bits, then skip if all bits If (Pn)N = all 1, then skip specified are true TPF P1n N Test port1 bits, then skip if all bits If (Pn)N = all 0, then skip specified are false BANK I Select Bank BANK ← I 0 1 0 r ORI IN I/O instructions Operations function EXL DAC Bank switching instructions Function 1 1 I Continued on next page. No. 7275-12/13 LC723461W, 723462W Other instructions LCD instructions Instruction group Continued from preceding page. Mnemonic Operand 1st 2nd LCDA M I LCDB M I LCPA M I LCPB M I Function Output segment pattern to LCD digit direct Output segment pattern to LCD digit through LA ADCHG I AD converter reference voltage change DCDCC I DC/DC clock control HALT I CKSTP NOP Operations function LCD (DIGIT) ← M LCD (DIGIT) ← LA ← M Instruction format f e d c b a 1 1 0 0 0 0 9 DH 8 7 6 DL 5 4 3 DIGIT 2 1 1 1 0 0 0 1 DH DL DIGIT 1 1 0 0 1 0 DH DL DIGIT 1 1 0 0 1 1 DH DL DIGIT 1 1 1 1 1 1 1 1 1 1 1 0 I 0 0 0 0 0 0 0 0 1 1 1 1 I Halt mode control HALT reg ← I, then CPU clock stop 0 0 0 0 0 0 0 0 0 1 0 0 I Clock stop Stop x’tal OSC 0 0 0 0 0 0 0 0 0 1 0 1 No operation No operation 0 0 0 0 0 0 0 0 0 0 0 0 0 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2003. Specifications and information herein are subject to change without notice. PS No. 7275-13/13