Ordering number : EN5065A CMOS LSI LC72358N, 72362N, 72366 Single-Chip PLL Microcontrollers Overview The LC72358N, LC72362N, and LC72366 are 1.33 µs instruction execution time single-chip microcontrollers for electronic tuning applications. These products incorporate a high-speed locking circuit and a high-performance direct PLL circuit that can control the local oscillator C/N characteristics. These products have 256 or 512 bytes of RAM and 16K, 24K or 32K bytes of program ROM on chip, and incorporate a three-channel serial I/O interface, a six-channel A/D converter and other interfaces. • • Features • ROM — LC72358N: 8K steps (8191 × 16 bits) — LC72362N: 12K steps (12287 × 16 bits) — LC72366: 16K steps (16383 × 16 bits) The subroutine area in both products is 4K steps (4095 × 16 bits). • RAM — LC72358N, 72362N: 512 × 4 bits (banks 0 to 7) — LC72366: 1K × 4 bits (banks 0 to F) • Stack: Eight levels • Serial I/O: Three channels (8-bit 3-wire format) There are three internal serial clocks: 12.5 kHz, 37.5 kHz and 187.5 kHz. • External interrupts: Two channels (the INT0 and INT1 pins) Switching between rising and falling edge detection is supported. • Internal interrupts: Three channels — Two internal timer interrupt channels The timers provide eight interrupt periods: 100 µs, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms and 250 ms. — One serial I/O interrupt channel • Multiple interrupt levels: Four levels Hardware priority order INT0 pin > INT1 pin > SI/O pin > internal timer 0 > internal timer 1 • A/D converter: Six channels (6-bit successive approximation type) • General-purpose ports — Input ports: 10 • • • • • • • • • — Output ports: 28 — I/O ports: 25 (These pins can be switched between input and output in bit units.) PLL block — Built-in sub-charge pump for high-speed locking — Support for dead zone control — Built-in unlock detection circuit — Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9, 10, 12.5, 25, 30, 50 and 100 kHz Universal counter: 20 bits Supports frequency and period measurement with counting periods of 1, 4, 8 and 32 ms. Timers: Timer interrupt periods 100 µs, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms and 250 ms Beep: Six frequencies: 2.08 kHz, 2.25 kHz, 2.5 kHz, 3.0 kHz, 3.75 kHz, 4.17 kHz. Reset: Built-in voltage detection type reset circuit Cycle time: 1.33 µs (all instructions execute in one cycle) Halt mode: The microcontroller operating clock is stopped in halt mode. There are four types of event that clear halt mode: interrupt requests, timer FF overflows, key inputs, and hold pin inputs. Operating supply voltage: 4.5 to 5.5 V (3.5 to 5.5 V when only the controller block operates) Package: QFP80E (QIP80E) OTP version: LC72P366 Development tools: Emulator .................RE32N Evaluation chip.......LC72EV350 Evaluation chip board ................................EB-72EV350 This LSI can easily use CCB that is SANYO’s original bus format. • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63096HA (OT)/62295TH (OT) No. 5065-1/13 LC72358N, 72362N, 72366 Package Dimensions unit: mm 3174-QFP80E [LC72358N, 72362N, 72366] SANYO: QIP80E Pin Assignment No. 5065-2/13 LC72358N, 72362N, 72366 Block Diagram No. 5065-3/13 LC72358N, 72362N, 72366 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings VDD max Input voltage VIN All input pins Unit –0.3 to +6.5 V –0.3 to VDD + 0.3 V –0.3 to +15 V VOUT (1) J port VOUT (2) All output ports other than VOUT (1) IOUT (1) J port 0 to 5 mA Output current IOUT (2) D, E, F, G, K, L, M, N, O, P and Q ports, EO1, EO2, EO3, SUBPD 0 to 3 mA IOUT (3) B and C ports 0 to 1 mA Allowable power dissipation Pd max Ta = –40 to +85°C 400 mW Output voltage –0.3 to VDD + 0.3 V Operating temperature Topr –40 to +85 °C Storage temperature Tstg –45 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VDD = 3.5 to 5.5 V Parameter Supply voltage Input high level voltage Input low level voltage Input frequency Input amplitude Input voltage range Symbol Conditions min typ VDD (1) CPU and PLL operating 4.5 VDD (2) CPU operating VDD (3) Memory retention 5.0 max Unit 5.5 V 3.5 5.5 V 1.3 5.5 V VIH (1) E, H, I, L, M and Q ports, HCTR and LCTR (when selected for input) 0.7 VDD VDD V VIH (2) F, G and K ports, LCTR (period measurement mode), HOLD 0.8 VDD VDD V VIH (3) SNS VIH (4) A port 2.5 VDD V 0.6 VDD VDD V VIL (1) E, H, I, L, M and Q ports, HCTR and LCTR (when selected for input) 0 0.3 VDD V VIL (2) A, F, G and K ports, LCTR (period measurement mode) 0 0.2 VDD V VIL (3) SNS 0 1.3 V VIL (4) HOLD fIN (1) XIN 4.0 fIN (2) FMIN: VIN (2), VDD (1) fIN (3) FMIN: VIN (3), VDD (1) fIN (4) 0 0.4 VDD 4.5 V 5.0 MHz 10 150 MHz 10 130 MHz AMIN (H): VIN (3), VDD (1) 2.0 40 MHz fIN (5) AMIN (L): VIN (3), VDD (1) 0.5 10 MHz fIN (6) HCTR: VIN (3), VDD (1) 0.4 12 MHz fIN (7) LCTR: VIN (3), VDD (1) 100 500 kHz fIN (8) LCTR (period measurement): VIH (2), VIL (2), VDD (1) 1 20 × 103 VIN (1) XIN 0.5 1.5 Vrms VIN (2) FMIN 0.10 1.5 Vrms VIN (3) FMIN, AMIN, HCTR, LCTR 0.07 1.5 Vrms VIN (4) ADI0 to ADI5 0 VDD V Hz No. 5065-4/13 LC72358N, 72362N, 72366 Electrical Characteristics for the Allowable Operating Ranges Parameter Input high level current Symbol µA IIH (2) FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V 4.0 10 30 µA IIH (3) A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD, HCTR, LCTR, with no pull-down resistor on A port. VI = VDD = 5.0 V, with the E, F, G, K, L, M and Q ports selected for input. 3.0 µA IIH (4) A port: pull-down resistor present, VI = VDD = 5.0 V IIL (1) XIN: VI = VSS 2.0 5.0 15 µA IIL (2) FMIN, AMIN, HCTR, LCTR: VI = VSS 4.0 10 30 µA IIL (3) A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD, HCTR, LCTR, with no pull-down resistor on A port. VI = VSS, with the E, F, G, K, L, M and Q ports selected for input. 3.0 µA VIF VH A port: pull-down resistor present µA 0.05 VDD A port: pull-down resistor present, VDD = 5 V 100 V 200 kΩ 0.1 VDD 0.2 VDD V VDD – 2.0 VDD – 1.0 V VOH (2) D, E, F, G, K, L, M, N, O, P and Q ports: IO = –1 mA VDD – 1.0 V VOH (3) EO1, EO2, EO3, SUBPD: IO = –500 µA VDD – 1.0 V VOH (4) XOUT: IO = –200 µA VDD – 1.0 VOL (1) B and C ports: IO = 50 µA VOL (2) D, E, F, G, K, L, M, N, O, P and Q ports: IO = 1 mA 1.0 V VOL (3) EO1, EO2, EO3, SUBPD: IO = 500 µA 1.0 V VOL (4) XOUT: IO = 200 µA 1.5 V VOL (5) J port: IO = 5 mA 2.0 V IOFF (1) B, C, D, E, F, G, K, L, M, N, O, P and Q ports –3.0 +3.0 µA IOFF (2) EO1, EO2, EO3, SUBPD –100 +100 nA IOFF (3) J port –5.0 +5.0 µA ADI0 to ADI5: VDD (1) –1/2 +1/2 LSB PREJ Power-down detection voltage VDET F, G and K ports, LCTR (period measurement mode) 75 B and C ports: IO = –1 mA Reject pulse width Current drain 50 VOH (1) A/D conversion error Pull-down resistance Unit 15 RPD (1) Output off leakage current max 5.0 Input floating voltage Output low level voltage typ 2.0 Pull-down resistance Output high level voltage min XIN: VI = VDD = 5.0 V Input low level current Hysteresis Conditions IIH (1) V 1.0 SNS 2.0 V 50 2.7 RPD (2) TEST1, TEST2 IDD (1) VDD (1): fIN (2) = 130 MHz, Ta = 25°C IDD (2) VDD (2): Halt mode*, Ta = 25°C (Figure 1) IDD (3) IDD (4) 3.0 µs 3.3 V 10 kΩ 12 24 mA 0.45 (0.9) mA VDD = 5.5 V, oscillator stopped, Ta = 25°C (Figure 2) 5 µA VDD = 2.5 V, oscillator stopped, Ta = 25°C (Figure 2) 1 µA Note: Execute 20 STEP instructions every 1 ms. With the PLL, counters and other functions all stopped. ( ) Value: LC72366 Test Circuit Note: All of the pins PB to PG and PJ to PQ must be left open. Here, the pins PE to PG, PK to PM, and PQ are selected for output. Figure 1: IDD(2) in Halt Mode Note: All of the pins PA to PQ must be left open. Figure 2. IDD(3) and IDD(4) in Backup Mode No. 5065-5/13 LC72358N, 72362N, 72366 Pin Functions Pin No. Symbol 30 PA0 29 PA1 28 PA2 27 PA3 26 PB0 25 PB1 24 PB2 23 PB3 22 PC0 21 PC1 20 PC2 19 PC3 18 PD0 17 PD1 16 PD2 15 PD3 14 PE0 13 PE1/SCK2 12 PE2/SO2 11 PE3/SI2 10 PF0 9 PF1/SCK1 8 PF2/SO1 7 PF3/SI1 6 PG0 5 PG1/SCK0 4 PG2/SO0 3 PG3/SI0 I/O I Pull-down resistor included Input O Unbalanced CMOS push-pull Key source signal output-only ports. Since the output transistor circuit is an unbalanced CMOS structure, diodes to prevent shorting due to multiple key presses are not required. In clock stop mode, these pins go to the output high-impedance state. During the power-on reset, these pins go to the output high-impedance state and hold that state until an output instruction is executed. CMOS push-pull Output-only ports. In clock stop mode, these pins go to the output high-impedance state. During the power-on reset, these pins go to the output high-impedance state and hold that state until an output instruction is executed. CMOS push-pull General-purpose I/O port/serial I/O pin shared-function ports. The F and G port inputs are Schmitt inputs. The E ports is a normal input. The IOS instruction switches these ports between general-purpose I/O ports and serial I/O ports, and between input and output for general-purpose I/O ports. • When used as general-purpose I/O ports these pins: Can be set for input or output in bit units (bit I/O), and are set for use as general-purpose I/O ports by the IOS instruction with PWn = 0. b0 = SI/O 0 0 ...................general-purpose port b1 = SI/O 1 1 ...................SI/O port b2 = SI/O 2 are set for input or output by the IOS instruction in bit units. PE..............PWn = 4 0 ...................Input PF..............PWn = 5 1 ...................Output PG .............PWn = 6 • When used as serial I/O ports these pins: Are set for serial I/O port use by the IOS instruction with PWn = 0, and are accessed by reading and writing the serial I/O data buffer with the INR and OUTR instructions. Note: Pin setup states when used as serial I/O ports: PE0, PF0, PG0 ......General-purpose I/O PE1, PF1, PG1 ......SCK output in internal clock mode SCK input in external clock mode PE2, PF2, PG2......SO output PE3, PF3, PG3......SI input In clock stop mode, input is disabled and these pins go to the high-impedance state. During the power-on reset, these pins become general-purpose input ports. — Connections for a 4.5 MHz crystal oscillator CMOS tristate Main charge pump outputs These pins output a high level when the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, and a low level when that frequency is lower. These pins go to the high-impedance state when the frequencies match. These pins go to the high-impedance state when the HOLD pin is set low in the hold enable state. In clock stop mode, during the power-on reset and in the PLL stop state, these pins go to the high-impedance state. O I/O 1 XIN I XOUT O EO1 77 EO2 Function Key return signal input-only ports. The threshold voltage is set to a relatively low value. When a key matrix is formed in combination with the PB and PC ports, up to three simultaneous key presses can be detected. The pull-down resistors are set by the IOS instruction with PWn = 2 for all four pins at the same time and cannot be set on an individual pin basis. Input is disabled in clock stop mode. 80 78 I/O type O Continued on next page. No. 5065-6/13 LC72358N, 72362N, 72366 Continued from preceding page. Pin No. Symbol 76 VSS 73 VDD 31 VDD 75 FMIN I/O — I I/O type Function — Power supply connections Input FM VCO (local oscillator) input This pin is selected by the PLL instruction CW1 (b1, b0 are ignored). Capacitor coupling must be used for signal input. Input is disabled when the HOLD pin is set low in the hold enable state. Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state. AM VCO (local oscillator) input This pin is selected and the band set by the PLL instruction CW1 (b1, b0). 74 AMIN I Input b1 b0 1 0 2 to 40 MHz (SW) Band 1 1 0.5 to 10 MHz (MW, LW) Capacitor coupling must be used for signal input. Input is disabled when the HOLD pin is set low in the hold enable state. Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state. Sub-charge pump output This pin, in combination with the main charge pump, allows the construction of a highspeed locking circuit. The DZC instruction controls the sub-charge pump. 72 SUBPD O CMOS tristate b3 b2 0 0 High impedance Operation 0 1 Only operates in the unlocked state (450 kHz) 1 0 Only operates in the unlocked state (900 kHz) 1 1 Normal operation This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable state. This pin goes to the high-impedance state in clock stop mode, during the power-on reset, and in the PLL stop state. 71 EO3 O CMOS tristate Second PLL charge pump output This pin outputs a low level when the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, and a high level when that frequency is lower. This pin goes to the high-impedance state when the frequencies match. (Note that this pin’s output logic is the opposite of that of the EO1 and EO2 pins.) This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable state. This pin goes to the high-impedance state in clock stop mode, during the power-on reset, and in the PLL stop state. Continued on next page. No. 5065-7/13 LC72358N, 72362N, 72366 Continued from preceding page. Pin No. 70 69 68 Symbol HCTR LCTR SNS I/O I I I I/O type Function Input Universal counter/general-purpose input shared-function input port The IOS instruction b3 with PWn = 3 switches the pin function between universal counter input and general-purpose input. • Frequency measurement The universal counter function is selected by an IOS instruction with PWn = 3 and b3 = 0. HCTR frequency measurement mode is set up by a UCS instruction with b3 = 0 and b2 = 0, and counting is started with a UCC instruction after the count time is selected. The CNTEND flag is set when the count completes. To operate this circuit as an AC amplifier in this mode, the input must be capacitor coupled. • General-purpose input pin use The general-purpose input port function is selected by an IOS instruction with PWn = 3 and b3 = 1. An internal register (address: 0EH) input instruction INR (b0) is used to acquire data from this pin. Input is disabled in clock stop mode. (The input pin will be pulled down.) During the power-on reset, the universal counter function is selected. Input Universal counter (frequency and period measurement)/general-purpose input sharedfunction input port The IOS instruction b2 with PWn = 3 switches the pin function between universal counter input and general-purpose input. • Frequency measurement The universal counter function is selected by an IOS instruction with PWn = 3 and b2 = 0. LCTR frequency measurement mode is set up by a UCS instruction with b3 = 0 b2 = 1, and counting is started with a UCC instruction after the count time is selected. The CNTEND flag is set when the count completes. To operate this circuit as an AC amplifier in this mode, the input must be capacitor coupled. • Period measurement With the universal counter function selected, set up period measurement mode with a UCS instruction with b3 = 1 and b2 = 0, and start the count with a UCC instruction after selecting the count time. The CNTEND flag will be set when the count completes. In this mode, the signal must be input with DC coupling to turn off the bias feedback resistor. • General-purpose input pin use The general-purpose input port function is selected by an IOS instruction with PWn = 3, b2 = 1. An internal register (address: 0EH) input instruction INR (b1) is used to acquire data from this pin. Input is disabled in clock stop mode. (The input pin will be pulled down.) During the power-on reset, the universal counter function (in HCTR frequency measurement mode) is selected. Input Voltage sense/general-purpose input pin shared-function port This circuit is designed for a relatively low input threshold voltage. • Voltage sense pin usage This input pin is used to determine whether or not a power failure occurred after recovery from backup (clock stop) mode. An internal sense F/F is used for this determination. The sense F/F is tested with a TUL instruction (b2). • General-purpose input port usage When used as a general-purpose input port, the state is sensed by using a TUL instruction (b3). Since, unlike other input ports, input is not disabled in clock stop mode and during the power-on reset, special care is required with respect to through currents. Continued on next page. No. 5065-8/13 LC72358N, 72362N, 72366 Continued from preceding page. Pin No. 67 Symbol HOLD 66 PH0/ADI0 65 PH1/ADI1 64 PH2/ADI2 63 PH3/ADI3 62 PI0/ADI4 61 PI1/ADI5 60 PJ0 59 PJ1 58 PJ2 57 PJ3 56 PK0/INT0 55 PK1/INT1 54 PK2 53 PK3 52 to 45 PL0 to PL3 PM0 to PM3 I/O I/O type Function Input PLL control and clock stop mode control Setting this pin low in the hold enabled state disables input to the FMIN and AMIN pins and sets the EO pin to the high-impedance state. To enter clock stop mode, set the HOLDEN flag, set this pin low, and execute a CKSTP instruction. To clear clock stop mode, set this pin high. Input General-purpose input port/A/D converter shared-function pins The IOS instruction with PWn = 7 or 8 switches the pin function between general-purpose input ports and A/D converter inputs. • General-purpose input port usage Specify general-purpose input port usage with the IOS instruction with PWn = 7 or 8 in bit units. • A/D converter usage Specify A/D converter usage with the IOS instruction with PWn = 7 or 8 in bit units. Specify the pin to convert with the IOS instruction with PWn = 1. Start a conversion with the UCC instruction (b2). The ADCE flag will be set when the conversion competes. Note: Executing an input instruction for a port specified for ADI usage will always return low since input is disabled. These pins must be set up for general-purpose input port usage before an input instruction is executed. Input is disabled in clock stop mode. During the power-on reset, these pins go to the general-purpose input port function. N-channel open drain General-purpose output ports An external pull-up resistor is required since these pins are open-drain circuits. In clock stop mode, these pins go to the transistor off state (high level output). During the power-on reset, these pins are set up as general-purpose output ports and go to the transistor off state (high level output). I/O CMOS push-pull General-purpose I/O/external interrupt shared-function ports There is no instruction that switches the function of these ports between general-purpose ports and external interrupt ports. These pins function as external interrupt pins at the point that the external interrupt enable flag is set. • General-purpose I/O port usage These pins can be set for input or output in bit units (bit I/O). The IOS instruction is used to specify input or output in bit units. • External interrupt pin usage This function can be used by setting the external interrupt enable flags (INT0EN and INT1EN) in status register 2. The corresponding pin must be set up for input. To enable interrupt operation, the interrupt enable flag (INTEN) in status register 1 also must be set. The IOS instruction with PWn = 3, b1 = INT1, and b0 = INT0 is used to select rising or falling edge detection. In clock stop mode, input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. I/O CMOS push-pull General-purpose I/O ports The IOS instruction is used to specify input or output. In clock stop mode input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. I I O Continued on next page. No. 5065-9/13 LC72358N, 72362N, 72366 Continued from preceding page. Pin No. Symbol 44 PN0/BEEP 43 PN1 42 PN2 41 PN3 40 to 33 PO0 to PO3 PP0 to PP3 32 PQ0 79 TEST1 2 TEST2 I/O I/O type Function O CMOS push-pull General-purpose output port/BEEP tone shared-function output pins The BEEP instruction switches between the general-purpose output port and BEEP tone functions. • General-purpose output port usage The BEEP instruction with b3 = 0 sets up the general-purpose output port function. Pins PN1 to PN3 are general-purpose output-only pins. • BEEP output usage The BEEP instruction with b3 = 1 sets up BEEP output. The BEEP instruction bits b0, b1 and b2 sets the frequency. When set up as the BEEP port, executing an output instruction will set the internal latch data but has no influence on the output. These pins go to the output high-impedance state in clock stop mode. These pins go to the output high-impedance state during the power-on reset and hold that state until an output instruction is executed. O CMOS push-pull Output-only ports These pins go to the output high-impedance state in clock stop mode. These pins go to the output high-impedance state during the power-on reset and hold that state until an output instruction is executed. CMOS push-pull General-purpose I/O ports The IOS instruction is used to specify input or output. The OUTR and INR instructions are used for output and input. The bit set, reset and test instruction cannot be used. In clock stop mode input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. I/O LSI test pins These pins must be either left open or connected to ground. No. 5065-10/13 LC72358N, 72362N, 72366 LC72358N, LC72362N and LC72366 Instruction Table Instruction Group Abbreviations: ADDR: Program memory address b: Borrow C: Carry DH: Data memory address high (row address): 2 bits DL: Data memory address low (column address):4 bits I: Immediate data:4 bits M: Data memory address N: Bit position Pn: Port number:4 bits PWn: Port control word number: 4 bits r: General register (one of banks 00 to 0FH) Rn: Register number:4 bits ( ): Contents of register or memory ( )N: Contents of bit N of register or memory Operand Subtraction instructions Addition instructions AD Comparison instructions Machine code Mnemonic Function Operation 1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 r M Add M to r r ← (r) + (M) 0 1 0 0 0 0 r ← (r) + (M) skip if carry DH DL r 0 1 0 0 0 1 DH DL r ADS r M Add M to r, then skip if carry AC r M Add M to r with carry r ← (r) + (M) + C 0 1 0 0 1 0 DH DL r Add M to r with carry, then skip if carry r ← (r) + (M) + C skip if carry 0 1 0 0 1 1 DH DL r ACS r M AI M I Add I to M M ← (M) + I 0 1 0 1 0 0 DH DL I Add I to M, then skip if carry M ← (M) + I skip if carry 0 1 0 1 0 1 DH DL I AIS M I AIC M I Add I to M with carry M ← (M) + I + C 0 1 0 1 1 0 DH DL I Add I to M with carry, then skip if carry M ← (M) + I + C skip if carry 0 1 0 1 1 1 DH DL I AICS M I SU r M Subtract M from r r ← (r) – (M) 0 1 1 0 0 0 DH DL r r ← (r) – (M) skip if borrow 0 1 1 0 0 1 DH DL r SUS r M Subtract M from r, then skip if borrow SB r M Subtract M from r with borrow r ← (r) – (M) – b 0 1 1 0 1 0 DH DL r SBS r M Subtract M from r with borrow, then skip if borrow r ← (r) – (M) – b skip if borrow 0 1 1 0 1 1 DH DL r SI M I Subtract I from M M ← (M) – I 0 1 1 1 0 0 DH DL I M ← (M) – I skip if borrow 0 1 1 1 0 1 DH DL I SIS M I Subtract I from M, then skip if borrow SIB M I Subtract I from M with borrow M ← (M) – I – b 0 1 1 1 1 0 DH DL I SIBS M I Subtract I from M with borrow, then skip if borrow M ← (M) – I – b skip if borrow 0 1 1 1 1 1 DH DL I SEQ r M Skip if r equal to M (r) – M skip if zero 0 0 0 1 0 0 DH DL r SEQI M I Skip if M equal to I (M) – I skip if zero 0 0 0 1 0 1 DH DL I SNEI M I Skip if M not equal to I (M) – I skip if not zero 0 0 0 0 0 1 DH DL I SGE r M Skip if r is greater than or equal to M (r) – M skip if not borrow 0 0 0 0 1 1 DH DL r SGEI M I Skip if M is greater than or equal to I (M) – I skip if not borrow 0 0 0 1 1 1 DH DL I SLEI M I Skip if M is less than I (M) – I skip if zero 0 0 0 0 1 1 DH DL I Continued on next page. No. 5065-11/13 LC72358N, 72362N, 72366 Logical operation instructions Instruction Group Continued from preceding page. Operand Mnemonic Transfer instructions Bit test instructions Jump and subroutine call instructions Operation 1st 2nd AND r M AND M with r r ← (r) AND (M) 0 0 1 0 0 0 ANDI M I AND I with M M ← (M) AND I 0 0 1 0 0 OR r M OR M with r r ← (r) OR (M) 0 0 1 0 ORI M I OR I with M M ← (M) ORI 0 0 1 EXL r M Exclusive OR M with r r ← (r) XOR (M) 0 0 EXLI M I Exclusive OR I with M M ← (M) XOR I 0 Carry (r) SHR Status register instructions Machine code Function D15 14 13 12 11 10 9 8 Shift r right with carry r 7 6 5 4 3 2 1 D0 DH DL r 1 DH DL I 1 0 DH DL r 0 1 1 DH DL I 1 1 0 0 DH DL r 0 1 1 0 1 DH DL I 0 0 0 0 0 0 0 0 1 1 1 0 r LD r M Load M to r r ← (M) 1 1 0 1 0 0 DH DL r ST M r Store r to M M ← (r) 1 1 0 1 0 1 DH DL r [DH, rn] ← (M) 1 1 0 1 1 0 DH DL r MVRD r M Move M to destination M referring to r in the same row MVRS M r Move source M referring to r to M in the same row M ← [DH, rn] 1 1 0 1 1 1 DH DL r MVSR M1 M2 Move M to M in the same row [DH, DL1] ← [DH, DL2] 1 1 1 0 0 0 DH DL1 DL2 MVI M I Move I to M M←I 1 1 1 0 0 1 DH DL I if M (N) = all 1, then skip 1 1 1 1 0 0 DH DL N 1 1 0 1 DH DL N TMT M N Test M bits, then skip if all bits specified are true TMF M N Test M bits, then skip if all bits specified are false if M (N) = all 0, then skip 1 1 JMP ADDR Jump to the address PC ← ADDR 1 0 CAL ADDR Call subroutine Stack ← (PC) + 1 1 1 0 0 RT Return from subroutine PC ← Stack 0 0 0 0 0 0 0 0 1 0 0 0 RTS Return from subroutine and skip PC ← Stack + 1 0 0 0 0 0 0 0 0 1 0 1 0 RTB Return from subroutine with bank data PC ← Stack BANK ← Stack 1 1 1 1 1 1 1 1 1 1 0 0 RTBS Return from subroutine with bank data and skip PC ← Stack + 1 BANK ← Stack 1 1 1 1 1 1 1 1 1 1 0 1 RTI Return from interrupt PC ← Stack BANK ← Stack Carry ← Stack 0 0 0 0 0 0 0 0 1 0 0 1 ADDR (14 bits) ADDR (12 bits) SS I N Set status register (Status reg I) N←1 1 1 1 1 1 1 1 1 0 0 0 I N RS I N Reset status register (Status reg I) N←0 1 1 1 1 1 1 1 1 0 0 1 I N TST I N Test status register true if (Status reg I) N = all 1, then skip 1 1 1 1 1 1 1 1 0 1 I N TSF I N Test status register false if (Status reg I) N = all 0, then skip 1 1 1 1 1 1 1 1 1 0 I N No. 5065-12/13 LC72358N, 72362N, 72366 Hardware control instructions F/F test Internal register transfer instructions instructions Instruction Group Continued from preceding page. Operand I/O instructions Bank switching instructions Function 1st Operation 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 Test unlock F/F then skip if it has not been set if unlock FF (N) = 0, then skip 0 0 0 0 0 0 0 0 1 1 0 1 N Load M to PLL registers PLL reg ← PLL data 1 1 1 1 1 0 DH DL r Rn Input register/port data to M M ← (Rn reg) 0 0 1 1 1 0 DH DL Rn M Rn Output contents of M to register/port Rn reg ← (M) 0 0 1 1 1 1 DH DL Rn SIO I1 I2 Serial I/o control SIO reg ← I1, I2 0 0 0 0 0 0 0 1 I1 I2 UCS I Set I to UCCW1 UCCW1 ← I 0 0 0 0 0 0 0 0 0 0 0 1 I UCC I Set I to UCCW2 UCCW2 ← I 0 0 0 0 0 0 0 0 0 0 1 0 I TUL N PLL M r INR M OUTR BEEP I Beep control Beep reg ← I 0 0 0 0 0 0 0 0 0 1 1 0 I DZC I Data zone control DZC reg ← I 0 0 0 0 0 0 0 0 1 0 1 1 I N TMS N Set timer register Timer reg ← I 0 0 0 0 0 0 0 0 1 1 0 0 IOS PWn N Set port control word IOS reg PWn ← N 1 1 1 1 1 1 1 0 PWn N M Pn Input port data to M M ← (Pn) 1 1 1 0 1 0 DH DL Pn OUT M Pn Output contents of M to port Pn ← M 1 1 1 0 1 1 DH DL Pn SPB Pn N Set port bits (Pn) N ← 1 0 0 0 0 0 0 1 0 Pn N RPB Pn N Reset port bits (Pn) N ← 0 0 0 0 0 0 0 1 1 Pn N if (Pn) N = all 1, then skip 1 1 1 1 1 1 0 0 Pn N IN Other instruc-tions Machine code Mnemonic TPT Pn N Test port bits, then skip if all bits specified are true TPF Pn N Test port bits, then skip if all bits specified are false if (Pn)) N = all 0, then skip 1 1 1 1 1 1 0 1 Pn N BANK I Select bank BANK ← I 0 0 0 0 0 0 0 0 0 1 1 1 I HALT I Halt mode control HALT reg ← I, then CPU clock stop 0 0 0 0 0 0 0 0 0 1 0 0 I CKSTP Clock stop Stop Xtal OSC if HOLD = 0 0 0 0 0 0 0 0 0 0 1 0 1 NOP No operation No operation 0 0 0 0 0 0 0 0 0 0 0 0 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1996. Specifications and information herein are subject to change without notice. No. 5065-13/13