Not recommended for new designs – Please use 93AA46C, 93AA56C or 93AA66C. 93AA46/56/66 1K/2K/4K 1.8V Microwire Serial EEPROM Features: Package Types +70°C -40°C to +85°C 1 8 V CC CLK 2 7 NU DI 3 6 ORG DO 4 5 V SS CS 1 8 V CC CLK 2 7 NU DI 3 6 ORG DO 4 5 V SS NU 1 8 ORG Vcc 2 7 Vss CS 3 6 DO CLK 4 5 DI SOIC SOIC 93AA46X 93AA56X 93AA66X - Industrial (I): 0°C to CS 93AA46 93AA56 93AA66 - Commercial (C): PDIP 93AA46 93AA56 93AA66 • Single supply with programming operation down to 1.8V • Low-power CMOS technology: - 70 µA typical active read current at 1.8V - 2 µA typical standby current at 1.8V • ORG pin selectable memory configuration: - 128 x 8- or 64 x 16-bit organization (93AA46) - 256 x 8- or 128 x 16-bit organization (93AA56) - 512 x 8 or 256 x 16-bit organization (93AA66) • Self-timed erase and write cycles (including auto-erase) • Automatic ERAL before WRAL • Power on/off data protection circuitry • Industry standard 3-wire serial I/O • Device status signal during erase/write cycles • Sequential read function • 1,000,000 E/W cycles ensured • Data retention > 200 years • 8-pin PDIP/SOIC (SOIC in JEDEC and EIAJ standards) • Temperature ranges supported: Description: The Microchip Technology Inc. 93AA46/56/66 are 1K, 2K and 4K low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 bits depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93AA Series is available in standard 8-pin PDIP and surface mount SOIC packages. The rotated pin-out 93AA46X/ 56X/66X are offered in the “SN” package only. Block Diagram VCC VSS Memory Array Address Decoder Address Counter Data Register Output Buffer DO DI 2004 Microchip Technology Inc. ORG CS Mode Decode Logic CLK Clock Generator DS20067J-page 1 93AA46/56/66 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C Soldering temperature of leads (10 seconds) .......................................................................................................+300°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DS20067J-page 2 2004 Microchip Technology Inc. 93AA46/56/66 TABLE 1-1: DC AND AC ELECTRICAL CHARACTERISTICS VCC = +1.8V to +5.5V Commercial (C): TA = 0°C to +70°C Industrial (I): TA = -40°C to +85°C Parameter Symbol High-level input voltage Min Typ Max Units Conditions VIH1 2.0 — VCC+1 V VCC ≥ 2.7V VIH2 0.7 VCC — VCC+1 V VCC < 2.7V VIL1 -0.3 — 0.8 V VCC ≥ 2.7V VIL2 -0.3 — 0.2 VCC V VCC < 2.7V VOL1 — — 0.4 V IOL = 2.1 mA; VCC = 4.5V VOL2 — — 0.2 V IOL = 100µA; VCC = 1.8V VOH1 2.4 — — V IOH = -400 µA; VCC = 4.5V VOH2 VCC-0.2 — — V IOH = -100 µA; VCC = 1.8V Input leakage current ILI -10 — 10 µA VIN = 0.1V to VCC Output leakage current ILO -10 — 10 µA VOUT = 0.1V to VCC Pin capacitance (all inputs/outputs) CIN, COUT — — 7 pF VIN/VOUT = 0V (Note 1 & 2) TA = +25°C, FCLK = 1 MHz Operating current ICC write — — 3 mA FCLK = 2 MHz; VCC=5.5V (Note 2) ICC read — — 1 500 mA µA µA FCLK = 2 MHz; VCC = 5.5V FCLK = 1 MHz; VCC = 3.0V FCLK = 1 MHz; VCC = 1.8V 100 30 µA µA µA CLK = CS = 0V; VCC = 5.5V CLK = CS = 0V; VCC = 3.0V CLK = CS = 0V; VCC = 1.8V ORG, DI = VSS or VCC 2 1 MHz MHz Low-level input voltage Low-level output voltage High-level output voltage 70 Standby current ICCS 2 VCC ≥ 4.5V VCC < 4.5V Clock frequency FCLK Clock high time TCKH 250 ns Clock low time TCKL 250 ns Chip select setup time TCSS 50 ns Relative to CLK Relative to CLK Chip select hold time TCSH 0 ns Chip select low time TCSL 250 ns Data input setup time TDIS 100 ns Relative to CLK Data input hold time TDIH 100 Data output delay time Data output disable time ns Relative to CLK TPD 400 ns CL = 100 pF TCZ 100 ns CL = 100 pF (Note 2) Status valid time TSV 500 ns CL = 100 pF Program cycle time TWC 4 10 ms Erase/Write mode TEC 8 15 ms ERAL mode (Vcc = 5V ± 10%) TWL 16 30 ms WRAL mode (Vcc = 5V ± 10%) — 1M — 25°C, Vcc = 5.0V, Block mode (Note 3) Endurance Note 1: 2: 3: — 1M This parameter is tested at TA = 25°C and FCLK = 1 MHz. This parameter is periodically sampled and not 100% tested. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site. 2004 Microchip Technology Inc. DS20067J-page 3 93AA46/56/66 TABLE 1-2: INSTRUCTION SET FOR 93AA46: ORG = 1 (X 16 ORGANIZATION) SB Opcode Address Data In Data Out Req. CLK Cycles READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25 EWEN 1 00 1 1 X X X X — High-Z 9 ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 9 ERAL 1 00 1 0 X X X X — (RDY/BSY) 9 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 25 WRAL 1 00 0 1 X X X X D15 - D0 (RDY/BSY) 25 EWDS 1 00 0 0 X X X X — High-Z 9 Instruction TABLE 1-3: INSTRUCTION SET FOR 93AA46: ORG = 0 (X 8 ORGANIZATION) SB Opcode Address Data In Data Out Req. CLK Cycles READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18 EWEN 1 00 1 1 X X X X X — High-Z 10 ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 10 ERAL 1 00 1 0 X X X X X — (RDY/BSY) 10 WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 18 Instruction WRAL 1 00 0 1 X X X X X D7 - D0 (RDY/BSY) 18 EWDS 1 00 0 0 X X X X X — High-Z 10 TABLE 1-4: INSTRUCTION SET FOR 93AA56: ORG = 1 (X 16 ORGANIZATION) SB Opcode Address Data In Data Out Req. CLK Cycles READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27 EWEN 1 00 1 1 X X X X X X — High-Z 11 ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 11 ERAL 1 00 1 0 X X X X X X — (RDY/BSY) 11 WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 27 Instruction WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY) 27 EWDS 1 00 0 0 X X X X X X — High-Z 11 TABLE 1-5: INSTRUCTION SET FOR 93AA56: ORG = 0 (X 8 ORGANIZATION) SB Opcode Address Data In Data Out Req. CLK Cycles READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20 EWEN 1 00 1 1 X X X X X X X — High-Z 12 ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 12 ERAL 1 00 1 0 X X X X X X X — (RDY/BSY) 12 WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 20 WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/BSY) 20 EWDS 1 00 0 0 X X X X X X X — High-Z 12 Instruction DS20067J-page 4 2004 Microchip Technology Inc. 93AA46/56/66 TABLE 1-6: INSTRUCTION SET FOR 93AA66: ORG = 1 (X 16 ORGANIZATION) SB Opcode Address Data In Data Out Req. CLK Cycles READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27 EWEN 1 00 1 1 X X X X X X — High-Z 11 ERASE 1 11 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 11 ERAL 1 00 1 0 X X X X X X — (RDY/BSY) 11 WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 27 Instruction WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY) 27 EWDS 1 00 0 0 X X X X X X — High-Z 11 TABLE 1-7: INSTRUCTION SET FOR 93AA66: ORG = 0 (X 8 ORGANIZATION) Data In Data Out Req. CLK Cycles A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20 1 1 X X X X X X X — High-Z 12 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 12 1 00 1 0 X X X X X X X — (RDY/BSY) 12 WRITE 1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 20 WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/BSY) 20 EWDS 1 00 0 0 X X X X X X X — High-Z 12 Instruction SB Opcode Address READ 1 10 EWEN 1 00 ERASE 1 ERAL 2004 Microchip Technology Inc. DS20067J-page 5 93AA46/56/66 2.0 FUNCTIONAL DESCRIPTION When the ORG pin is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the Ready/Busy status during a programming operation. The Ready/ Busy status can be verified during an erase/write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-Z state on the falling edge of the CS. 2.1 Start Condition The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (read, write, erase, EWEN, EWDS, ERAL, and WRAL). As soon as CS is high, the device is no longer in the Standby mode. An instruction following a Start condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become “don't care” bits until a new Start condition is detected. 2.2 DI/DO It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. 2.3 Data Protection The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. 2.4 Read The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16-bit (x16 organization) or 8 bit (x8 organization) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. 2.5 Erase/Write Enable and Disable (EWEN, EWDS) The 93AA46/56/66 power up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all erase/write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. 2.6 Erase The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction. The erase cycle takes 4 ms per word typical. During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V at nominal conditions. DS20067J-page 6 2004 Microchip Technology Inc. 93AA46/56/66 2.7 Write The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. The WRITE instruction is followed by 16 bits (or by 8 bits) of data which are written into the specified address. After the last data bit is put on the DI pin, CS must be brought low before the next rising edge of the CLK clock. This falling edge of CS initiates the self-timed auto-erase and programming cycle. The ERAL cycle takes (8 ms typical). 2.9 The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the Self Clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is ensured at 5V ± 10%. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. The write cycle takes 4 ms per word typical. 2.8 The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). Erase All (ERAL) The ERAL instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the erase cycle except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the Self Clocking mode. The ERAL instruction is ensured at 5V ± 10%. FIGURE 2-1: Write All (WRAL) The WRAL cycle takes 16 ms typical. SYNCHRONOUS DATA TIMING VIH CS VIL TCSS TCKH TCKL TCSH VIH CLK VIL TDIS TDIH VIH DI VIL TPD TPD TCZ VOH DO (Read) VOL TCZ TSV VOH DO (Program) VOL 2004 Microchip Technology Inc. Status Valid DS20067J-page 7 93AA46/56/66 FIGURE 2-2: READ TIMING TCSL CS CLK DI DO 1 1 An 0 A0 Tri-state FIGURE 2-3: 0 Dx D0 Dx D0 Dx D0 EWEN TIMING TCSL CS CLK 1 DI 0 0 FIGURE 2-4: X X 1 1 EWDS TIMING TCSL CS CLK DI DS20067J-page 8 1 0 0 0 0 X X 2004 Microchip Technology Inc. 93AA46/56/66 FIGURE 2-5: WRITE TIMING TCSL CS CLK 1 DI 1 0 An A0 D0 Dx Tri-state DO Busy Ready TWC FIGURE 2-6: WRAL TIMING TCSL Standby CS CLK 1 DI 0 0 0 X X Dx D0 Busy Tri-state DO Ready Tri-state TWL Ensured at Vcc = +4.5V to +6.0V. FIGURE 2-7: ERASE TIMING TCSL Check Status CS Standby CLK 1 DI 1 1 An An-1 An-2 A0 TSV DO Tri-state Busy TCZ Ready Tri-state TWC 2004 Microchip Technology Inc. DS20067J-page 9 93AA46/56/66 FIGURE 2-8: ERAL TIMING TCSL Check Status CS Standby CLK 1 DI 0 0 1 0 TCZ TSV DO Tri-state Busy Ready Tri-state TEC Ensured at Vcc = +4.5V to +6.0V. DS20067J-page 10 2004 Microchip Technology Inc. 93AA46/56/66 3.0 PIN DESCRIPTION TABLE 3-1: PIN FUNCTION TABLE Name 3.1 Function CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output Note: CS must go low between consecutive instructions. VSS Ground ORG Memory Configuration 3.3 NU Not Utilized VCC Power Supply Data In is used to clock in a Start bit, opcode, address and data synchronously with the CLK input. Chip Select (CS) A high level selects the device. A low level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. 3.2 After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed (see instruction set truth table). CLK and DI then become “don't care” inputs waiting for a new Start condition to be detected. Serial Clock (CLK) The Serial Clock is used to synchronize the communication between a master device and the 93AAXX. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. 3.4 Data In (DI) Data Out (DO) Data Out is used in the Read mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an erase or write operation has been initiated. The status signal is not available on DO, if CS is held low or high during the entire write or erase cycle. In all other cases DO is in the High-Z mode. If status is checked after the write/erase cycle, a pull-up resistor on DO is required to read the Ready signal. 3.5 Organization (ORG) When ORG is connected to VCC, the (x16) memory organization is selected. When ORG is tied to VSS, the (x8) memory organization is selected. ORG can only be floated for clock speeds of 1MHz or less for the (x16) memory organization. For clock speeds greater than 1 MHz, ORG must be tied to VCC or VSS. CLK is a “don't care” if CS is low (device deselected). If CS is high, but Start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for Start condition). CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle. 2004 Microchip Technology Inc. DS20067J-page 11 93AA46/56/66 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead PDIP XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (.150”) XXXXXXXX XXXXYYWW NNN 8-Lead SOIC (.208”) XXXXXXXX XXXXXXXX YYWWNNN DS20067J-page 12 Example 93AA46 017 0410 Example 93AA46 /SN0410 017 Example 93AA46X /SM 0310017 2004 Microchip Technology Inc. 93AA46/56/66 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2004 Microchip Technology Inc. DS20067J-page 13 93AA46/56/66 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS20067J-page 14 2004 Microchip Technology Inc. 93AA46/56/66 8-Lead Plastic Small Outline (SM) – Medium, 208 mil Body (SOIJ) (JEITA/EIAJ Standard, Formerly called SOIC) E E1 p D 2 1 n B α c A2 A φ L β Units Dimension Limits n p MIN INCHES* NOM 8 .050 .075 .074 .005 .313 .208 .205 .025 4 .009 .017 12 12 A1 MAX MILLIMETERS NOM 8 1.27 1.78 1.97 1.75 1.88 0.05 0.13 7.62 7.95 5.11 5.28 5.13 5.21 0.51 0.64 0 4 0.20 0.23 0.36 0.43 0 12 0 12 MIN Number of Pins Pitch Overall Height A .080 .070 Molded Package Thickness A2 .078 .069 Standoff A1 .002 .010 Overall Width E .300 .325 Molded Package Width E1 .201 .212 Overall Length D .202 .210 Foot Length L .020 .030 φ Foot Angle 0 8 c Lead Thickness .008 .010 Lead Width B .014 .020 α Mold Draft Angle Top 0 15 β Mold Draft Angle Bottom 0 15 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 2.03 1.98 0.25 8.26 5.38 5.33 0.76 8 0.25 0.51 15 15 Drawing No. C04-056 2004 Microchip Technology Inc. DS20067J-page 15 93AA46/56/66 APPENDIX A: REVISION HISTORY Revision J Added note to page 1 header (Not recommended for new designs). Added Section 4.0: Package Marking Information. Added On-line Support page. Updated document format. DS20067J-page 16 2004 Microchip Technology Inc. 93AA46/56/66 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2004 Microchip Technology Inc. DS20067J-page 17 93AA46/56/66 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: 93AA46/56/66 Y N Literature Number: DS20067J Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS20067J-page 18 2004 Microchip Technology Inc. 93AA46/56/66 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device 93AA46/56/66: 93AA46/56/66X: Microwire Serial EEPROM Microwire Serial EEPROM in alternate pinouts (SN package only) 93AA46T/56T/66T: Microwire Serial EEPROM (Tape and Reel) 93AA46XT/56XT/66XT: Microwire Serial EEPROM (Tape and Reel) Temperature Range Blank = 0°C to Package P SN SM = = = Plastic PDIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (208 mil Body), 8-lead (93AA46/56/66) +70°C Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. DS20067J-page 19 93AA46/56/66 NOTES: DS20067J-page 20 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS20067J-page 21 WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Korea Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. 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