TI SN74LVC1G3157DCKR

SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
D
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
1.65-V to 5.5-V VCC Operation
Useful for Both Analog and Digital
Applications
Specified Break-Before-Make Switching
Rail-to-Rail Signal Handling
High Degree of Linearity
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
Low On-State Resistance, Typically ≈6 Ω
(VCC = 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
B2
GND
B1
1
6
2
5
3
4
S
VCC
A
YEP OR YZP PACKAGE
(BOTTOM VIEW)
B1
GND
B2
3 4
2 5
1 6
A
VCC
S
description/ordering information
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes
of up to VCC (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40 C to 85
–40°C
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
TOP-SIDE
MARKING‡
SN74LVC1G3157YEPR
Tape and reel
_ _ _C5_
SN74LVC1G3157YZPR
SOT (SOT-23) – DBV
Tape and reel
SN74LVC1G3157DBVR
CC5_
SOT (SC-70) – DCK
Tape and reel
SN74LVC1G3157DCKR
C5_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
FUNCTION TABLE
CONTROL
INPUT
S
ON
CHANNEL
L
B1
H
B2
logic diagram (positive logic)
B2
S
B1
1
6
4
A
3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Switch I/O voltage range, VI/O (see Notes 1, 2, 3, and 4) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
On-state switch current, II/O (VI/O = 0 to VCC) (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 6): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 5.5 V maximum.
4. VI, VO, VA, and VBn are used to denote specific conditions for VI/O.
5. II, IO, IA, and IBn are used to denote specific conditions for II/O.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
recommended operating conditions (see Note 7)
VCC
VI/O
VIN
MIN
MAX
1.65
5.5
V
0
VCC
5.5
V
0
VCC × 0.75
VCC × 0.7
VIH
High-level input voltage, control input
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 5.5 V
VIL
Low-level input voltage, control input
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 5.5 V
VCC × 0.25
VCC × 0.3
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
10
∆t/∆v
t/ v
Input transition rise/fall time
UNIT
V
V
20
V
ns/V
10
TA
–40
85
°C
NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
ron
rrange
∆rron
ron(flat)
TEST CONDITIONS
On-state switch resistance‡
On-state switch resistance
over signal range‡§
Difference of on-state
resistance between switches‡¶#
ON resistance flatness‡¶||
See
Figures 1 and 2
IO= 4 mA
IO = –4 mA
VI = 0 V
VI = 2.3 V
IO = 8 mA
IO = –8 mA
2.3 V
VI = 0 V
VI = 3 V
IO = 24 mA
IO = –24 mA
3V
VI = 0 V
VI = 2.4 V
IO = 30 mA
IO = –30 mA
VI = 4.5 V
IO = –30 mA
IA = –4 mA
IA = –8 mA
IA = –24 mA
0 ≤ VBn ≤ VCC
(see Figures 1 and 2)
See Figure 1
VCC
VI = 0 V
VI = 1.65 V
VBn = 1.15 V
VBn = 1.6V
VBn = 2.1 V
VBn = 3.15 V
IA = –30 mA
IA = –4 mA
MAX
11
20
15
50
8
12
11
30
7
9
9
20
6
7
7
12
7
15
1.65 V
140
2.3 V
45
3V
18
4.5 V
UNIT
Ω
Ω
10
0.5
IA = –8 mA
IA = –24 mA
2.3 V
0.1
3V
0.1
IA = –30 mA
IA = –4 mA
4.5 V
0.1
1.65 V
110
2.3 V
26
3V
9
4.5 V
4
IA = –30 mA
Ω
Ω
±1
±1†
µA
5.5 V
±1
±0.1†
µA
0 ≤ VIN ≤ VCC
0 V to
5.5 V
±0.05
±1
±1†
µA
VIN = VCC or GND
VIN = VCC – 0.6 V
5.5 V
1
10
µA
500
µA
Ioffk
Off-state switch leakage current
0 ≤ VI, VO ≤ VCC, (see Figure 3)
IS(on)
On-state switch leakage current
VI = VCC or GND,
VO = Open (see Figure 4)
IIN
Control input current
ICC
∆ICC
Supply current
Supply-current change
4.5 V
TYP†
1.65 V
IA = –8 mA
IA = –24 mA
0 ≤ VBn ≤ VCC
1.65 V
MIN
1.65 V
to 5.5 V
±0.05
5.5 V
Cin
Control input
capacitance
S
5V
2.7
pF
Cio(off)
Switch input/output
capacitance
Bn
5V
5.2
pF
Cio(on)
Switch input/output
capacitance
Bn
5V
A
17.3
17.3
pF
† TA = 25°C
‡ Measured by the voltage drop between I/O pins at the indicated current through the switch. ON resistance is determined by the lower of the
voltages on the two (A or B) ports.
§ Specified by design
¶ ∆ron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels.
# This parameter is characterized, but not tested in production.
|| Flatness is defined as the difference between the maximum and minimum values of ON resistance over the specified range of conditions.
k Ioff is the same as IS(off) (off-state switch leakage current).
4
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
analog switch characteristics, TA = 25°C
FROM
(INPUT)
PARAMETER
Frequency response
(switch on)†
TO
(OUTPUT)
A or Bn
Crosstalk
(between switches)‡
Charge injection§
CL = 5 pF, RL = 50 Ω,,
fin = 10 MHz (sine wave)
(see Figure 8)
Bn or A
S
Total harmonic distortion
RL = 50 Ω,,
fin = 10 MHz (sine wave)
(see Figure 7)
B2 or B1
A or Bn
CL = 0.1 nF, RL = 1 M
MΩ,,
(see Figure 9)
A
A or Bn
VCC
RL = 50 Ω,,
fin = sine wave
(see Figure 6)
Bn or A
B1 or B2
Feed-through attenuation
(switch off)‡
TEST CONDITIONS
VI = 0.5 V p-p, RL = 600 Ω,
fin = 600 Hz to 20 kHz
(sine wave)
(see Figure 10)
Bn or A
TYP
1.65 V
300
2.3 V
300
3V
300
4.5 V
300
1.65 V
–54
2.3 V
–54
3V
–54
4.5 V
–54
1.65 V
–57
2.3 V
–57
3V
–57
4.5 V
–57
3.3 V
3
5V
7
1.65 V
0.1
2.3 V
0.025
3V
0.015
4.5 V
0.01
UNIT
MHz
dB
dB
pC
%
† Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
‡ Adjust fin voltage to obtain 0 dBm at input.
§ Specified by design
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 5 and 11)
PARAMETER
tpd¶
ten#
tdis||
FROM
(INPUT)
TO
(OUTPUT)
A or Bn
Bn or A
S
Bn
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
MAX
7
24
3.5
14
2.5
7.6
1.7
5.7
3
13
2
7.5
1.5
5.3
0.8
3.8
2
MIN
1.2
MAX
VCC = 5 V
± 0.5 V
MIN
0.8
UNIT
MAX
0.3
ns
ns
tB-Mk
0.5
0.5
0.5
0.5
ns
¶ tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch and the
specified load capacitance when driven by an ideal voltage source (zero output impedance).
# ten is the slower of tPZL or tPZH.
|| tdis is the slower of tPLZ or tPHZ.
k Specified by design
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5
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VIL or VIH
VCC
S
S
1
VIL
2
VIH
1
B1
SW
B2
VO
2
A
VI = VCC or GND
SW
GND
IO
r on
V
VI – VO
Figure 1. On-State Resistance Test Circuit
120
VCC = 1.65 V
100
ron
80
60
40
VCC = 2.3 V
20
VCC = 3 V
VCC = 4.5 V
0
0
1
2
3
4
5
VI – V
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
6
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Ť Ť
+ V *I V
I
O
O
W
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
S
VIL or VIH
S
1
VIL
2
VIH
VCC
1
B1
SW
B2
VI
SW
VO
2
A
A
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
VIL or VIH
SW
VCC
S
B1
B2
A
1
VIL
2
VIH
1
SW
VI
S
VO
VO = Open
2
A
GND
VI = VCC or GND
Figure 4. On-State Switch Leakage-Current Test Circuit
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7
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
50 pF
50 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
500 Ω
0.3 V
0.3 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
S
1
VIL
2
VIH
VCC
S
VIL or VIH
SW
B1
1
SW
B2
A
VO
2
RL
GND
50 Ω
fin
RL = 50 Ω
Figure 6. Frequency Response (Switch On)
S
VCC
VIL or VIH
TEST CONDITION
VIL
20log10(VO2/VI)
VIH
20log10(VO1/VI)
VCC
S
B1
VB1
fin
VB2
A
Analyzer
B2
GND
50 Ω
RL
RL = 50 Ω
Figure 7. Crosstalk (Between Switches)
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9
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
S
VIL or VIH
SW
B1
S
1
VIL
2
VIH
1
SW
Analyzer
B2
A
2
RL
GND
50 Ω
fin
RL = 50 Ω
Figure 8. Feed Through
VCC
VCC
S
B1
LOGIC
INPUT
1
SW
B2
VOUT
2
RGEN
VGE
A
GND
RL
CL
RL/CL = 1 MΩ/100 pF
LOGIC
INPUT
VOUT
OFF
ON
OFF
∆VOUT
Q = (∆VOUT) (CL)
Figure 9. Charge-Injection Test
10
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
S
VIL or VIH
SW
B1
S
1
VIL
2
VIH
1
10 µF
SW
B2
A
2
VO
RL
10 kΩ
CL
50 pF
GND
600 Ω
fin
VCC/2
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.30 V, VI = 2.0 VP-P
VCC = 3.00 V, VI = 2.5 VP-P
VCC = 4.50 V, VI = 4.0 VP-P
Figure 10. Total Harmonic Distortion
VCC
VCC
S
B1
VI = VCC/2
B2
VO
A
GND
VS
RL
CL
RL/CL = 50 Ω/35 pF
VO
0.9 x VO
tD
Figure 11. Break-Before-Make Internal Timing
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11
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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