FUJITSU MB39A125WQN

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27248-1E
ASSP for Power Supply Applications (Secondary battery)
DC/DC Converter IC for Charging
Li-ion Battery
MB39A125/126
■ DESCRIPTION
MB39A125/126 is a DC/DC converter IC for charging Li-ion battery, which is suitable for down-conversion, and
uses pulse width modulation (PWM) for controlling the output voltage and current independently. This IC integrates
the build-in comparator for the voltage detection of the AC adapter, and selects the AC adapter or battery automatically for power supply to the system.
Provides a wide range of power supply voltage, low standby current, and high efficiency, which makes them ideal
as a built-in charging device in products such as notebook PC.
■ FEATURES
•
•
•
•
High efficiency : 97% (MAX)
Built-in two constant current control circuits
Analog control of the charging current value (+INE1, +INE2 terminal)
Built-in AC adapter voltage detection function (ACOK, XACOK terminal)
(Continued)
■ PACKAGES
24-pin plastic SSOP
28-pin plastic QFN
(FPT-24P-M03)
(LCC-28P-M11)
MB39A125/126
(Continued)
• External output voltage setting resistor : MB39A125
• Built-in output voltage setting resistor : MB39A126
• Built-in charge stop function at low VCC
• Output voltage setting accuracy : ± 0.74% (Ta = −10 °C to +85 °C) : MB39A125
: 12.6 V/16.8 V ± 0.8% (Ta = −10 °C to +85 °C) : MB39A126
• Built-in high accuracy current detection amplifier (±5%) (At input voltage difference 100 mV) ,
(±15%) (At input voltage difference 20 mV)
• In IC standby mode (Icc = 0 µA Typ) , make output voltage setting resistor open to prevent inefficient current loss
• Built-in soft-start circuit
• Standby current : 0 µA (Typ)
• Totem-pole type output for Pch MOS FET
2
MB39A125/126
■ PIN ASSIGNMENTS
• MB39A125
(TOP VIEW)
−INC2
1
24
+INC2
OUTC2
2
23
GND
+INE2
3
22
CS
−INE2
4
21
VCC
ACOK
5
20
OUT
VREF
6
19
VH
ACIN
7
18
XACOK
−INE1
8
17
RT
+INE1
9
16
−INE3
OUTC1
10
15
FB123
OUTD
11
14
CTL
−INC1
12
13
+INC1
(FPT-24P-M03)
(Continued)
3
MB39A125/126
(Continued)
CS
VCC
OUT
VH
XACOK
RT
−INE3
(TOP VIEW)
28
27
26
25
24
23
22
CTL
+INC2
3
19
+INC1
N.C.
4
18
N.C.
−INC2
5
17
−INC1
OUTC2
6
16
OUTD
+INE2
7
15
N.C.
8
9
10
11
12
13
14
OUTC1
20
+INE1
2
−INE1
GND
ACIN
FB123
VREF
21
ACOK
1
−INE2
N.C.
(LCC-28P-M11)
Note : Connect IC’s radiation board at bottom side to potential of GND.
4
MB39A125/126
• MB39A126
(TOP VIEW)
−INC2
1
24
+INC2
OUTC2
2
23
GND
+INE2
3
22
CS
−INE2
4
21
VCC
ACOK
5
20
OUT
VREF
6
19
VH
ACIN
7
18
XACOK
−INE1
8
17
RT
+INE1
9
16
−INE3
OUTC1
10
15
FB123
SEL
11
14
CTL
−INC1
12
13
+INC1
(FPT-24P-M03)
(Continued)
5
MB39A125/126
(Continued)
CS
VCC
OUT
VH
XACOK
RT
−INE3
(TOP VIEW)
28
27
26
25
24
23
22
CTL
+INC2
3
19
+INC1
N.C.
4
18
N.C.
−INC2
5
17
−INC1
OUTC2
6
16
SEL
+INE2
7
15
N.C.
8
9
10
11
12
13
14
OUTC1
20
+INE1
2
−INE1
GND
ACIN
FB123
VREF
21
ACOK
1
−INE2
N.C.
(LCC-28P-M11)
Note : Connect IC’s radiation board at bottom side to potential of GND.
6
MB39A125/126
■ PIN DESCRIPTIONS
• MB39A125 : SSOP-24
Pin No.
Pin Name
I/O
Description
1
−INC2
I
Current detection amplifier (Current Amp2) inverted input terminal
2
OUTC2
O
Current detection amplifier (Current Amp2) output terminal
3
+INE2
I
Error amplifier (Error Amp2) non-inverted input terminal
4
−INE2
I
Error amplifier (Error Amp2) inverted input terminal
5
ACOK
O
AC adapter voltage detection block (AC Comp.) output terminal
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
6
VREF
O
Reference voltage output terminal
7
ACIN
I
AC adapter voltage detection block (AC Comp.) input terminal
8
−INE1
I
Error amplifier (Error Amp1) inverted input terminal
9
+INE1
I
Error amplifier (Error Amp1) non-inverted input terminal
10
OUTC1
O
Current detection amplifier (Current Amp1) output terminal
11
OUTD
O
When IC is standby mode, this terminal is set to “Hi-Z” to prevent loss
of inefficient current through the output voltage setting resistor.
Set CTL terminal to “H” level to output “L” level.
12
−INC1
I
Current detection amplifier (Current Amp1) inverted input terminal
13
+INC1
I
Current detection amplifier (Current Amp1) non-inverted input terminal
14
CTL
I
Power supply control terminal
Setting the CTL terminal at “L” level places the IC in the standby
mode.
15
FB123
O
Error amplifier (Error Amp1, 2, 3) output terminal
16
−INE3
I
Error amplifier (Error Amp3) inverted input terminal
17
RT
⎯
Triangular wave oscillation frequency setting resistor connection terminal
18
XACOK
O
AC adapter voltage detection block ( AC Comp.) output terminal
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
19
VH
O
Power supply terminal for FET drive circuit (VH = VCC − 6 V)
20
OUT
O
External FET gate drive terminal
21
VCC
⎯
Power supply terminal for reference voltage, control circuit, and output circuit
22
CS
⎯
Soft-start setting capacitor connection terminal
23
GND
⎯
Ground terminal
24
+INC2
I
Current detection amplifier (Current Amp2) non-inverted input terminal
7
MB39A125/126
• MB39A125 : QFN-28
Pin No.
Pin Name
8
I/O
Description
1
N.C.
⎯
No connection
2
GND
⎯
Ground terminal
3
+INC2
I
4
N.C.
⎯
5
−INC2
I
Current detection amplifier (Current Amp2) inverted input terminal
6
OUTC2
O
Current detection amplifier (Current Amp2) output terminal
7
+INE2
I
Error amplifier (Error Amp2) non-inverted input terminal
8
−INE2
I
Error amplifier (Error Amp2) inverted input terminal
9
ACOK
O
AC adapter voltage detection block (AC Comp.) output terminal
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
10
VREF
O
Reference voltage output terminal
11
ACIN
I
AC adapter voltage detection block (AC Comp.) input terminal
12
−INE1
I
Error amplifier (Error Amp1) inverted input terminal
13
+INE1
I
Error amplifier (Error Amp1) non-inverted input terminal
14
OUTC1
O
Current detection amplifier (Current Amp1) output terminal
15
N.C.
⎯
No connection
16
OUTD
O
When IC is standby mode, this terminal is set to “Hi-Z” to prevent loss
of inefficient current through the output voltage setting resistor.
Set CTL terminal to “H” level to output “L” level.
17
−INC1
I
Current detection amplifier (Current Amp1) inverted input terminal
18
N.C.
⎯
19
+INC1
I
Current detection amplifier (Current Amp1) non-inverted input terminal
20
CTL
I
Power supply control terminal
Setting the CTL terminal at “L” level places the IC in the standby
mode.
21
FB123
O
Error amplifier (Error Amp1, 2, 3) output terminal
22
−INE3
I
Error amplifier (Error Amp3) inverted input terminal
23
RT
⎯
Triangular wave oscillation frequency setting resistor connection terminal
24
XACOK
O
AC adapter voltage detection block ( AC Comp.) output terminal
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
25
VH
O
Power supply terminal for FET drive circuit (VH = VCC - 6 V)
26
OUT
O
External FET gate drive terminal
27
VCC
⎯
Power supply terminal for reference voltage, control circuit, and output circuit
28
CS
⎯
Soft-start setting capacitor connection terminal
Current detection amplifier (Current Amp2) non-inverted input terminal
No connection
No connection
MB39A125/126
• MB39A126 : SSOP-24
Pin No.
Pin Name
I/O
Description
1
−INC2
I
Current detection amplifier (Current Amp2) inverted input terminal
2
OUTC2
O
Current detection amplifier (Current Amp2) output terminal
3
+INE2
I
Error amplifier (Error Amp2) non-inverted input terminal
4
−INE2
I
Error amplifier (Error Amp2) inverted input terminal
5
ACOK
O
AC adapter voltage detection block (AC Comp.) output terminal
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
6
VREF
O
Reference voltage output terminal
7
ACIN
I
AC adapter voltage detection block (AC Comp.) input terminal
8
−INE1
I
Error amplifier (Error Amp1) inverted input terminal
9
+INE1
I
Error amplifier (Error Amp1) non-inverted input terminal
10
OUTC1
O
Current detection amplifier (Current Amp1) output terminal
11
SEL
I
Charge voltage setting switch terminal (3cells or 4cells)
SEL terminal “H” level : Charge voltage setting 16.8 V (4cells)
SEL terminal “L” level : Charge voltage setting 12.6 V (3cells)
12
−INC1
I
Current detection amplifier (Current Amp1) inverted input terminal
13
+INC1
I
Current detection amplifier (Current Amp1) non-inverted input terminal
14
CTL
I
Power supply control terminal
Setting the CTL terminal at “L” level places the IC in the standby mode.
15
FB123
O
Error amplifier (Error Amp1, 2, 3) output terminal
16
−INE3
I
Error amplifier (Error Amp3) inverted input terminal
17
RT
⎯
Triangular wave oscillation frequency setting resistor connection terminal
18
XACOK
O
AC adapter voltage detection block ( AC Comp.) output terminal
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
19
VH
O
Power supply terminal for FET drive circuit (VH = VCC - 6 V)
20
OUT
O
External FET gate drive terminal
21
VCC
⎯
Power supply terminal for reference voltage, control circuit, and output circuit
22
CS
⎯
Soft-start setting capacitor connection terminal
23
GND
⎯
Ground terminal
24
+INC2
I
Current detection amplifier (Current Amp2) non-inverted input terminal
9
MB39A125/126
• MB39A126 : QFN-28
Pin No.
Pin Name
10
I/O
Description
1
N.C.
⎯
No connection
2
GND
⎯
Ground terminal
3
+INC2
I
4
N.C.
⎯
5
−INC2
I
Current detection amplifier (Current Amp2) inverted input terminal
6
OUTC2
O
Current detection amplifier (Current Amp2) output terminal
7
+INE2
I
Error amplifier (Error Amp2) non-inverted input terminal
8
−INE2
I
Error amplifier (Error Amp2) inverted input terminal
9
ACOK
O
AC adapter voltage detection block (AC Comp.) output terminal
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
10
VREF
O
Reference voltage output terminal
11
ACIN
I
AC adapter voltage detection block (AC Comp.) input terminal
12
−INE1
I
Error amplifier (Error Amp1) inverted input terminal
13
+INE1
I
Error amplifier (Error Amp1) non-inverted input terminal
14
OUTC1
O
Current detection amplifier (Current Amp1) output terminal
15
N.C.
⎯
No connection
16
SEL
I
Charge voltage setting switch terminal (3cells or 4cells) .
SEL terminal “H” level : Charge voltage setting 16.8 V (4cells)
SEL terminal “L” level : Charge voltage setting 12.6 V (3cells)
17
−INC1
I
Current detection amplifier (Current Amp1) inverted input terminal
18
N.C.
⎯
19
+INC1
I
Current detection amplifier (Current Amp1) non-inverted input terminal
20
CTL
I
Power supply control terminal
Setting the CTL terminal at “L” level places the IC in the standby
mode.
21
FB123
O
Error amplifier (Error Amp1, 2, 3) output terminal
22
−INE3
I
Error amplifier (Error Amp3) inverted input terminal
23
RT
⎯
Triangular wave oscillation frequency setting resistor connection terminal
24
XACOK
O
AC adapter voltage detection block ( AC Comp.) output terminal
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
25
VH
O
Power supply terminal for FET drive circuit (VH = VCC - 6 V)
26
OUT
O
External FET gate drive terminal
27
VCC
⎯
Power supply terminal for reference voltage, control circuit, and output circuit
28
CS
⎯
Soft-start setting capacitor connection terminal
Current detection amplifier (Current Amp2) non-inverted input terminal
No connection
No connection
MB39A125/126
■ BLOCK DIAGRAMS
• MB39A125
ACIN
ACOK
XACOK
7
5
18
<AC Comp.>
+
−INE1
8
−
1.4 V
OUTC1
10
+INC1
13
−INC1
12
VREF
<Current Amp1>
+
×20
−
<Error Amp1>
−
0.2 V <UV Comp.>
+
+
+INE1
9
−INE2
4
−
−INC1
(Vo)
21 VCC
<PWM Comp.>
+
OUTC2
2
+INC2
24
−INC2
1
+INE2
3
FB123
15
<Current Amp2>
−
<Error Amp2>
−
+
×20
−
<OUT>
Drive
20 OUT
+
−2.5 V
−1.5 V
(VCC − 6 V)
19 VH
VH
Bias
Voltage
<Error Amp3>
−INE3
16
−
OUTD
11
+
4.2 V
<UVLO>
VREF
UVLO
VREF
4.2 V
Bias
< SOFT>
10 µA
Slope
Control
<OSC>
500 kHz Max
CS
<REF>
VCC
<CTL>
14 CTL
22
VREF
5.0 V
CT
(45 pF)
17
6
23
RT
VREF
GND
11
MB39A125/126
• MB39A126
ACIN
ACOK
XACOK
7
5
18
<AC Comp.>
+
−INE1
8
−
1.4 V
OUTC1
10
+INC1
13
−INC1
12
VREF
<Current Amp1>
+
×20
−
<Error Amp1>
−
0.2 V <UV Comp.>
+
+
+INE1
9
−INE2
4
−
−INC1
(Vo)
21 VCC
<PWM Comp.>
+
OUTC2
2
+INC2
24
−INC2
1
+INE2
3
FB123
15
<Current Amp2>
−
<Error Amp2>
−
+
×20
−
<OUT>
Drive
20 OUT
+
−2.5 V
−1.5 V
(VCC − 6 V)
19 VH
VH
−INE3
Bias
Voltage
<Error Amp3>
R1
−
16
R2
+
4.2 V/3.15 V
<UVLO>
VREF
UVLO
SEL 11
Hi : 4 Cells
Lo : 3 Cells
VREF
4.2 V
Bias
< SOFT>
10 µA
Slope
Control
<OSC>
500 kHz Max
CS
<REF>
<CTL>
22
VREF
5.0 V
CT
(45 pF)
12
VCC
17
6
23
RT
VREF
GND
14 CTL
MB39A125/126
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Power supply voltage
VCC
Output current
Peak output current
Power dissipation
Storage temperature
Rating
Unit
Min
Max
VCC terminal
⎯
28
V
IOUT
⎯
⎯
60
mA
IOUT
Duty ≤ 5% (t = 1 / fosc × Duty)
⎯
700
Ta ≤ +25 °C (SSOP-24)
⎯
Ta ≤ +25 °C (QFN-28)
⎯
3700*
⎯
−55
+125
PD
TSTG
mA
1
740*
2
mW
mW
°C
*1 : When mounted on a 10cm square epoxy double-sided.
*2 : The packages are mounted on the dual-sided epoxy board (10 cm × 10 cm) . Connect IC’s radiation board at
bottom side to potential of GND.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
13
MB39A125/126
■ RECOMMENDED OPERATION CONDITIONS
Parameter
Symbol
Condition
VCC terminal
Value
Unit
MIN
TYP
MAX
8
⎯
25
V
Power supply voltage
VCC
Reference voltage Output current
IREF
⎯
−1
⎯
0
mA
VH terminal output current
IVH
⎯
0
⎯
30
mA
Input voltage
VINE
+INE, −INE terminal
0
⎯
5
V
VINC
+INC, −INC terminal
0
⎯
VCC
V
CTL terminal input voltage
VCTL
⎯
0
⎯
25
V
Output current
IOUT
⎯
−45
⎯
+45
mA
Peak output current
IOUT
−600
⎯
+600
mA
ACIN terminal input Voltage
VACIN
⎯
0
⎯
VCC
V
ACOK terminal output voltage
VACOK
⎯
0
⎯
25
V
ACOK terminal output current
IACOK
⎯
0
⎯
1
mA
XACOK terminal output voltage
VXACOK
⎯
0
⎯
25
V
XACOK terminal output current
IXACOK
⎯
0
⎯
1
mA
OUTD terminal output voltage :
MB39A125
VOUTD
⎯
0
⎯
17
V
OUTD terminal output current :
MB39A125
IOUTD
⎯
0
⎯
2
mA
SEL terminal input voltage :
MB39A126
VSEL
⎯
0
⎯
25
V
Oscillation frequency
fOSC
⎯
100
300
500
kHz
Timing resistor
RT
⎯
27
47
130
kΩ
Soft-start capacitor
CS
⎯
⎯
0.22
1.0
µF
VH terminal capacitor
CVH
⎯
⎯
0.1
1.0
µF
Reference voltage output capacitor
CREF
⎯
⎯
0.22
1.0
µF
Ta
⎯
−30
+25
+85
°C
Operating ambient Temperature
Duty ≤ 5%
(t = 1 / fosc × Duty)
Note : The terminal number which has been described in the text is the one of the SSOP-24P package after this.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
14
MB39A125/126
■ ELECTRICAL CHARACTERISTICS
(VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
Parameter
2.
Under voltage
lockout
protection
circuit block
[UVLO]
Pin
No.
VREF1
6
Ta = +25 °C
VREF2
6
VREF1
Remarks
4.963 5.000 5.037
V
MB39A125
Ta = −10 °C to +85 °C
4.95
5.05
V
MB39A125
6
Ta = +25 °C
4.943 4.980 5.017
V
MB39A126
VREF2
6
Ta = −10 °C to +85 °C
4.930 4.980 5.030
V
MB39A126
Input stability
Line
6
VCC = 8 V to 25 V
⎯
3
10
mV
Load stability
Load
6
VREF = 0 mA to −1 mA
⎯
1
10
mV
Output current
at short circuit
Ios
6
VREF = 1 V
−50
−25
−12
mA
VTLH
6
VREF =
2.6
2.8
3.0
V
VTHL
6
VREF =
2.4
2.6
2.8
V
VH
6
⎯
⎯
0.2*
⎯
V
ICS
22
⎯
−14
−10
−6
µA
fOSC
20
RT = 47 kΩ
270
300
330
kHz
∆f/fdt
20
Ta = −30 °C to +85 °C
⎯
1*
⎯
%
⎯
1
5
mV
Threshold
voltage
Hysteresis
width
3.
Charge
Soft start block
current
[SOFT]
Oscillation
4.
frequency
Triangular
wave oscillator Frequency
temperature
block [OSC]
stability
Input offset
voltage
Input bias
current
VIO
Condition
Value
Unit
Output voltage
1.
Reference
voltage block
[REF]
Symbol
3, 4,
FB123 = 2 V
8, 9
Min
Typ
5.000
Max
IB
3, 4,
8, 9
⎯
−100
−30
⎯
nA
VCM
3, 4,
8, 9
⎯
0
⎯
5
V
Av
15
DC
⎯
100*
⎯
dB
BW
15
AV = 0 dB
⎯
1.3*
⎯
MHz
VFBH
15
⎯
4.8
5.0
⎯
V
VFBL
15
⎯
⎯
0.8
0.9
V
Output source
ISOURCE
current
15
FB123 = 2 V
⎯
−120
−60
µA
Output sink
current
15
FB123 = 2 V
2.0
4.0
⎯
mA
Common
mode input
voltage range
5-1.
Error amplifier Voltage gain
block
Frequency
[Error Amp1,
bandwidth
Error Amp2]
Output voltage
ISINK
* : Standard design value
(Continued)
15
MB39A125/126
(VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
Symbol
Pin
No.
Input
current
IINE
16
−INE3 = 0 V
Voltage
gain
Av
15
Frequency
bandwidth
BW
15
VFBH
15
VFBL
Parameter
Remarks
⎯
nA
MB39A125
100*
⎯
dB
⎯
1.3*
⎯
MHz
⎯
4.8
5.0
⎯
V
15
⎯
⎯
0.8
0.9
V
ISOURCE
15
FB123 = 2 V
⎯
−120
−60
µA
ISINK
15
FB123 = 2 V
2.0
4.0
⎯
mA
VTH1
16
FB123 = 2 V,
Ta = +25 °C
4.179
4.200
4.220
V
MB39A125
VTH2
16
FB123 = 2 V,
Ta = −10 °C to +85 °C
4.169
4.200
4.231
V
MB39A125
VTH3
12
SEL = 5 V, FB123 = 2 V,
16.700 16.800 16.900
Ta = +25 °C
V
MB39A126
VTH4
12
SEL = 5 V, FB123 = 2 V,
16.666 16.800 16.934
Ta = −10 °C to +85 °C
V
MB39A126
VTH5
12
SEL = 0 V, FB123 = 2 V,
12.525 12.600 12.675
Ta = +25 °C
V
MB39A126
VTH6
12
SEL = 0 V, FB123 = 2 V,
12.500 12.600 12.700
Ta = −10 °C to +85 °C
V
MB39A126
OUTD
terminal
output leak
current
ILEAK
11
OUTD = 17 V
⎯
0
1
µA
MB39A125
OUTD
terminal
output ON
resistance
RON
11
OUTD = 1 mA
⎯
35
50
Ω
MB39A125
IIN
12
−INC1 = 16.8 V
⎯
84
150
µA
MB39A126
R1
12, 16
⎯
105
150
195
kΩ
MB39A126
R2
16
⎯
35
50
65
kΩ
MB39A126
Output
source
current
Output sink
current
5-2.
Error
amplifier
block
[Error
Amp3]
Value
Unit
Output
voltage
Threshold
voltage
Input
current
Input
resistance
Condition
Min
Typ
Max
−100
−30
DC
⎯
AV = 0 dB
* : Standard design value
(Continued)
16
MB39A125/126
(VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
Parameter
Symbol
Input
current
Input
offset
voltage
Input
current
6.
Current
Detection
Amplifier
Block
[Current
Amp1,
Current
Amp2]
Condition
Value
Unit
Remarks
25
V
MB39A126
⎯
0.8
V
MB39A126
⎯
50
100
µA
MB39A126
⎯
0
1
µA
MB39A126
⎯
+3
mV
Min
Typ
Max
11
Error Amp3
reference voltage
= 4.2 V
(4-cell setting)
2
⎯
VOFF
11
Error Amp3
reference voltage
= 3.15 V
(3-cell setting)
0
ISELH
11
SEL = 5 V
ISELL
11
SEL = 0 V
VON
5-2.
SEL input
Error
voltage
amplifier
block
[Error Amp3]
Pin No.
VIO
+INC1 = +INC2 =
1, 12,
−INC1 = −INC2 =
13, 24
3 V to VCC
I+INCH
+INC1 = +INC2 =
13, 24 3 V to VCC,
∆VIN = −100 mV
⎯
20
30
µA
1, 12
+INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV
⎯
0.1
0.2
µA
MB39A125
1
+INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV
⎯
0.1
0.2
µA
MB39A126
I-INCH
−3
I+INCL
13, 24
+INC1 = +INC2 = 0 V,
∆VIN = −100 mV
−180
−120
⎯
µA
I-INCL
1, 12
+INC1 = +INC2 = 0 V,
∆VIN = −100 mV
−195
−130
⎯
µA
VOUTC1
2, 10
+INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV
1.9
2.0
2.1
V
VOUTC2
2, 10
+INC1 = +INC2 =
3 V to VCC,
∆VIN = −20 mV
0.34
0.40
0.46
V
VOUTC3
2, 10
+INC1 = +INC2 = 0 V,
∆VIN = −100 mV
1.8
2.0
2.2
V
VOUTC4
2, 10
+INC1 = +INC2 = 0 V,
∆VIN = −20 mV
0.2
0.4
0.6
V
Common
mode input
voltage
range
VCM
1, 12,
13, 24
⎯
0
⎯
VCC
V
Voltage
gain
Av
2, 10
19
20
21
V/V
Current
detection
voltage
+INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV
(Continued)
17
MB39A125/126
(VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
Parameter
6.
Current
Detection
Amplifier
Block
[Current
Amp1,
Current
Amp2]
9.
Low Input
Voltage
Detection
Block
[UV Comp.]
10.
AC Adapter
Voltage
Detection
Block
[AC Comp.]
Pin No.
BW
2, 10
VOUTCH
2, 10
VOUTCL
Condition
Value
Unit
Min
Typ
Max
⎯
2*
⎯
MHz
⎯
4.7
4.9
⎯
V
2, 10
⎯
⎯
20
200
mV
Output
source cur- ISOURCE
rent
2, 10
OUTC1 = OUTC2 = 2 V
⎯
−2
−1
mA
Output sink
current
ISINK
2, 10
OUTC1 = OUTC2 = 2 V
150
300
⎯
µA
VTL
15
Duty cycle = 0%
1.4
1.5
⎯
V
VTH
15
Duty cycle = 100%
⎯
2.5
2.6
V
Output
source cur- ISOURCE
rent
20
OUT = 13 V,
Duty ≤ 5%
(t = 1 / fosc × Duty)
⎯
−400*
⎯
mA
Output sink
current
ISINK
20
OUT = 19 V,
Duty ≤ 5%
(t = 1 / fosc × Duty)
⎯
400*
⎯
mA
Output ON
resistance
ROH
20
OUT = −45 mA
⎯
6.5
9.8
Ω
ROL
20
OUT = 45 mA
⎯
5.0
7.5
Ω
Rise time
tr1
20
OUT = 3300 pF
⎯
50*
⎯
ns
Fall time
tf1
20
OUT = 3300 pF
⎯
50*
⎯
ns
VTLH
21
VCC =
,
−INC1 = 16.8 V
17.2
17.4
17.6
V
VTHL
21
VCC =
,
−INC1 = 16.8 V
16.8
17.0
17.2
V
VH
21
⎯
0.4*
⎯
V
VTLH
7
ACIN =
1.3
1.4
1.5
V
VTHL
7
ACIN =
1.2
1.3
1.4
V
VH
7
⎯
0.1*
⎯
V
Frequency
bandwidth
Output
voltage
7.
PWM Comp.
Threshold
Block
voltage
[PWM
Comp.]
8.
Output
block
[OUT]
Symbol
Threshold
voltage
Hysteresis
width
Threshold
voltage
Hysteresis
width
AV = 0 dB
⎯
⎯
Remarks
* : Standard design value
(Continued)
18
MB39A125/126
(Continued)
(VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
Symbol
Pin
No.
ACOK
terminal
output leak
current
ILEAK
5
ACOK
terminal
output ON
resistance
RON
XACOK
terminal
output leak
current
XACOK
terminal
output ON
resistance
Parameter
Condition
Value
Unit
Min
Typ
Max
ACOK = 25 V
⎯
0
1
µA
5
ACOK = 1 mA
⎯
200
400
Ω
ILEAK
18
XACOK = 25 V
⎯
0
1
µA
RON
18
XACOK = 1 mA
⎯
200
400
Ω
VON
14
IC operation mode
2
⎯
25
V
VOFF
14
IC standby mode
0
⎯
0.8
V
ICTLH
14
CTL = 5 V
⎯
100
150
µA
ICTLL
14
CTL = 0 V
⎯
0
1
µA
12.
Bias Voltage Output
Block
Voltage
[VH]
VH
19
VCC = 8 V to 25 V,
VH = 0 mA to 30 mA
VCC −
6.5
VCC −
6.0
VCC −
5.5
V
Standby
current
ICCS
21
CTL = 0 V
⎯
0
10
µA
Power
supply
current
ICC
21
CTL = 5 V
⎯
5
7.5
mA
10.
AC Adapter
Voltage
Detection
Block
[AC Comp.]
11.
Power
Supply
Control
Block
[CTL]
13.
General
CTL input
voltage
Input current
Remarks
* : Standard design value
19
MB39A125/126
■ TYPICAL CHARACTERISTICS
6
1000
5
4
3
2
Ta = +25 °C
CTL = 5 V
1
Ta = +25 °C
VCC = 19 V
VREF = 0 mA
900
800
600
5
10
15
20
4
3
300
ICTL
200
1
0
5
10
15
0
25
20
CTL terminal input voltage VCTL (V)
Reference Voltage vs. Power Supply Voltage
Reference Voltage vs. Load Current
6
Reference voltage VREF (V)
6
Reference voltage VREF (V)
2
100
Power supply voltage VCC (V)
5
4
3
2
Ta = +25 °C
CTL = 5 V
VREF = 0 mA
1
0
0
5
10
15
20
Ta = +25 °C
VCC = 19 V
CTL = 5 V
5
4
3
2
1
0
0
25
5
Power supply voltage VCC (V)
10
15
20
25
30
35
Load current IREF (mA)
Reference Voltage vs.
Operating Ambient Temperature
Triangular Wave Oscillation Frequency vs.
Power Supply Voltage
340
VCC = 19 V
CTL = 5 V
VREF = 0 mA
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
−40
−20
Triangular wave oscillation
frequency fosc (kHz)
5.08
Reference voltage VREF (V)
5
400
25
8
6
VREF
500
0
0
9
7
700
0
10
Reference voltage VREF (V)
CTL Terminal Input Current, Reference Voltage vs.
CTL Terminal Input Voltage
CTL terminal input
current ICTL (µA)
Power supply current Icc (mA)
Power Supply Current vs. Power Supply Voltage
Ta = +25 °C
CTL = 5 V
RT = 47 kΩ
330
320
310
300
290
280
270
260
0
20
40
60
80
Operating ambient temperature Ta ( °C)
100
0
5
10
15
20
25
Power Supply Voltage VCC (V)
(Continued)
20
MB39A125/126
340
VCC = 19 V
CTL = 5 V
RT = 47 kΩ
330
320
310
300
290
280
270
260
−40
Triangular Wave Oscillation Frequency vs.
Timing Resistor
Triangular wave oscillation
frequency fosc (kHz)
Triangular wave oscillation
frequency fosc (kHz)
Triangular Wave Oscillation Frequency vs.
Operating Ambient Temperature
1000
Ta = +25 °C
VCC = 19 V
CTL = 5 V
100
10
−20
0
20
40
60
80
100
10
100
4.28
Timing resistor RT (kΩ)
VCC = 19 V
CTL = 5 V
VREF = 0 mA
4.26
4.24
4.22
4.20
4.18
4.16
4.14
4.12
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
Error amplifier threshold voltage VTH (V)
<MB39A126>
Error Amplifier Threshold Voltage vs.
Operating Ambient Temperature
16.90
VCC = 19 V
CTL = 5 V
SEL = 5 V
16.85
16.80
16.75
16.70
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
Error amplifier threshold voltage VTH (V)
Error amplifier threshold voltage VTH (V)
Operating ambient temperature Ta ( °C)
<MB39A125>
Error Amplifier Threshold Voltage vs.
Operating Ambient Temperature
1000
Error Amplifier Threshold Voltage vs.
Operating Ambient Temperature
12.70
VCC = 19 V
CTL = 5 V
SEL = 0 V
12.65
12.60
12.55
12.50
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
(Continued)
21
MB39A125/126
Error Amplifier, Gain, Phase vs. Frequency
Vcc = 19 V
Ta = +25 °C
VCC = 19 V 180
40
4.2 V
10
kΩ
20
90
φ
10
Av
0
0
−10
−90
−20
Phase φ (deg)
Gain Av (dB)
30
IN
1 µF
+
240 kΩ
10
kΩ
−INE1, 2
2.4 kΩ
−
8
FB123
15
(4)
+
(3)
+INE1, 2
OUT
9
10
kΩ
10
kΩ
−30
Error Amp1
(Error Amp2)
−180
−40
100
1k
10k
100k
1M
10M
Frequency f (Hz)
Error Amplifier, Gain, Phase vs. Frequency
Ta = +25 °C
VCC = 19 V 180
40
30
φ
10
Av
0
0
−10
−90
−20
−30
240 kΩ
10
kΩ
90
Phase φ (deg)
Gain Av (dB)
20
IN
1µF
+
−INE3
16
−
2.4 kΩ
FB123
15
+
10
kΩ
4.2 V
OUT
Error Amp3
−180
−40
100
1k
10k
100k
1M
10M
Frequency f (Hz)
Current Detection Amplifier, Gain, Phase vs. Frequency
40
30
0
0
φ
−10
−20
−90
Phase φ (deg)
90
10
VCC = 19 V
+
13
×20
(24)
−INC
−
12
(1)
Av
20
Gain Av (dB)
+INC
180
OUTC
10
(2)
OUT
Current Amp1
(Current Amp2)
12.6 V
12.55 V
−30
−40
100
−180
1k
10k
100k
1M
10M
Frequency f (Hz)
(Continued)
22
MB39A125/126
(Continued)
Power Dissipation vs.
Operating Ambient Temperature (QFN)
800
740
700
Power dissipation PD (mW)
Power dissipation PD (mW)
Power Dissipation vs.
Operating Ambient Temperature (SSOP)
600
500
400
300
200
100
0
−40
−20
4000
3700
3500
3000
2500
2000
1500
1000
500
0
0
20
40
60
80
Operating ambient temperature Ta ( °C)
100
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
23
MB39A125/126
■ FUNCTIONAL DESCRIPTION
1. DC/DC Converter Block
(1) Reference voltage block (REF)
The reference voltage circuit uses the voltage supplied from the VCC terminal (pin 21) to generate a temperature
compensated, stable voltage (5.0 V Typ) used as the reference power supply voltage for the IC’s internal circuitry.
This block can also be used to obtain a load current to a maximum of 1 mA from the reference voltage VREF
terminal (pin 6) .
(2) Triangular wave oscillator block (OSC)
The triangular wave oscillator block has built-in capacitor for frequency setting into and generates the triangular
wave oscillation waveform by connecting the frequency setting resistor with the RT terminal (pin 17) .
The triangular wave is input to the PWM comparator circuits on the IC.
(3) Error amplifier block (Error Amp1)
This amplifier detects the output signal from the current detection amplifier (Current Amp1) , compares this to
the +INE1 terminal (pin 9) , and outputs a PWM control signal to be used in controlling the charge current.
In addition, an arbitrary loop gain can be set up by connecting a feedback resistor and capacitor between the
FB123 terminal (pin 15) and −INE1 terminal (pin 8) , providing stable phase compensation to the system.
(4) Error amplifier block (Error Amp2)
This amplifier detects the output signal from the current detection amplifier (Current Amp2) , compares this to
the +INE2 terminal (pin 3) , and outputs a PWM control signal to be used in controlling the charge current.
In addition, an arbitrary loop gain can be set up by connecting a feedback resistor and capacitor between the
FB123 terminal (pin 15) and −INE2 terminal (pin 4) , providing stable phase compensation to the system.
(5) Error amplifier block (Error Amp3)
This error amplifier (Error Amp3) detects the output voltage from the DC/DC converter and outputs the PWM
control signal. MB39A125 can set the desired level of output voltage from 1 cell to 4 cells by connecting external
output voltage setting resistors to the error amplifier inverted input terminal. MB39A126 can set the output voltage
for 3 cells or 4 cells by SEL terminal (pin 11) input.
In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the FB123
terminal (pin 15) to the −INE3 terminal (pin 16) , enabling stable phase compensation to the system.
(6) Current detection amplifier block (Current Amp1)
The current detection amplifier (Current Amp1) detects a voltage drop which occurs between both ends of the
output sense resistor (RS2) due to the flow of the charge current, using the +INC1 terminal (pin 13) and −INC1
terminal (pin 12) . The signal amplified to 20 times is output to the OUTC1 terminal (pin 10) .
24
MB39A125/126
(7) Current detection amplifier block (Current Amp2)
The current detection amplifier (Current Amp2) detects a voltage drop which occurs between both ends of the
output sense resistor (RS1) due to the flow of the AC adapter current, using the +INC2 terminal (pin 24) and
−INC2 terminal (pin 1) . The signal amplified to 20 times is output to the OUTC2 terminal (pin 2) .
(8) PWM comparator block (PWM Comp.)
The PWM comparator circuit is a voltage-pulse width converter for controlling the output duty of the error
amplifiers (Error Amp1 to Error Amp3) depending on their output voltage.
The PWM comparator circuit compares the triangular wave voltage the lowest generated by the triangular wave
oscillator to the error amplifier output voltage and turns on the external output transistor, during the interval in
which the triangular wave voltage is lower than the error amplifier output voltage.
(9) Output block (OUT)
The output circuit uses a totem-pole configuration capable of driving an external Pch MOS FET.
The output “L” level sets the output amplitude to 6 V (Typ) using the voltage generated by the bias voltage block
(VH) .
This results in increasing conversion efficiency and suppressing the withstand voltage of the connected external
transistor in a wide range of input voltages.
(10) Power supply control block (CTL)
Setting the CTL terminal (pin 14) low places the IC in the standby mode. (The power supply current is 10µA at
maximum in the standby mode.)
CTL function table : MB39A125
CTL
Power
OUTD
L
OFF (Standby)
Hi-Z
H
ON (Active)
L
CTL function table : MB39A126
CTL
Power
L
OFF (Standby)
H
ON (Active)
(11) Bias voltage block (VH)
The bias voltage circuit outputs VCC − 6 V (Typ) as the minimum potential of the output circuit. In the standby
mode, this circuit outputs the potential equal to VCC.
25
MB39A125/126
2. Protection Functions
(1) Under voltage lockout protection circuit block (UVLO)
The transient state or a momentary decrease in power supply voltage or internal reference voltage (VREF) ,
which occurs when the power supply (VCC) is turned on, may cause malfunctions in the control IC, resulting in
breakdown or deterioration of the system.
To prevent such malfunction, the under voltage lockout protection circuit detects internal reference voltage drop
and fixes the OUT terminal (pin 20) to the “H” level. The system restores voltage supply when the internal
reference voltage reaches the threshold voltage of the under voltage lockout protection circuit.
Protection circuit (UVLO) operation function table : MB39A125
When UVLO is operating (VREF voltage is lower than UVLO threshold voltage, the logic of the following terminal
is fixed.)
OUTD
OUT
CS
ACOK
XACOK
Hi-Z
H
L
H
L
Protection circuit (UVLO) operation function table : MB39A126
When UVLO is operating (VREF voltage is lower than UVLO threshold voltage, the logic of the following terminal
is fixed.)
OUT
CS
ACOK
XACOK
H
L
H
L
(2) Low input voltage detection block (UV Comp.)
UV Comp. detects that power supply voltage (VCC) is lower than the battery voltage +0.2 V (Typ) and fixes the
OUT terminal (pin 20) to the “H” level.
The system restores voltage supply when the power supply voltage reaches the threshold voltage of the AC
adapter detection block.
Protection circuit (UV Comp.) operation function table : MB39A125
When UV Comp. is operating (VCC voltage is lower than UV Comp. threshold voltage, the logic of the following
terminal is fixed.)
OUTD
OUT
CS
L
H
L
Protection circuit (UV Comp.) operation function table : MB39A126
When UV Comp. is operating (VCC voltage is lower than UV Comp. threshold voltage, the logic of the following
terminal is fixed.)
OUT
CS
H
26
L
MB39A125/126
3. Detection Function
(1) AC adapter voltage detection block (AC Comp.)
When ACIN terminal (pin 7) voltage is lower than 1.3 V (Typ) , AC adapter voltage detection block (AC Comp.)
outputs “Hi-Z” level to the ACOK terminal (pin 5) and outputs “L” level to the XACOK terminal (pin 18) . When
CTL terminal (pin 14) is set to “L” level, ACOK terminal (pin 5) and XACOK terminal (pin 18) are fixed to “Hi-Z” level.
ACIN
ACOK
XACOK
H
L
Hi-Z
L
Hi-Z
L
4. Switch Function : MB39A126
The charge voltage can be set to 16.8 V/12.6 V with the SEL terminal (pin 11) .
SEL function table
SEL
DC/DC output setting voltage
H
16.8 V
L
12.6 V
27
MB39A125/126
■ CONSTANT CHARGING VOLTAGE AND CURRENT OPERATION
MB39A125/126 is DC/DC converter with the pulse width modulation (PWM) .
MB39A125 is in the output voltage control loop, the Error Amp3 compares internal voltage reference voltage
4.2 V and DC/DC converter output to output the PWM controlled signal.
MB39A126 is in the output voltage control loop, the Error Amp3 compares internal voltage reference voltage
4.2 V/3.15 V and DC/DC converter output to output the PWM controlled signal.
In the charging current control loop, the voltage drop generated at both ends of charging current sense resistor
(RS2) is sensed by +INC1 terminal (pin 13) , −INC1 terminal (pin 12) of Current Amp1, and the signal is output
to OUTC1 terminal (pin 10) , which is amplified by 20 times. Error Amp1 compares the OUTC1 terminal (pin
10) voltage, which is the output of Current Amp1, and +INE1 terminal (pin 9) to output the PWM control signal
and regulates the charging current.
In the AC adapter current control loop, the voltage drop generated at both ends of AC adapter current sense
resistor (RS1) is sensed by +INC2 terminal (pin 24) , −INC2 terminal (pin 1) of Current Amp2, and the signal is
output to OUTC2 terminal (pin 2) , which is amplified by 20 times. Error Amp2 compares OUTC2 terminal (pin
2) voltage, which is output of Current Amp2, and +INE2 terminal (pin 3) voltage and outputs PWM controlled
signal, and it limits the charging current due to the AC adapter current not to exceed the setting value.
The PWM comparator compares the triangular wave to the smallest terminal voltage among the Error AMP1,
Error AMP2 and Error AMP3. And the triangular wave voltage generated by the triangular wave oscillator. When
the triangular wave voltage is smaller than the error amplifier output voltage, the main side output transistor is
turned on.
28
MB39A125/126
■ SETTING THE CHARGE VOLTAGE
MB39A125
The charging voltage (DC/DC output voltage) can be set by connecting external output voltage setting resistors
(R3, R4) to the −INE3 terminal (pin 16) . Be sure to select a resistor value that allows you to ignore the onresistance (35 Ω, 1 mA) of the internal FET connected to the OUTD terminal (pin 11) .
Battery charging voltage : Vo
Vo (V) = (R3 + R4) / R4 × 4.2 (V)
B Vo
R3
−INE3
<Error Amp3>
16
R4
−
+
11
4.2 V
OUTD
29
MB39A125/126
MB39A126
The setting of the charge voltage is switched to 3cells or 4cells by the SEL terminal (pin 11) .
Charge voltage is set to 16.8 V when SEL terminal is “H” level, and charge voltage is set to 12.6 V when SEL
terminal is “L” level.
Battery charging voltage : Vo
Vo (V) = (150 kΩ + 50 kΩ) / 50 kΩ × 4.2 (V) = 16.8 (V) (SEL = H)
Vo (V) = (150 kΩ + 50 kΩ) / 50 kΩ × 3.15 (V) = 12.6 (V) (SEL = L)
−INC1
12
R3
−INE3
150 kΩ
<Error Amp3>
−
16
R4
50 kΩ
+
SEL
11
3.15 V
30
4.2 V
MB39A125/126
■ SETTING THE CHARGE CURRENT
The charge current value can be set at the analog voltage value of the +INE1 terminal (pin 9) .
Charge current formula : Ichg (A) = V+INE1 (V) / (20 × RS1 (Ω) )
Charge current setting voltage : V+INE1 (V) = 20 × Ichg (A) × RS1 (Ω)
■ SETTING THE INPUT CURRENT
The input limit current value can be set at the analog voltage value of the +INE2 terminal (pin 3) .
Input current formula : IIN (A) = V+INE2 (V) / (20 × RS2 (Ω) )
Input current setting voltage : V+INE2 (V) = 20 × IIN (A) × RS2 (Ω)
■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY
The triangular wave oscillation frequency can be set by the timing resistor (RT) connected to the RT terminal
(pin 17) .
Triangular wave oscillation frequency fosc
fosc (kHz) =: 14100 / RT (kΩ)
31
MB39A125/126
■ SETTING THE SOFT-START TIME
Soft-start function prevents rush current at start-up of IC when the Soft-start capacitor (Cs) is connected to the
CS terminal (pin 22) . This IC charges external soft-start capacitor (Cs) with 10 µA after CTL terminal (pin 14)
voltage level becomes high and IC starts (when VCC ≥ UVLO threshold voltage) .
Output ON duty depends on PWM comparator, which compares the FB123 terminal (pin 15) voltage with the
triangular wave oscillator output voltage.
During soft start, FB123 terminal (pin 15) voltage increases with sum voltage of CS terminal and diode voltage.
Therefore, the output voltage of the DC/DC converter and current increase can be set by output ON duty in
proportion to rise of CS terminal (pin 22) voltage. The ON Duty is affected by the ramp voltage of FB123 terminal
(pin 15) until an output voltage of one Error Amp reaches the DC/DC converter loop controlled voltage.
Soft-start time is obtained from the following formula :
Soft-start time : ts (time to output on duty 80 %)
ts (s) =: 0.13 × Cs (µF)
• Soft-start timing chart
CS
CT
FB123
CS
FB123
CT
0V
OUT
OUT
0V
Vo
Error Amp3 threshold voltage
Vo
0V
Io
0A
32
Io
MB39A125/126
■ TRANSIENT RESPONSE AT LOAD-STEP
The constant voltage control loop and the constant current control loop are independent. With the load-step,
these two control loops change.
The battery voltage and current overshoot are generated by the delay time of the control loop when the mode
changes. The delay time is determined by phase compensation constant. When the battery is removed if the
charge control is switched from the constant current control to the constant voltage control, and the charging
voltage does overshoot by generating the period controlled with high duty by output setting voltage. The excessive
voltage is not applied to the battery because the battery is not connected.
When the battery is connected if the charge control is switched from the constant voltage control to the constant
current control, and the charging current does overshoot by generating the period controlled with high duty by
charge current setting.
The battery pack manufacturer in Japan thinks it is not the problem the current overshoot of 10 ms or less.
• Timing chart at load-step
Error Amp3 Output
Error Amp1 Output
Constant Current
Battery Voltage
Battery Current
Error Amp1 Output
Error Amp3 Output
Constant Voltage
Constant Current
When charge control switches
from the constant current control to
the constant voltage control, the
voltage does overshoot by generating the period controlled with
high duty by output setting voltage.
The battery pack manufacturer in Japan thinks it is
not the problem the current
overshoot of 10 ms or less.
10 ms
33
MB39A125/126
■ AC ADAPTER DETECTION FUNCTION
When ACIN terminal (pin 7) voltage is lower than 1.3 V (Typ) , AC adapter voltage detection block (AC Comp.)
outputs “Hi-Z” level to the ACOK terminal (pin 5) and outputs “L” level to the XACOK terminal (pin 18) . When
CTL terminal (pin 14) is set to “L” level, ACOK terminal (pin 5) and XACOK terminal (pin 18) are fixed to “Hi-Z” level.
(1) AC adapter presence
If you connect as shown in the figure below the presence of AC adapter can be easily detected because the
signal is output from the ACOK terminal (pin 5) to microcomputer etc. In this case, if the CTL terminal is set to
“L” level, IC becomes the standby state (ICC = 0 µA Typ).
• Connection example of detecting AC adapter presence
micon
AC adapter
ACIN
ACOK
7
5
<AC Comp.>
+
−
34
XACOK
18
MB39A125/126
(2) Automatic changing system power supply between AC adapter and battery
The AC adapter voltage is detected and external switch at input side and battery side can be changed automatically with the connection as follows. Connect CTL terminal (pin 14) to VCC terminal (pin 21) for this function.
OFF duty cycle becomes 100% when CS terminal (pin 22) voltage is made to be 0 V, if it is needed after full charge.
• Connection example of automatic changing system power supply between AC adapter and battery
System
AC adapter
7
ACIN
5
ACOK
18
XACOK
Battery
<AC Comp.>
+
−
VCC
21
CTL
14
< SOFT>
VREF
10 µA
CS
micon
22
35
MB39A125/126
(3) Battery selector function
When control signal from microcomputer etc. is input to ACIN terminal (pin 7) as shown in the following diagram,
ACOK terminal (pin 5) output voltage and XACOK terminal (pin 18) output voltage are controlled to select one
of the two batteries for charge. Connect CTL terminal (pin 14) to VCC terminal (pin 21) for this function. OFF
duty cycle becomes 100% when CS terminal (pin 22) voltage is made to be 0 V, if it is needed after full charge.
• Connection example of battery selector function
System
AC adapter
7
ACIN
5
<AC Comp.>
+
ACOK
18
XACOK
A
B
ICHG
RS1
−
VCC
CTL
micon
36
CS
21
14
Battery1
< SOFT>
VREF
10 µA
22
Battery2
MB39A125/126
(4) When AC Comp. is not used
When AC Comp. (ACIN (pin 7) , ACOK (pin 5) , and XACOK (pin 18) terminals) is not used as follows, connect
the ACIN (pin 7) , ACOK (pin 5) , and XACOK (pin 18) terminals to GND terminal (pin 23) .
And connect VCC terminal (pin 21) to system, as follows, to avoid the reverse current from the battery to the
VCC terminal (pin 21) .
• Connection example when AC Comp. is not used
System
AC adapter
ACIN
7
ACOK
5
<AC Comp.>
+
−
XACOK
18
A
B
ICHG
RS1
Battery
VCC
21
37
MB39A125/126
■ PHASE COMPENSATION
• Example Circuit
VIN
21
<Error Amp 3>
−INE3
16
RS2
15mΩ
VCC
<PWM Comp.>
−
<OUT>
+
Cc
OUT
+
20
Drive
I1
−
4.2 V
Lo
Rc
−2.5V
−1.5V
FB123
15
19
VH
VH
RS1
33 mΩ
(VCC − 6V)
Ro
Rin1
Co
Bias
Voltage
OSC
VBATT
RL
ESR
Rin2
Lo : Inductance
RL : Equivalent series resistance of inductance
Co : Capacity of condenser
ESR : Equivalent series resistance of condenser
Ro : Load resistance
• Frequency Characteristics of LC filter
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
gain
phase
Gain
Phase
1
10
100
1k
10k
Frequency [Hz]
38
100k
1M
180
160
140
120
100
80
60
40
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
10M
Cut-off frequency
1
f1 (Hz) =
Phase [deg]
Gain [dB]
Frequency characteristic of power output LC filter
(DC gain is included.)
2π
Lo × Co ×
Lo = 15 µH
Co = 14.1 µF
Ro = 4.2 Ω
RL = 30 mΩ
ESR = 100 mΩ
(Ro + ESR)
(Ro + RL)
MB39A125/126
• Frequency Characteristics of Error Amp
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
total gain
AMP Open
Loop Gain
total phase
Gain
Phase
1
10
100
1k
10k
100k
180
160
140
120
100
80
60
40
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
1M
Cut-off frequency
f2(Hz) =
Phase [deg]
Gain [dB]
Total frequency characteristic
1
2π × Rc × Cc
Rc = 150 kΩ
Cc = 3300 pF
Frequency [Hz]
• Frequency Characteristics of DC/DC converter
total gain
AMP Open
Loop Gain
total phase
Gain
Phase
1
10
100
1k
10k
Frequency [Hz]
100k
180
160
140
120
100
80
60
40
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
1M
Phase [deg]
Gain [dB]
Total frequency characteristic
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
The overview of frequency characteristic
for DC/DC converter can be obtained in
combination between “Frequency
Characteristics of LC filter” and
“Frequency Characteristics of Error Amp ”
as mentioned above.
Please note the following point in order to
stabilize the frequency characteristics of
DC/DC converter .
Cut-off frequency of DC/DC converter
should be set to half or less of the
triangular wave oscillator frequency.
Triangular wave frequency
Notes : 1) Please review the Error Amp frequency characteristics, when LC filter parameter is modified.
2) When the ceramic capacitor is used as smoothing capacitor Co, phase margin is reduced because ESR
of the ceramic capacitor is extremely small as shown in “Frequency Characteristics of LC filter which is
using low ESR”.
Therefore, change phase compensation of Error Amp or create resistance equivalent to ESR using
pattern.
39
MB39A125/126
• Frequency Characteristics of LC filter which is using low ESR
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
gain
phase
Gain
Phase
1
10
100
1k
10k
100k
1M
180
160
140
120
100
80
60
40
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
10M
Cut-off frequency
1
f1 (Hz) =
Phase [deg]
Gain [dB]
Frequency characteristic of power output LC filter
(DC gain is included.)
2π
Lo × Co ×
(Ro + ESR)
(Ro + RL)
Lo = 15 µH
Co = 14.1 µF
Ro = 4.2 Ω
RL = 30 mΩ
ESR = 100 mΩ
Frequency [Hz]
<3Pole2Zero>
DC/DC output
< Additional ESR>
−
+
40
Board Pattern
or connected
resistor
MB39A125/126
■ PROCESSING WITHOUT USING OF THE CURRENT AMP1 AND AMP2
When Current Amp is not used, connect the +INC1 terminal (pin 13) , +INC2 terminal (pin 24) , −INC1 terminal
(pin 12) , and −INC2 terminal (pin 1) to VREF terminal (pin 6) , and then leave OUTC1 terminal (pin 10) and
OUTC2 terminal (pin 2) open.
• Connection when Current Amp is not used
12 −INC1
1 −INC2
”open”
+INC1 13
+INC2 24
10 OUTC1
2 OUTC2
6
VREF
■ PROCESSING WITHOUT USING OF THE ERROR AMP1 AND AMP2
When Error Amp is not used, leave FB123 terminal (pin 15) open, connect the −INE1 terminal (pin 8) and −INE2
terminal (pin 4) to GND, and connect +INE1 terminal (pin 9) and +INE2 terminal (pin 3) to VREF terminal (pin 6) .
• Connection when Error Amp is not used
9 +INE1
3 +INE2
GND
23
8 −INE1
4 −INE2
”open”
16 FB123
6
VREF
41
MB39A125/126
■ PROCESSING WITHOUT USING OF THE CS TERMINAL
When soft-start function is not used, leave the CS terminal (pin 22) open.
• Connection when no soft-start time is specified
”open”
CS 22
42
MB39A125/126
■ I/O EQUIVALENT CIRCUIT
• <Reference voltage block>
• <Power supply control block>
VCC 21
1.235 V
ESD
protection
element
+
−
CTL 14
6 VREF
37.8
kΩ
ESD
protection
element
12.35
kΩ
GND 23
• <Soft-start block>
VREF
(5.0 V)
33.1
kΩ
51
kΩ
GND
• <Triangular wave
oscillator block>
• <Error amplifier block (Error Amp1) >
VCC
VREF
(5.0 V)
VCC
22 CS
+
−
−INE1 8
FB123
17 RT
GND
GND
GND
9
• <Error amplifier block (Error Amp2) >
+INE1
• <Error amplifier block (Error Amp3) >
VCC
VCC
VREF
(5.0 V)
CS
−INE2 4
FB123
GND
16
4.2 V
15 FB123
GND
3
+INE2
• <Current detection amplifier block
(Current Amp1) >
• <Current detection amplifier block
(Current Amp2) >
VCC
VCC
−INC2 1
−INC1 12
10 OUTC1
GND
2 OUTC2
GND
13 +INC1
24 +INC2
(Continued)
43
MB39A125/126
(Continued)
• <PWM comparator block>
• <Output block>
VCC
VCC
FB123
20 OUT
CT
VH
GND
GND
• <AC adapter voltage detection block>
ACIN
7
VCC
VREF
(5.0 V)
5
18 XACOK
ACOK
GND
• <Bias voltage block>
• <Invalidity current prevention block> • <Output voltage switching function block>
<MB39A125>
<MB39A126>
VCC
11 OUTD
SEL 11
33.1 kΩ
19 VH
51 kΩ
GND
44
GND
GND
MB39A125/126
■ APPLICATION EXAMPLE 1
• MB39A125
IIN
to System
Q2
R14
15 kΩ
C15
0.22 µF
R20
56 kΩ R19 100 kΩ
R17 RS1
51
kΩ 0.015
Ω
R18
24
kΩ
Q3
R15
68 kΩ
ACOK
ACIN
R16
10 kΩ
7
XACOK
5
18
<AC Comp.>
−INE1
C8
6800 pF
R6
10 kΩ
VIN
(8 V to
25 V)
+
+INE1
R11
1.1
kΩ
−
8
10
OUTC1
+INC1 13
A
B −INC1 12
R12
30 kΩ
R13
20
kΩ
R5
100 kΩ
VREF
<Current Amp 1>
+
×20
−
<Error Amp 1>
0.2 V <UV Comp.>
+
−
−
+
−INC1
(Vo)
9
−INE2
4
R8
C10
100 kΩ
6800
pF
2
R7
10 kΩ OUTC2
24
+INC2
1
−INC2
SW2
R9
36 kΩ
R10
20 kΩ
R3
33
kΩ
C13
22 pF
C6
C14
2200 pF 47 pF
<Current Amp 2>
+
×20
−
<Error Amp 2>
−
−2.5 V
−1.5 V
VH
R21
100 kΩ
R22
200 kΩ
−INE3
16
R23
100 kΩ
11
OUTD
(VCC −
6 V)
VCC
21
C12 C7
0.1
µF 0.1
µF
20
OUT
C1
10 µF
A
B
Q1
L1
15 µH
VH
19
D1
C3
10 µF
Bias
Voltage
<Error Amp 3>
ICHG
RS2
0.033
Ω
C4
10 µF
Battery
−
+
<UVLO>
4.2 V
VREF
UVLO
<SOFT>
4.2 V
Bias
Slope
Control
10 µF
VCC
CTL
<OSC>
500 kHz Max
CS
<OUT>
Drive
+
+INE2 3
FB123
15
VREF
C11
0.22 µF
<PWM Comp.>
+
−
<REF>
<CTL>
14
22
VREF
5.0 V
CT
(45 pF)
RT
R4
47 kΩ
17
VREF
6
GND
C9
0.22
µF
23
45
MB39A125/126
■ PARTS LIST 1
• MB39A125
COMPONENT
ITEM
SPECIFICATION
VENDOR
PARTS No.
Q1, Q2, Q3
Pch FET
VDS = −30 V, ID = −7.0 A
NEC
µPA2714GR
D1
Diode
VF = 0.42 V (Max) , At IF = 3 A
ROHM
RB053L-30
L1
Inductor
15 µH
3.6 A, 50 mΩ
SUMIDA
CDRH104R-150
C1, C3, C4
C6
C7, C12
C8, C10
C9, C11
C13
C14
C15
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
10 µF
2200 pF
0.1 µF
6800 pF
0.22 µF
22 pF
47 pF
0.22 µF
25 V
50 V
50 V
50 V
16 V
50 V
50 V
25 V
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
C3225X5R1E106K
C1608JB1H222K
C1608JB1H104K
C1608JB1H682K
C1608JB1C224K
C1608CH1H220J
C1608CH1H470J
C2012JB1E224K
RS1
RS2
R3
R4
R5, R8
R6, R7
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19, R21, R23
R20
R22
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
15 mΩ
33 mΩ
33 kΩ
47 kΩ
100 kΩ
10 kΩ
36 kΩ
20 kΩ
1.1 kΩ
30 kΩ
20 kΩ
15 kΩ
68 kΩ
10 kΩ
51 kΩ
24 kΩ
100 kΩ
56 kΩ
200 kΩ
1%
1%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
KOA
KOA
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
SL1TTE15LOF
SL1TTE33LOF
RR0816P-333-D
RR0816P-473-D
RR0816P-104-D
RR0816P-103-D
RR0816P-363-D
RR0816P-203-D
RR0816P-112-D
RR0816P-303-D
RR0816P-203-D
RR0816P-153-D
RR0816P-683-D
RR0816P-103-D
RR0816P-513-D
RR0816P-243-D
RR0816P-104-D
RR0816P-563-D
RR0816P-204-D
Note : NEC
ROHM
SUMIDA
TDK
KOA
ssm
46
: NEC Corporation
: ROHM CO., LTD.
: Sumida Corporation
: TDK Corporation
: KOA Corporation
: SUSUMU CO., LTD.
MB39A125/126
■ APPLICATION EXAMPLE 2
• MB39A126
IIN
to System
Q2
R14
15 kΩ
R17 RS1
51
kΩ 0.015
R18 Ω
24
kΩ
C15
0.22 µF
R20
56 kΩ R19 100 kΩ
Q3
R15
68 kΩ
XACOK
ACOK
ACIN
R16
10 kΩ
7
5
18
<AC Comp.>
+
−
−INE1
C8
6800 pF
R6
10 kΩ
VIN
(8 V to
25 V)
8
10
OUTC1
+INC1 13
A
12
B
−INC1
R12
30 kΩ
R13
20
kΩ
R5
100 kΩ
+INE1
R11
1.1
kΩ
VREF
<Current Amp 1>
+
×20
−
<Error Amp 1>
0.2 V <UV Comp.>
+
−
−
+
−INC1
(Vo)
9
−INE2
SW2
R9
36 kΩ
R10
20 kΩ
C13
22 pF
4
C10
R8
6800
100 kΩ
pF
2
R7
10 kΩ OUTC2
24
+INC2
1
−INC2
3
+INE2
15
R3
FB123
33
kΩ
C14
47 pF
−INE3
C6
2200 pF
<PWM Comp.>
+
−
<Current Amp 2>
+
×20
−
<Error Amp 2>
−
<OUT>
Drive
+
−2.5 V
−1.5 V
VH
R1
R2
+
B
L1
15 µH
D1
C3
10 µF
ICHG
RS2
0.033
Ω
C4
10 µF
Battery
<UVLO>
4.2 V/3.15 V
VREF
VREF
UVLO
<SOFT>
4.2 V
Bias
Slope
Control
10 µF
VCC
CTL
<OSC>
500 kHz Max
CS
A
Q1
VH
19
Bias
Voltage
<Error Amp 3>
C1
10 µF
−
16
SEL 11
Hi : 4 Cells
Lo : 3 Cells
(VCC −
6 V)
VCC
21
C12 C7
0.1
µF 0.1
µF
20
OUT
<REF>
<CTL>
14
22
VREF
5.0 V
CT
C11
0.22 µF
(45 pF)
RT
R4
47 kΩ
17
VREF
6
GND
C9
0.22
µF
23
47
MB39A125/126
■ PARTS LIST 2
• MB39A126
COMPONENT
ITEM
SPECIFICATION
VENDOR
PARTS No.
Q1, Q2, Q3
Pch FET
VDS = −30 V, ID = -7.0 A
NEC
µPA2714GR
D1
Diode
VF = 0.42 V (Max) , At IF = 3 A
ROHM
RB053L-30
L1
Inductor
15 µH
3.6 A, 50 mΩ
SUMIDA
CDRH104R-150
C1, C3, C4
C6
C7, C12
C8, C10
C9, C11
C13
C14
C15
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
10 µF
2200 pF
0.1 µF
6800 pF
0.22 µF
22 pF
47 pF
0.22 µF
25 V
50 V
50 V
50 V
16 V
50 V
50 V
25 V
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
C3225X5R1E106K
C1608JB1H222K
C1608JB1H104K
C1608JB1H682K
C1608JB1C224K
C1608CH1H220J
C1608CH1H470J
C2012JB1E224K
RS1
RS2
R3
R4
R5, R8
R6, R7
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
15 mΩ
33 mΩ
33 kΩ
47 kΩ
100 kΩ
10 kΩ
36 kΩ
20 kΩ
1.1 kΩ
30 kΩ
20 kΩ
15 kΩ
68 kΩ
10 kΩ
51 kΩ
24 kΩ
100 kΩ
56 kΩ
1%
1%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
KOA
KOA
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
SL1TTE15LOF
SL1TTE33LOF
RR0816P-333-D
RR0816P-473-D
RR0816P-104-D
RR0816P-103-D
RR0816P-363-D
RR0816P-203-D
RR0816P-112-D
RR0816P-303-D
RR0816P-203-D
RR0816P-153-D
RR0816P-683-D
RR0816P-103-D
RR0816P-513-D
RR0816P-243-D
RR0816P-104-D
RR0816P-563-D
Note : NEC
ROHM
SUMIDA
TDK
KOA
ssm
48
: NEC Corporation
: ROHM CO., LTD.
: Sumida Corporation
: TDK Corporation
: KOA Corporation
: SUSUMU CO., LTD.
MB39A125/126
■ SELECTION OF COMPONENTS
• Pch MOS FET
The Pch MOS FET for switching use should be rated for at least +20% more than the input voltage. To minimize
continuity loss, use a FET with low RDS (ON) between the drain and source. For high input voltage and high
frequency operation, on-cycle switching loss will be higher so that power dissipation must be considered. In this
application, the NEC µPA2714GR is used. Continuity loss, on/off switching loss, and total loss are determined
by the following formulas. The selection must ensure that peak drain current does not exceed rated values.
Continuity loss : Pc
= ID2 × RDS (ON) × Duty
PC
On-cycle switching loss : PS (ON)
PS (ON)
=
VD (Max) × ID × tr × fosc
6
Off-cycle switching loss : PS (OFF)
PS (OFF) =
VD (Max) × ID (Max) × tf × fosc
6
Total loss : PT
= PC + PS (ON) + PS (OFF)
PT
Example) Using the µPA2714GR
16.8 V setting
Input voltage VIN (Max) = 25 V, output voltage VO = 16.8 V, drain current ID = 3 A, oscillation frequency fosc = 300 kHz,
L = 15 µH, drain-source on resistance RDS (ON) =: 18 mΩ, tr =: 15 ns, tf =: 42 ns
Drain current (Max) : ID (Max)
ID (Max)
=
Io +
=
3+
=:
3.6 A
VIN − Vo
2L
tON
25 − 16.8
2 × 15 × 10
−6
×
1
300 × 103
× 0.672
Drain current (Min) : ID (Min)
ID (Min)
=
Io−
=
3−
=:
2.4 A
VIN − Vo
2L
tON
25 − 16.8
2 × 15 × 10−6
×
1
300 × 103
× 0.672
49
MB39A125/126
PC = ID2 × RDS (ON) × Duty
= 32 × 0.018 × 0.672
=:
PS (ON)
0.109 W
=
=
=:
PS (OFF) =
=
=:
VD × ID × tr × fosc
6
25 × 3 × 15 × 10−9 × 300 × 103
6
0.056 W
VD × ID (Max) × tf × fosc
6
25 × 3.6 × 42 × 10−9 × 300 × 103
6
0.189 W
PT = PC + PS (ON) + PS (OFF)
=:
0.109 + 0.056 + 0.189
=:
0.354 W
The above power dissipation figures for the µPA2714GR are satisfied with ample margin at 2.0 W.
12.6 V setting
Input voltage VIN (Max) = 22 V, output voltage VO = 12.6 V, drain current ID = 3 A, oscillation frequency fosc = 300 kHz,
L = 15 µH, drain-source on resistance RDS (ON) =: 18 mΩ, tr =: 15 ns, tf =: 42 ns
Drain current (Max) : ID (Max)
ID (Max)
=
Io +
=
3+
=:
3.6 A
VIN − Vo
2L
tON
22 − 12.6
2 × 15 × 10
−6
×
1
300 × 103
× 0.572
Drain current (Min) : ID (Min)
ID (Min)
50
=
Io −
=
3−
=:
2.4 A
VIN − Vo
2L
tON
22 − 12.6
2 × 15 × 10−6
×
1
300 × 103
× 0.572
MB39A125/126
PC = ID2 × RDS (ON) × Duty
= 32 × 0.018 × 0.572
=:
0.093 W
=
PS (ON)
=
=:
PS (OFF) =
=
=:
PT
VD × ID × tr × fosc
6
22 × 3 × 15 × 10−9 × 300 × 103
6
0.050 W
VD × ID (Max) × tf × fosc
6
22 × 3.6 × 42 × 10−9 × 300 × 103
6
0.166 W
= PC + PS (ON) + PS (OFF)
=:
0.093 + 0.050 + 0.166
=:
0.309 W
The above power dissipation figures for the µPA2714GR are satisfied with ample margin at 2.0 W.
The Pch MOS FET for switching use must use the one of more than input voltage +20%.
FET which operates when the AC adapter is connected should select FET which satisfies the current decided
by sense resistance R1 enough. Because FET which operates when the AC adapter is not connected becomes
a supply by the battery, it is necessary to select FET which satisfies the current of the system enough.
In this application, the NEC µPA2714GR is used.
• Inductor
In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor,
but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous
operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value,
which will enable continuous operation under light-loads.
Note that if the inductance value is too high, however, direct current resistance (DCR) is increased and this will
also reduce efficiency. The inductance must be set at the point where efficiency is greatest.
Note also that the DC superimposition characteristic becomes worse as the load current value approaches the
rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing
loss of efficiency.
The selection of rated current value and inductance value will vary depending on where the point of peak efficiency
lies with respect to load current.
Inductance values are determined by the following formulas.
The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the
load current or less.
51
MB39A125/126
Inductance value : L
L
≥
2 (VIN − Vo)
Io
tON
16.8 V output
Example)
2 (VIN (Max) − Vo)
tON
L ≥
Io
≥
2 × (25 − 16.8)
3
×
1
300 × 103
× 0.672
≥ 12.2 µH
12.6 V output
Example)
2 (VIN (Max) − Vo)
L ≥
tON
Io
≥
2 × (22 − 12.6)
3
×
1
300 × 103
× 0.572
≥ 12.0 µH
Inductance values derived from the above formulas are values that provide sufficient margin for continuous
operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore
necessary to determine the load level at which continuous operation becomes possible. In this application, the
SUMIDA CDRH104R-150 is used. The following formula is available to obtain the load current as a continuous
current condition when 15 µH is used.
The value of the load current satisfying the continuous current condition : Io
Io
≥
Vo
2L
tOFF
Example) Using the CDRH104R-150
15 µH (tolerance ± 30%) , rated current = 3.6 A
16.8 V output
Vo
Io ≥
tOFF
2L
≥
16.8
2 × 15 × 10
≥ 0.61 A
52
−6
×
1
300 × 103
×
(1 − 0.672)
MB39A125/126
12.6 V output
Vo
Io ≥
tOFF
2L
12.6
≥
2 × 15 × 10
−6
1
×
300 × 103
×
(1 − 0.572)
≥ 0.60 A
To determine whether the current through the inductor is within rated values, it is necessary to determine the
peak value of the ripple current as well as the peak-to-peak values of the ripple current that affects the output
ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following
formulas.
Peak Value : IL
≥
IL
VIN − Vo
Io +
2L
tON
Peak-to-peak Value : ∆IL
=
∆IL
VIN − Vo
tON
L
Example) Using the CDRH104R-150
15 µH (tolerance ± 30%) , rated current = 3.6 A
Peak Value
16.8 V output
IL
≥
Io +
≥
3+
VIN − Vo
2L
tON
25−16.8
2 × 15 × 10
−6
×
1
300 × 103
× 0.672
≥ 3.6 A
12.6 V output
IL
≥
Io +
≥
3+
VIN − Vo
2L
tON
22 − 12.6
2 × 15 × 10
−6
×
1
300 × 103
× 0.572
≥ 3.6 A
53
MB39A125/126
Peak-to-peak Value
16.8 V output
VIN − Vo
tON
∆IL =
L
=
=:
25 − 16.8
15 × 10
=:
1
300 × 103
× 0.672
1.22 A
12.6 V output
VIN − Vo
∆IL =
L
=
×
−6
tON
22 − 12.6
15 × 10−6
×
1
300 × 103
× 0.572
1.2 A
• Flyback diode
Shottky barrier diode (SBD) is generally used for the flyback diode when the reverse voltage to the diode is less
than 40V. The SBD has the characteristics of higher speed in terms of faster reverse recovery time, and lower
forward voltage, and is ideal for achieving high efficiency. As long as the DC reverse voltage is sufficiently higher
than the input voltage, and the mean current flowing during the diode conduction time is within the mean output
current level, and as the peak current is within the peak surge current limits, there is no problem. In this application
the ROHM RB053L-30 are used. The diode mean current and diode peak current can be obtained by the following
formulas.
Diode mean current : IDi
≥
IDi
Io ×
(1 −
Vo
)
VIN
Diode peak current : IDip
≥
IDip
Vo
(Io +
2L
tOFF)
Example) Using the RB053L-30
VR (DC reverse voltage) = 30 V, mean output current = 3.0 A, peak surge current = 70 A,
VF (forward voltage) = 0.42 V, at IF = 3.0 A
16.8 V output
IDi
≥
Io ×
≥
3×
(1 −
VIN
(1 − 0.672)
≥ 0.984 A
54
Vo
)
MB39A125/126
12.6 V output
IDi
≥
Io ×
≥
3×
(1 −
Vo
VIN
)
(1 − 0.572)
≥ 1.284 A
16.8 V output
IDip
≥
(Io +
Vo
2L
tOFF)
≥ 3.6 A
12.6 V output
IDip
≥
(Io +
Vo
2L
tOFF)
≥ 3.6 A
• Charge current sense resistor
Please note the following in selecting the charge current sense resistance. First of all, meet the electric power
to the flowing current. However, the conversion efficiency deteriorates because the loss in the sense resistance
grows when resistance is adjusted to a too big value. The accuracy of the charge current deteriorates because
the voltage difference of both ends of the sense resistance becomes small when resistance is adjusted to a too
small value oppositely. 33 mΩ of the KOA SL1TTE33LOF is used in this application. The sense resistance value
can be determined by the following formulas.
In this application, 33 mΩ of the KOA SL1TTE33LOF is used.
Sense resistor : RS2
RS2
=
+INE1
20 × Io
Example) When the +INE1 terminal (pin 9) voltage is 2 V and the charge current (Io) is 3.0 A
RS2
=
=
+INE1
20 × Io
2
20 × 3.0
= 33.3 mΩ
55
MB39A125/126
• Input current sense resistor
Please note the following in selecting the input current sense resistance. First of all, meet the electric power to
the flowing current. However, the conversion efficiency deteriorates because the loss in the sense resistance
grows when resistance is adjusted to a too big value. The accuracy of the input current deteriorates because
the voltage difference of both ends of the sense resistance becomes small when resistance is adjusted to a too
small value oppositely. 33 mΩ of the KOA SL1TTE33LOF is used in this application. The sense resistance value
can be determined by the following formulas.
In this application, 15 mΩ of the KOA SL1TTE15LOF is used.
Sense resistor : RS1
RS1
=
+INE2
20 × IIN
Example) When the +INE2 terminal (pin 3) voltage is 1.79 V and the input current (IIN) is 6.0 A
RS1
=
=
+INE2
20 × IIN
1.79
20 × 6.0
= 14.9 mΩ
56
MB39A125/126
■ REFERENCE DATA
Conversion efficiency vs. Charging current
(Constant Voltage mode)
100
Conversion efficiency η (%)
Conversion efficiency η (%)
Conversion efficiency vs. Charging current
(Constant Voltage mode)
95
90
85
80
75
70
65
VIN = 19 V
Vo = 16.8 V setting
60
55
0.1
10
1
90
85
80
75
70
65
VIN = 19 V
Vo = 12.6 V setting
60
55
0.01
0.1
10
1
Charging current IO (A)
Charging current IO (A)
Conversion efficiency vs. Charging voltage
(Constant Current mode)
Conversion efficiency vs. Charging voltage
(Constant Current mode)
Conversion efficiency η (%)
100
95
90
85
80
75
70
65
VIN = 19 V
Io = 3 A setting
60
55
50
0
2
4
6
8
10
12
14
16
100
95
90
85
80
75
70
65
55
50
0
6
8
10
12
14
16
Charging voltage vs. Charging current
Charging voltage vs. Charging current
20
18
16
SW2 = OFF
SW2 = ON
10
8
6
VIN = 19 V
Vo = 16.8 V setting
4
2
0
0.0
4
Charging voltage VO (V)
18
12
2
Charging voltage VO (V)
20
14
VIN = 19 V
Io = 3 A setting
60
18
Charging voltage VO (V)
Conversion efficiency η (%)
95
50
50
0.01
Charging voltage VO (V)
100
0.5
1.0
1.5
2.0
2.5
3.0
Charging current IO (A)
3.5
4.0
18
VIN = 19 V
Vo = 12.6 V setting
16
14
12
10
8
SW2 = ON
SW2 = OFF
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Charging current IO (A)
(Continued)
57
MB39A125/126
Switching waveform (Constant Voltage Mode)
VO = 12.6 V setting
OUT
(V)
15
VO = 16.8 V setting
OUT
(V)
15
OUT
10
10
5
5
0
Pch
Drain
(V)
10
Pch
Drain
VIN = 19 V
Vo = 16.8 V setting
Io = 1.5 A
SW2 = OFF
0
Pch
Drain
(V)
10
5
5
0
0
0
OUT
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 (µs)
Pch
Drain
0
VIN = 19 V
Vo = 12.6 V setting
Io = 1.5 A
SW2 = OFF
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 (µs)
Switching waveform (Constant Current Mode)
VO = 12.6 V setting
OUT
(V)
15
VO = 16.8 V setting
OUT
(V)
15
OUT
10
10
5
5
0
Pch
Drain
(V)
10
0
Pch
Drain
(V)
10
Pch
Drain
VIN = 19 V
Vo = 10.0 V
Io = 3.0 A setting
SW2 = OFF
5
5
0
0
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 (µs)
OUT
Pch
Drain
0
VIN = 19 V
Vo = 10.0 V
Io = 3.0 A setting
SW2 = OFF
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 (µs)
(Continued)
58
MB39A125/126
Soft-start operating waveform (Constant Current Mode)
Vo
(V)
18 lo
(A)
VIN = 19 V
Io = 3 A setting
SW2 = OFF
lo
(A)
5
4
3
2
1
lo
0
CTL
5
5
14
4
12
Vo
0
16
2
CTL
(V)
10
1
16
14
Vo
3
10
Vo
(V)
18
VIN = 19 V
Io = 3 A setting
SW2 = OFF
12
lo
0
10
CTL
(V)
10
CTL
0
10 15
20 25
30 35 40 45
0
50 (ms)
0
5
10 15
20 25
30 35 40 45
50 (ms)
Soft-start operating waveform (Constant Voltage Mode)
lo
(A)
5
Vo
(V)
18 lo
(A)
Vo
4
3
VIN = 19 V
Vo = 16.8 V setting
SW2 = OFF
2
1
lo
0
CTL
0
5
10 15
Vo
(V)
18
Vo
16
5
16
14
4
14
12
3
10
2
CTL
(V)
10
1
12
VIN = 19 V
Vo = 16.8 V setting
SW2 = OFF
10
CTL
(V)
10
lo
0
CTL
0
20 25
30 35 40 45
50 (ms)
0
0
5
10 15
20 25
30 35 40 45
50 (ms)
(Continued)
59
MB39A125/126
(Continued)
Load-step response operation waveform
(C.V mode → C.C mode)
Load-step response operation waveform
(C.C mode → C.V mode)
Io (A)
Vo (V) Io (A)
18
6
16
5
14
4
6
5
Vo
4
Vo
12
3
10
Io
2
VIN = 19 V
Io = 3.0 A setting
SW2 = OFF
CV to CC
1
Io
0
0
2
4
6
8
10
12
14
16
18
VIN = 19 V
Vo = 16.8 V setting
SW2 = OFF
CV to CV
3
Io
2
20 (ms)
14
12
10
2
0
2
10
4
6
8
10
12
14
16
18
20 (ms)
Io (A)
6
VIN = 19 V
Vo = 16.8 V setting
SW2 = OFF
CV to CV
Vo
4
3
0
16
14
12
10
2
Io
1
Io
Vo (V)
18
Vo
5
Io
1
Io
0
0
60
VIN = 19 V
Io = 3.0 A setting
SW2 = OFF
CC to CV
Io
16
4
12
3
0
Vo (V)
18
Vo
Vo
14
Vo
Load-step response operation waveform
(C.V mode → C.V mode)
Io (A)
5
16
1
Load-step response operation waveform
(C.V mode → C.V mode)
6
Vo (V)
18
Vo
2
4
6
8
10
12
14
16
18
20 (ms)
0
2
4
6
8
10
12
14
16
18 20 (ms)
MB39A125/126
■ USAGE PRECAUTIONS
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply negative voltages.
• The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause
abnormal operation.
■ ORDERING INFORMATION
Part number
Package
MB39A125PFV
24-pin plastic SSOP
(FPT-24P-M03)
MB39A125WQN
28-pin plastic QFN
(LCC-28P-M11)
MB39A126PFV
24-pin plastic SSOP
(FPT-24P-M03)
MB39A126WQN
28-pin plastic QFN
(LCC-28P-M11)
Remarks
61
MB39A125/126
■ PACKAGE DIMENSIONS
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
24-pin plastic SSOP
(FPT-24P-M03)
0.17±0.03
(.007±.001)
*17.75±0.10(.305±.004)
24
13
*2 5.60±0.10
7.60±0.20
(.220±.004) (.299±.008)
INDEX
Details of "A" part
+0.20
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.25(.010)
1
"A"
12
0.65(.026)
0.24
.009
+0.08
–0.07
+.003
–.003
0.13(.005)
0~8˚
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.10(.004)
C
2003 FUJITSU LIMITED F24018S-c-4-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
62
MB39A125/126
(Continued)
28-pin plastic QFN
(LCC-28P-M11)
3.50±0.10
(.138±.004)
5.00±0.10
(.197±.004)
5.00±0.10
(.197±.004)
INDEX AREA
3.50±0.10
(.138±.004)
0.25±0.10
(.010±.004)
3-R0.20
(3-R.008)
0.50(.020)
TYP
0.40±0.10
(.016±.004)
1PIN CORNER
(C0.30(C.012))
0.08(.003)
0.02
.0008
C
+0.05
–0.02
+.002
–.0008
0.80(.032)
MAX
0.20(.008)
2004 FUJITSU LIMITED C28068Sc-2-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
63
MB39A125/126
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0511
© 2004 FUJITSU LIMITED Printed in Japan