® Precision Edge 2.5V, 2GHz ANY DIFF. IN-TO-LVDS SY89872U ® PROGRAMMABLE CLOCK DIVIDER/FANOUT Precision Edge SY89872U BUFFER WITH INTERNAL TERMINATION Micrel, Inc. FEATURES ■ Guaranteed AC performance over temperature and voltage: • >2GHz fMAX • < 750ps tPD (matched delay between banks) • < 15ps within-device skew • < 200ps rise/fall time ■ Low jitter design • < 1psRMS cycle-to-cycle jitter • < 10psPP total jitter ■ Unique input termination and VT pin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) ■ Precision differential LVDS outputs ■ Matched delay: all outputs have matched delay, independent of divider setting ■ TTL/CMOS inputs for select and reset/disable ■ Two output banks (matched delay) • Bank A: Buffered copy of input clock (undivided) • Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies ■ 2.5V power supply ■ Wide operating temperature range: –40°C to +85°C ■ Available in 16-pin (3mm × 3mm) MLF® package Precision Edge® DESCRIPTION This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89872U includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89872U is part of Micrel’s high-speed Precision Edge® timing and distribution family. For 3.3V applications, consider the SY89873L. For applications that require an LVPECL output, consider the SY89872U. The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN). Refer to the “Timing Diagram.” APPLICATIONS ■ ■ ■ ■ OC-3 to OC-192 SONET/SDH applications Transponders Oscillators SONET/SDH line cards FUNCTIONAL BLOCK DIAGRAM /RESET, /DISABLE TYPICAL APPLICATION 622MHz/155.5MHz SONET Clock Generator Enable FF Enable MUX QA 622MHz LVPECL Clock In /QA IN /IN QB0 IN Divided by 2, 4, 8 or 16 50Ω VT 50Ω QA 622MHz LVDS /QA Clock Out OC-12 or OC-3 Clock Generator QB 155.5MHz LVDS /QB Clock Out /QB0 QB1 /IN Bank A: 622MHz for OC-12 line card Bank B: 155.5MHz for OC-3 line card (set to divide-by-4) /QB1 VREF-AC S1 Decoder S0 Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-020707 [email protected] or (408) 955-1690 Rev.: D 1 Amendment: /0 Issue Date: February 2007 Precision Edge® SY89872U Micrel, Inc. S0 S1 VCC GND PACKAGE/ORDERING INFORMATION 16 15 14 13 Ordering Information(1) /QB0 2 11 VT QB1 3 10 VREF-AC /QB1 4 9 6 7 8 VCC IN /RESET /DISABLE 12 /QA 1 QA QB0 5 Package Operating Type Range Part Number /IN Package Marking Lead Finish SY89872UMI MLF-16 Industrial 872U Sn-Pb SY89872UMITR(2) MLF-16 Industrial 872U Sn-Pb SY89872UMG(3) MLF-16 Industrial 872U with Pb-Free bar line indicator NiPdAu Pb-Free SY89872UMGTR(2, 3) MLF-16 Industrial 872U with Pb-Free bar line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 16-Pin MLF® (MLF-16) PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 2, 3, 4 QB0, /QB0 QB1, /QB1 Differential LVDS Compatible Outputs: Divide by 2, 4, 8, 16. Unused outputs must be terminated with 100Ω across the pin (Q, /Q). 5, 6 QA, /QA 7, 14 VCC 8 /RESET, /DISABLE 12, 9 IN, /IN 10 VREF-AC 11 VT 13 GND 15, 16 S1, S0 Differential LVDS Compatible Undivided Output Clock. Positive Power Supply: Bypass with 0.1µF/0.01µF low ESR capacitors. Output Reset and Output Enable/Disable: Internal 25kΩ pull-up. Input threshold is VCC/2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In addition, when LOW, Bank A and Bank B will be disabled. Differential Reference Input Clock: Internal 50Ω termination resistors to VT input. See “Input Interface Applications” section. Reference Voltage: Equal to VCC–1.4V (approx.), and used for AC-coupled applications. Maximum sink/source current is 0.5mA. See “Input Interface Applications” section. Termination Center-Tap: For DC-coupled CML and LVDS inputs, leave this pin floating. See “Input Interface Applications” section. Ground. Select Pins: LVTTL/CMOS logic levels. Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2. TRUTH TABLE /RESET /DISABLE S1 S0 Bank A Output Bank B Outputs 1 0 0 Input Clock Input Clock ÷2 1 0 1 Input Clock Input Clock ÷4 1 1 0 Input Clock Input Clock ÷8 1 1 1 Input Clock Input Clock ÷16 0 X X QA = Low, /QA = High(1) QB0 = Low, /QB0 = High(2) QB1 = Low, /QB1 = High(2) Note 1. On the next negative transition of the input signal. Note 2. Asynchronous reset/disable function. (See “Timing Diagram”) M9999-020707 [email protected] or (408) 955-1690 2 Precision Edge® SY89872U Micrel, Inc. Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VCC) .................................. –0.5V to +6.0V Input Voltage (VIN) ......................................... –0.5V to VCC LVDS Output Current (IOUT) .................................... ±10mA Input Current IN, /IN (IIN) .......................................... ±50mA VREF-AC Input Sink/Source Current (IVREF-AC),Note 3 . ±2mA Lead Temperature (soldering, 20sec.) ...................... 260°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage Range ............................ 2.375V to 2.625V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance MLF® (θJA) Still-Air ............................................................. 60°C/W 500lfpm ............................................................ 54°C/W MLF® (ψJB), Note 4 Junction-to-Board ............................................ 32°C/W Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Note 3. Due to the limited drive capability use for input of the same package only. Note 4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. DC ELECTRICAL CHARACTERISTICS(Note 1, 2) TA= –40°C to +85°C; Unless otherwise stated. Symbol Parameter Min Typ Max Units VCC Power Supply Voltage 2.375 2.5 2.625 V ICC Power Supply Current 75 110 mA RIN Differential Input Resistance (IN-to-/IN) 100 110 Ω VIH Input High Voltage IN, /IN Note 3 0.1 VCC+0.3 V VIL Input Low Voltage IN, /IN Note 3 –0.3 VCC+0.2 V VIN Input Voltage Swing Notes 3, 4 0.1 3.6 V VDIFF_IN Differential Input Voltage Swing Notes 3, 4, 5 0.2 |IIN| Input Current IN, /IN Note 3 VREF-AC Reference Voltage Note 6 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Condition No load, max. VCC 90 V 45 VCC –1.525VCC–1.425 VCC–1.325 mA V The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Due to the internal termination (see “Input Buffer Structure” section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! See “Timing Diagram” for VIN definition. VIN (max.) is specified when VT is floating. See Figures 1c and 1d for VDIFF definition. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin. M9999-020707 [email protected] or (408) 955-1690 3 Precision Edge® SY89872U Micrel, Inc. LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS(Note 1, 2) VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOUT Output Voltage Swing Note 5 250 350 450 mV VOH Output High Voltage Note 3 1.475 V VOL Output Low Voltage Note 3 0.925 VOCM Output Common Mode Voltage Note 4 1.125 1.375 V ∆VOCM Change in Common Mode Voltage –50 50 mV Note 1. Note 2. Note 3. Note 4. Note 5. V The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Measured as per Figure 1a, 100Ω across Q and /Q outputs. Measured as per Figure 1b. See Figure 1c. LVTTL/CMOS INPUTS DC ELECTRICAL CHARACTERISTICS(Note 1, 2) VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter VIH Min Typ Max Units Input HIGH Voltage 2.0 – VCC V VIL Input LOW Voltage 0 – 0.8 V IIH Input HIGH Current –125 – 20 µA IIL Input LOW Current – – –300 µA Note 1. Note 2. Condition The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. M9999-020707 [email protected] or (408) 955-1690 4 Precision Edge® SY89872U Micrel, Inc. AC ELECTRICAL CHARACTERISTICS(Note 1, 2) VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Toggle Frequency Output Swing: ≥200mV Maximum Input Frequency Typ Max Units 2 GHz Note 3 3.2 GHz Differential Propagation Delay IN to Q Input Swing: <400mV 500 625 750 ps Input Swing: ≥400mV 450 575 700 ps Within-Device Skew (differential) (QB0-to-QB1) Note 4 7 15 ps Within-Device Skew (differential) (Bank A-to-Bank B) Note 4 12 30 ps Part-to-Part Skew (differential) Note 4 250 ps trr Reset Recovery Time Note 5 Tjitter Cycle-to-Cycle Jitter Note 6 1 psRMS Total Jitter Note 7 10 psPP 200 ps tPD tSKEW tr, tf Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. 600 Rise / Fall Time (20% to 80%) 70 ps 130 Measured with 400mV input signal, 50% duty cycle. 100Ω termination between Q and /Q, unless otherwise stated. Specification packaged product only. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output ÷2, ÷4, ÷8, ÷16) can accept an input frequency >3GHz, while Bank A will be slew rate limited. Skew is measured between outputs under identical transitions. See “Timing Diagram.” Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn–Tn+1, where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, of frequency ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. M9999-020707 [email protected] or (408) 955-1690 5 Precision Edge® SY89872U Micrel, Inc. LVDS OUTPUT 50Ω VOUT 100Ω 50Ω VOH, VOL VOCM, ∆VOCM VOH, VOL GND GND Figure 1a. LVDS Differential Measurement Figure 1b. LVDS Common Mode Measurement DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING VIN, VOUT VDIFF_IN, VDIFF_OUT 350mV (typical) 700mV (typical) Figure 1d. Differential Swing Figure 1c. Single-Ended Swing TIMING DIAGRAM VCC/2 /RESET tRR IN /IN VIN Swing tPD /QB VOUT Swing QB QA /QA M9999-020707 [email protected] or (408) 955-1690 6 Precision Edge® SY89872U Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS VCC = 2.5V, VIN = 400mV, TA = 25°C, unless otherwise stated. 250 200 150 100 50 600 550 800 600 400 200 0 3500 3000 2500 2000 1500 500 1000 500 0 0 650 600 575 550 525 500 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) INPUT SWING (mV) FREQUENCY (MHz) QA @622MHz and QB @155.5MHz (Divide-by-4) QA 1400 300 1200 PROPAGATION DELAY (ps) QA AMPLITUDE (mV) 350 PROPAGATION DELAY (ps) 700 400 IN to Q Propagation Delay vs. Temperature IN to Q Propagation Delay vs. Input Swing 1000 QA Output Amplitude vs. Frequency 1.25GHz Output 622MHz Output /QA QB0 Output Swing (50mV/div.) Output Swing (100mV/div.) /Q 155.5MHz Output Q /QB0 TIME (150ps/div.) TIME (1ns/div.) 2GHz Output Output Swing (50mV/div.) /Q Q TIME (100ps/div.) M9999-020707 [email protected] or (408) 955-1690 7 Precision Edge® SY89872U Micrel, Inc. INPUT BUFFER STRUCTURE VCC 1.86kΩ VCC 1.86kΩ 25kΩ R S0 S1 /RESET 1.86kΩ 1.86kΩ R IN 50Ω VT 50Ω GND GND /IN Figure 2a. Simplified Differential Input Buffer M9999-020707 [email protected] or (408) 955-1690 Figure 2b. Simplified TTL/CMOS Input Buffer 8 Precision Edge® SY89872U Micrel, Inc. INPUT INTERFACE APPLICATIONS VCC VCC VCC VCC VCC VCC IN PECL IN IN CML /IN CML /IN SY89872U GND SY89872U /IN SY89872U GND VCC NC VT NC VREF-AC VT 0.01µF VT VREF-AC 50Ω NC VCC VCC VREF-AC VCC * Bypass with 0.01µF to GND 0.01µF Figure 3a. DC-Coupled CML Input Interface VCC–2V* GND Figure 3b. AC-Coupled CML Input Interface VCC VCC Figure 3c. DC-Coupled PECL Input Interface VCC VCC IN IN IN HSTL LVDS PECL /IN /IN /IN 50Ω SY89872U SY89872U SY89872U 50Ω GND VCC VT GND NC VT NC VREF-AC VT NC GND GND VREF-AC GND 0.01µF Figure 3d. AC-Coupled PECL Input Interface VREF-AC Figure 3e. LVDS Input Interface Figure 3f. HSTL Input Interface RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89871U 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/Fanout Buffer w/Internal Termination http://www.micrel.com/product-info/products/sy89871u.shtml 3.3V, 2GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer http://www.micrel.com/product-info/products/sy89873l.shtml MLF® http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf SY89873L HBW Solutions Application Note New Products and Applications M9999-020707 [email protected] or (408) 955-1690 http://www.micrel.com/product-info/products/solutions.shtml 9 Precision Edge® SY89872U Micrel, Inc. 16-PIN MicroLeadFrame® (MLF-16) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. Note 2. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-020707 [email protected] or (408) 955-1690 10