SC2616 Complete DDR Power Solution POWER MANAGEMENT Description Features The SC2616 is a fully integrated DDR power solution providing power for the VDDQ and the VTT rails. The SC2616 also completely adheres to the ACPI sleep state power requirements. A synchronous buck controller provides the high current of the VDDQ at high efficiency, while a linear sink/source regulator provides the termination voltage with 2 Amp Source/Sink capability. This approach makes the best trade-off between cost and performance. Additional logic and UVLOs complete the functionality of this single chip DDR power solution in compliance with SLP_S3 and SLP_S5 motherboard signals. High efficiency (90%) switcher for VDDQ supplies 20 Amps High current gate drives Single chip solution complies fully with ACPI power The SC2616 is capable of sourcing up to 20A at the switcher output, and 2A source/sink at the VTT output. The MLP package provides excellent thermal impedance while keeping small footprint. VDDQ current limit as well as 3 independent thermal shutdown circuits assure safe operation under all fault conditions. sequencing specifications Internal S3 state LDO supplies high standby VDDQ current (0.65 Amp Min.) ACPI sleep state controlled 2 Amp VTT source/sink capability UVLO on 5V and 12V Indepent thermal shutdown for VDDQSTBY and VTT Fast transient response 18 pin MLP package Applications Power solution for DDR memory per ACPI motherboard specification High speed data line termination Memory cards Typical Application Circuit 5VCC R1 12VCC Q1 5VSBY R3 R9 Cin C8 U1 16 0 4 C18 SC2616 5VCC 12VCC TG 5VSBY BG PGND 11 SLP_S3# 10 SLP_S5# SLP_S3 VDDQSTBY SLP_S5 VDDQIN FB LGN D PAD VTT VTT October,13, 2003 0 0 VDDQ 0 0 15 14 R7 Q3 L1 Cout 13 7 8 0 1 2 5 R5 0 6 C15 C14 C6 0 Q2 9 1k VTT 3 0.1uF R2 COMP AGN D C5 VTTSNS 19 17 SS/EN 12 18 R4 R8 1k 0 0 1 www.semtech.com SC2616 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Supply Voltage, 5VCC to AGND V 5V C C 7 V Supply Voltage, 12VCC to AGND V 12V C C 15 V Standby Input Voltage V 5V S B Y 7 V I/O 5VSTBY +0.3, AGND -0.3 V 0.3 V IO(VTT) ±3 A Operating Ambient Temperature Range TA 0 to 70 °C Operating Junction Temperature TJ 125 °C Thermal Resistance Junction to Ambient θJA 25 ° C/W Thermal Resistance Junction to Case θJC 4 ° C/W Storage Temperature TSTG -65 to 150 °C TG/BG DC Voltage 12Vcc + 0.3, AGND -0.5 V TG/BG AC Voltage, t ≤ 100ns 12Vcc + 1.0, AGND -2.0 V 2 kV Inputs AGND to PGND or LGND VTT Output Current ESD Rating (Human Body Model) ESD Electrical Characteristics Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter Symbol Conditions Min Typ Max Units 5V Supply Voltage V 5V C C 4.5 5 5.5 V 12V Supply Voltage V 12V C C 10 12 14 V 5V Standby Voltage V 5V S B Y 4.5 5 5.5 V Quiescent Current IQ(5VSBY) S 0, S 5 5.2 mA S3, IDDQSTBY = 0 7.8 mA SLP_S3 Threshold TTL V SLP_S5 Threshold TTL V 50 µA SLP_S3/SLP_S5 Input Current © 2003 Semtech Corp. IS3,S5 2 www.semtech.com SC2616 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter Symbol Conditions Min Typ Max Units 8 9.2 10 V 12VCC Under Voltage Lockout UVLO12VCC 5VCC Under Voltage Lockout UVLO5VCC 2.5 V VREF 1.25 V Feedback Reference Feedback Current IFB VFB = 1.25V 0.5 µA SS/EN Shutdown Threshold VEN(TH) 0.3 V Thermal Shutdown TJ-SHDN 150 °C Thermal Shutdown Hysteresis TJ-HYST 10 °C 0.2 % Sw itcher Load Regulation IVDDQ = 0A to 10A; S0 Oscillator Frequency fOSC Soft Start Current ISS 225 250 275 25 Duty Cycle 0 KHz µA 95 % 80 % Overcurrent Trip Voltage VTRIP % of VDDQ Setpoint Top Gate Rise Time TGR Gate capacitance = 4000pF 25 nS Top Gate Fall Time TGF Gate capacitance = 4000pF 25 nS Bottom Gate Rise Time BGR Gate capacitance = 4000pF 35 nS Bottom Gate Fall Time BGF Gate capacitance = 4000pF 35 nS 50 nS 0.8 mS 38 dB 5 MHz ±60 µA Dead Time td Error Amplifier Transconductance GM Error Amplifier Gain @ DC A EA Error Amplifier Bandwidth GBW 20 RCOMP = open Error Amplifier Source/Sink Current © 2003 Semtech Corp. 70 3 75 www.semtech.com SC2616 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter Symbol Conditions VRAMP Peak to Peak IVDDQSTBY DC current ∆ V/∆I Min Typ Max Units Sw itcher (Cont.) PWM Ramp 0.55 V S TB Y LD O Output Current Load Regulation Current Limit 650 750 850 mA IVDDQ = 0A to 460mA; S3 0.3 0.5 % ILIM S LP _S 3 = 0 2.3 VTT VVDDQSTBY = 2.500V 1.237 1.250 1.267 IVTT = 1.8A to -1.8A 1.225 1.250 1.275 A V TT LD O Output Voltage Source and Sink Currents Load Regulation ∆ VTT/ ∆I Error Amplifier Gain AEA_VTT Current Limit VTTILIM © 2003 Semtech Corp. ±1.8 IVTT IVTT =+1.8A to -1.8A ±0.5 75 SLP_S3 = high (sink) 3 SLP_S3 = high (source) 3 4 V ±2 A ±1.0 % dB A www.semtech.com SC2616 POWER MANAGEMENT Pin Configuration Ordering Information TOP VIEW FB 1 18 SS/EN VTTSNS 2 17 COMP LGND 3 16 12VCC 5VSBY 4 15 TG VTT 5 14 BG VTT 6 13 PGND VDDQSTBY 7 12 AGND VDDQIN 8 11 SLP_S3 5VCC 9 10 SLP_S5 Part Numbers P ackag e SC2616MLTR(1) MLP-18 Note: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (18 Pin MLP) Note: Pin 19 is the thermal Pad on the bottom of the device Pin Descriptions Pin # Pin Name 1 FB 2 VTTSNS 3 LGND VTT return. Connect to point of load return. The trace connecting to this pin must be able to carry 2A of current. 4 5V S B Y Bias supply for the chip. Connect to 5V standby. 5, 6 VTT 7 Pin Function Feedback for the STBY LDO and the switcher for VDDQ. VTT LDO feedback and remote sense input. VTT output. Connect to point of load. The trace connecting to this pin must be able to carry 2A of current VDDQSTBY S3 VDDQ output. Provision must be made to prevent the VDDQSTBY supply from back feeding the input supply (see typical application schematic). Traces connecting to this pin must be capable of carring 0.85A of current. 8 VDDQIN 9 5V C C 10 S LP _S 5 Connect to SLP_S5 signal from motherboard. 11 S LP _S 3 Connect to SLP_S3 signal from motherboard. 12 AGND Analog ground. 13 PGND Gate drive return. Keep this pin close to bottom FET source. 14 BG Bottom gate drive. 15 TG Top gate drive. 16 12V C C Supply to the upper and lower gate drives. 17 COMP Compensation pin for the PWM transconductance amplifier. 18 SS/EN Soft start capacitor to AGND. Pull low to less than 0.3V to disable the controller. 19 TH_PAD © 2003 Semtech Corp. VDDQ power input to VTT LDO. The trace connecting to this pin must be able to carry 2 A of current. Supply to the lnternal logic Copper pad on bottom of chip used for heatsinking. This pin must be connected to ground plane under IC. (See application information). 5 www.semtech.com SC2616 POWER MANAGEMENT Block Diagram E/A © 2003 Semtech Corp. 6 www.semtech.com SC2616 POWER MANAGEMENT Timing Diagram UVLO 5V,12V Rails SLP_S3 SLP_S5 1.25V 1.0V 0.3V SS/EN Internal PGOOD TG BG VDDQSTBY VTT Vddqsb Vddqsw VDDQ S5 © 2003 Semtech Corp. S0 S3 7 S0 S5 www.semtech.com SC2616 POWER MANAGEMENT Applications Information supplies(5V and 12V), since both supplies have to be higher than their UVLO thresholds for proper start-up. Description The Semtech SC2616 DDR power supply controller offers a switching and linear regulator combination to provide the necessary functions to comply with S3 and S5 sleep state signals generated by the Desktop Computer Motherboards. VDDQ supply, and VTT termination voltage are supplied to the Memory bus during S0 (normal operation) state. During S0, VDDQ is supplied via the Switching regulator, sourcing high output currents to the VDDQ bus as well as supplying the termination supply current. The SC2616 is capable of driving a 4000pf capacitor in 25ns (typical, top gate). This drive capability allows 15-20A DC load on the VDDQ supply. The VTT termination voltage is an internal sink/source linear regulator, which during S0 state receives its power from the VDDQ bus. It is capable of sourcing and sinking 2 Amps (max). The current limit on this pin is set to 3 Amps (typical). Initial Conditions and Event Sequencing The main switcher will start-up in Asynchronous Mode when the voltage on SS/EN pin is greater than ~0.3V. The SS/EN will go high only after the 5Vcc and 12Vcc are higher than their respective UVLO thresholds. The switcher achieves maximum duty cycle when SS/EN reaches 0.8V. When the SS/EN equals 1.25V, the synchronous FET will also be activated. When the SLP_S5 and SLP_S3 go high for the first time, the VDDQ is supplied by the switcher, thus removing the burden of charging the output capacitors via the linear regulator. An internal latch guarantees that the supply goes through S0 state for the first time. During a transition from S3 to S0, where the 5V and 12V rails and subsequently the SS/EN pin go high, the internal VDDQ standby supply will remain ”on” until SS/EN has reached 1V, at which point only the switcher is supplying VDDQ , and the internal “power good” indicator goes high. Output Current and PCB layout The current handling capacity of SC2616 depends upon the amount of heat the PC board can sink from the SC2616 thermal pad. (See thermal considerations). The PC board layout must take into consideration the high current paths, and ground returns for both the VDDQ and VTT supply pins. VTT, LGND, VDDQ, 5VCC and PGND traces must also be routed using wide traces to minimize power loss and heat in these traces, based on the current handling requirements. The “Memory” activity should be slaved off the “Power OK” signal from the Silver Box supply, and since the “Power OK” is asserted after all supplies are within close tolerance of their final values, the VDDQ switcher should have been running for some time before the memory is activated. This is true for typical SS/EN capacitor values (10nf to 220nf). Thus during transitions from S3 to S0, the concern that the VDDQ Standby supply may have to provide high currents before the switcher is activated is alleviated. S3 and S5 States During S3 and S5 sleep states, the operation of the VDDQ and VTT supplies is governed by the internal sequencing logic in strict adherence with motherboard specifications. The timing diagram demonstrates the state of the controller, and each of the VDDQ and VTT supplies during S3 and S5 transitions. When SLP_S3 is low, the VDDQ supplies the “Suspend To RAM” current of 650 mA (min) to maintain the information in memory while in standby mode. The VTT termination voltage is not needed during this state, and is thus tri-stated during S3. Once SLP_S3 goes high, the VDDQ switcher recovers and takes control of the VDDQ supply voltage. When SLP_S5 and SLP_S3 are both pulled low, all supplies shut down. The SS/EN pin must be pulled low (<0.3V) and high again to restart the SC2616. This can be achieved by cycling the input © 2003 Semtech Corp. The logic inputs to SLP_S3 and SLP_S5 pins must be defined before application of power to the SC2616. This can be guaranteed by pulling up the SLP_S3 and SLP_S5 inputs to 5VStandby. If the chipset that asserts these signals is powered after the SC2616 powers up, and SLP_S3 and SLP_S5 are not pulled up, erroneous startup and operation can result. Care must be taken not to exceed the maximum voltage/ current specifications of the interface inputs supplying these signals. The pullup voltage and resistor must be chosen such that when high, the S3 and S5 do not “back drive” the interface chipset (Southbridge, etc.) and the 8 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) maximum voltage applied to these pins do not exceed the chipsets specifications. A separate lower pullup supply may be necessary to avoid damage to the chipset. that will give an inductor ripple current of approximately 20% of max. output current. Inductor ripple current is given by:- “Back Feeding” the Input Supply IL RIPPLE When in S3 state, VDDQ is supplied by the linear regulator and current can flow back from the VDDQ supply through the body diode of the Top switching MOSFET to the 5V supply of the Silver Box, which is off during the S3 state. This in turn shorts out the VDDQ supply and is not acceptable. ⎛ V ⎞ VO ⋅ ⎜⎜1 − O ⎟⎟ ⎝ VIN ⎠ = L ⋅ fOSC So choose inductor value from:⎛ V ⎞ 5 ⋅ VO ⋅ ⎜⎜1 − O ⎟⎟ ⎝ VIN ⎠ L= IO ⋅ fOSC OUTPUT CAPACITOR(S) - The output capacitors should be selected to meet output ripple and transient response criteria. Output ripple voltage is caused by the inductor ripple current flowing in the output capacitor’s ESR (There is also a component due to the inductor ripple current charging and discharging the output capacitor itself, but this component is usually small and can often be ignored). Given a maximum output voltage ripple requirement, ESR is given by:- An addittional MOSFET should be addded to avoid the reverse current flow. The MOSFETs should have the drains to each other(common- Drain). During S0 to S3 transition, As soon as SLP_S3 signal goes low, BG signal stops chopping. This can prevent the inductor to build up its current in the reverse direction. To avoid the MOSFET damaged by overshoot, the input bulk capacitor must be added to the node of common Drain. RESR < Current Limit L ⋅ fOSC ⋅ VRIPPLE ⎛ V ⎞ VO ⋅ ⎜⎜1 − O ⎟⎟ V IN ⎠ ⎝ Output voltage transient excursions are a function of load current transient levels, input and output voltages and inductor and capacitor values. Current limit is implemented by sensing the VDDQ voltage. If it falls to 75% off its nominal voltage, as sensed by the FB pin, the TG and BG pins are latched off and the switcher and the linear converters are shut down. To recover from the current limit condition, either the power rails, 5VCC or 12VCC have to be recycled, or the SS/EN pin must be pulled low and released to restart switcher operation. Capacitance and RESR values to meet a required transient condition can be calculated from RESR < VT IT L ⋅ IT2 2 ⋅ VT ⋅ VA Thermal Shutdown C> There are three independent Thermal Shutdown protection circuits in the SC2616: the VDDQ linear regulator, the VTT source regulator, and the VTT sink regulator. If any of the three regulators’ temperature rises above the threshold, that regulator will turn off independently, until the temperature falls below the thermal shutdown limit. where VA = VIN − VO for negative transients (load application) and VA = VO for positive transients (load release) values for positive and negative transients must be calculated seperately and the worst case value chosen. For Capacitor values, the calculated value should be doubled to allow for duty cycle limitation and voltage drop issues. OUTPUT INDUCTOR - A good starting point for output filter component selection is to choose an inductor value © 2003 Semtech Corp. 9 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accomplish the goal: Compensation Components Gpwm L EA R Vbg 1.25Vdc R1 Rc Vin C Co (1) Calculate the corner frequency of the output filter: Ro R2 The control model of SC2616 can be depicted in Fig. 1. This model can also be used in Spice kind of simulator to generate loop gain Bode plots. The bandgap reference is 1.25 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed gain of: 0.0008A ⋅ V The compensation network includes a resistor and a capacitor in series, which terminates from the output of the error amplifier to the ground. This device uses voltage mode control with input voltage feed forward. The peak-to-peak ramp voltage is proportional to the input voltage, which results in an excellent performance to reject input voltage variation. The PWM gain is inversion of the ramp amplitude, and this gain is given by: G pwm 2⋅ π⋅ L⋅ C o F esr := V ramp The total control loop-gain can then be derived as follows: L Ro 2 s . L. C o . 1 2⋅ π⋅ R c⋅ C o F esr < F sw 5 If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter. (4) Choose the loop gain cross over frequency (0 dB frequency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency : F x_over ≤ F sw 5 If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as: ⎛ F esr ⎞ R := ⋅⎜ G pwm ⋅ V in⋅ G m ⎝ F o ⎠ 1 s. R c. C o 1 s. R c. C o 1 (3) Check that the ESR zero frequency is not too high. 1 where the ramp amplitude (peak-to-peak) is 0.55 volts when input voltage is 5 volts. 1 s. R. C . T( s) T o . s. R. C 1 (2) Calculate the ESR zero frequency of the output filter capacitor: Fig. 1. SC2616 control model. G m := F o := 1 Rc 2 ⎛ F x_over ⎞ ⎛ V o ⎞ ⋅⎜ ⎝ F esr ⎠ ⎝ V bg ⎠ ⋅⎜ Ro when where ⎛ V bg ⎞ F o < F esr < F x_over T o := G m⋅ G pwm ⋅ V in⋅ R ⋅ ⎜ ⎝ Vo ⎠ © 2003 Semtech Corp. 10 www.semtech.com SC2616 F.o POWER MANAGEMENT Applications Information (Cont.) or Step 1. Output filter corner frequency ⎛ Fo ⎞ R := ⋅⎜ G pwm ⋅ V in⋅ G m ⎝ F esr ⎠ 1 2 ⎛ F x_over ⎞ ⎛ V o ⎞ ⋅⎜ ⎝ F o ⎠ ⎝ V bg ⎠ Fo = 1.13 KHz ⋅⎜ Step 2. ESR zero frequency: when Fesr = 4.019 KHz F esr < F o < F x_over Step 3. Check the following condition: (5) The compensation capacitor is determined by choosing the compensator zero to be about one fifth of the output filter corner frequency: F esr < F sw 5 Which is satisfied in this case. F zero F o 1 . . . 2 π R F C Step 4. Choose crossover frequency and calculate compensator R: 5 (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equations provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. An example is given below to demonstrate the procedure introduced above. The parameters of the power supply are given as: V V I F in o o sw Fx_over = 50 KHz zero R = 43.197 KΩ Step 5. Calculate the compensator C: C = 16.287 nF Step 6. Generate Bode plot and check the phase margin. In this case, the phase margin is about 85°C that ensures the loop stability. Fig. 2 shows the Bode plot of the loop. := 5 V := 2.5 V := 20 A := 250 KHz L := 3 µH C R R R © 2003 Semtech Corp. o := 6600 µF c := 0.006 Ω 1 := 1.0 KΩ 2 := 1.0 KΩ 11 www.semtech.com SC2616 POWER MANAGEMENT Loop Gain Mag (dB) 100 mag ( i ) 50 0 50 10 100 Fi 4 1 . 10 5 1 . 10 6 1 . 10 Loop Gain Phase (Degree) 0 phase ( i ) 3 1 . 10 45 90 135 180 10 100 3 1 . 10 Fi 4 1 . 10 5 1 . 10 6 1 . 10 Fig. 2. Bode plot of the loop © 2003 Semtech Corp. 12 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) Evaluation Board Schematic 5VCC 5VCC 5VSBY 0 C13 1uF 8 VDDQ C17 1uF BG VTT PGND VDDQSTBY AGND VDDQIN 5VCC SLP_S3 SLP_S5 15 L1 3uH Q3 14 13 R7 2R2 12 11 10 VDDQ 0 0 R6 2R2 C16 1n C9 C10 C11 C12 R5 1k FB R8 1k SLP_S3 SLP_S5 0 SC2616 R9 2R2 0 5VCC 0 C18 1uF 19 0 9 VTT 2R2 4 .7 u F /6 .3 V 7 TG 16 R4 4 .7 u F /6 .3 V 6 5VSBY C8 0 1uF Q2 C4 3 3 0 0 u F /6 .3 V 1 5 0 0 u F /6 .3 V C15 4.7uF 12VCC 17 R3 2R2 C3 3 3 0 0 u F /6 .3 V 5 LGND R2 43K IP P 06N 03LA VTT COMP PAD 4 VTTSNS 18 C2 4 .7 u F /6 .3 V 0 3 SS/EN C1 1 5 0 0 u F /6 .3 V 2 FB 12VCC 1 5 0 0 u F /6 .3 V 1 0 1 5 0 0 u F /6 .3 V U1 C7 C19 IP D 09N 03LA FB C6 15n non pop. 0 0.1uF C5 C14 2R2 R13 2.2R Q1 R1 4 .7 u F /6 .3 V 12VCC IP D 1 3 N 0 3 L 1N 4148 D1 0 Guidelines for Layout of DDR Supply Using SC2616 DDR Controllers on Typical Motherboards Signals of arbitrary importance (signals that can be routed last, such as SLP_S3, SLP_S5, 5VCC) have been omitted for simplicity. Parameters of importance in the Layout of the DDR power section are as follows (in order of importance): 1. The VTT decoupling cap,C15, must be placed less than 0.25 inch from Controller. 2. The power rail decoupling cap,C4, must be placed less than 0.25 inch from Q2 drain. 3. The decoupling caps for 5VSBY AND 12Vcc,C13 and C8, must be placed very close to the controller(0.25inch or less) 4. The VDDQ sense lines must be routed from a distant © 2003 Semtech Corp. load point (do not connect to the inductor output at the VDDQ plane near the controller/FETS. Place the voltage divider at the load point and route the divider center and the sense ground close together as a differential pair. Connect the AGND and the sensed ground and LGND at the chip. 5. The VTTSNS must be connected to a distant load point. 6. Adequate copper area must be allocated to both VDDQ and VTT. The copper coverage must be uniform, i. e. it provides low resistance to all areas around the DIMMs. VDDQIN traces (and vias if used to carry current) must be adequate for 2.0Amps. 7. Make the phase node area, which connects the Inductor, Top FET and the Bottom FET, as small as possible to prevent EMI, and ringing. Avoid making this 13 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) connection using Vias, to minimize inductance. 8. Route gate drive traces on the Top layer as much as possible, with traces 25 mil or wider. If Vias are used, use multiple vias. While gate drive resistors are not required, they may be needed to reduce ringing if the traces are long and inductive. 9. Place components R2,C5, C6 and C7 near the controller, preferably on an analog ground island. 10. Keep Input electrolytic capacitors near the FETs, to minimize AC current loops. The traces connecting to pins 9, 10, 11 are not critical, since low currents flow in these paths. Thermal considerations 11. The controller must be placed on a copper land, with at least 0.5” square area. Remove the Soldermask under the IC, as shown in the recommend landing pattern in this datasheet. The Solder-mask cutout area(also referred as stencil aperture) allows the Ground contact at the bottom of the controller (pin 19) to be directly soldered to the PC board for heatsinking to the PC board. There must be at least 5 vias connecting the top and bottom layers on this plane to reduce thermal resistance. These thermal vias must be minimum diameter for the PCB process(12mil drill for 62mil thick PCB). Also it is better to plug the vias by copper plating and solder plating. Making the soldermask cutout area too large will add to the risk of solder flowing near the pins and causing shorted connections. 12. The FETs must be placed on a copper area large enough to adequately transfer heat from the FETs to the PC board. Multiple vias aid in cooling the copper area surrounding the FETs, thus reducing the FETs’ junction to ambient thermal resistance. © 2003 Semtech Corp. 14 www.semtech.com SC2616 POWER MANAGEMENT Outline Drawing - MLP-18 TERMINAL 1 IDENTIFIER TOP VIEW TERMINAL 1 BOTTOM VIEW 1 CONTROLLING DIMENSIONS: MILLIMETERS © 2003 Semtech Corp. 15 www.semtech.com SC2616 POWER MANAGEMENT Recommended Land Pattern - MLP-18 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 © 2003 Semtech Corp. 16 www.semtech.com