STS9D8NH3LL Dual N-channel 30 V - 0.012 Ω - 9 A - SO-8 low on-resistance STripFET™ Power MOSFET Features Type STS9D8NH3LL VDSS RDS(on) Qg ID Q1 30V < 0.022Ω 7nC 8A Q2 30V < 0.015Ω 8nC 9A ■ Optimal RDS(on) x Qg trade-off @ 4.5V ■ Conduction losses reduced ■ Switching losses reduced S0-8 Application ■ Switching applications Figure 1. Description Internal schematic diagram This device uses the latest advanced design rules of ST’s STrip based technology. The Q1 and Q2 transistors, show respectively, the best gate charge and on-resistance for minimizing the switching and conduction losses. This application specific Power MOSFET has been designed to replace two SO-8 packages in DC-DC converters. Table 1. Device summary Order code Marking Package Packaging STS9D8NH3LL 9D8H3LL- SO-8 Tape & reel December 2007 Rev 3 1/14 www.st.com 14 Contents STS9D8NH3LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 5 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/14 ................................................ 8 STS9D8NH3LL 1 Electrical ratings Electrical ratings Table 2. Symbol Absolute maximum ratings Parameter Type Value Unit VDS Drain-source voltage (vGS = 0) Q1 Q2 30 30 V V VGS Gate- source voltage Q1 Q2 ±16 ±16 V V ID Drain current (continuous) at TC = 25°C Q1 Q2 8 9 A A ID Drain current (continuous) at TC = 100°C Q1 Q2 5 6.3 A A IDM (1) Drain current (pulsed) Q1 Q2 32 36 A A PTOT Total dissipation at TC = 25°C Q1 Q2 2 2 W W EAS(2) Single pulse avalanche energy 150 mJ Value Unit Thermal resistance junction-ambient max 62.5 °C/W Thermal operating junction-ambient 150 °C -55 to 150 °C 1. Pulse width limited by safe operating area 2. Starting TJ = 25 °C, ID = 7.5 A Table 3. Thermal data Symbol Rthj-a (1) TJ Tstg Parameter Storage temperature 1. When mounted on 1 inch² FR-4 board, 2 oz. Cu., t < 10s 3/14 Electrical characteristics 2 STS9D8NH3LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol Parameter Test conditions Type Min. 30 30 Typ. Max. Unit Drain-source Breakdown voltage ID = 250 µA, VGS = 0 Q1 Q2 IDSS Zero gate voltage Drain current (VGS = 0) VDS = Max rating Q1 Q2 1 1 µA µA IDSS Zero gate voltage Drain current (VGS = 0) VDS =Max rating @125°C Q1 Q2 10 10 µA µA IGSS Gate-body leakage current (VDS = 0) VGS = ± 16 V Q1 Q2 ±100 ±100 nA nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA Q1 Q2 RDS(on) Static drain-source on resistance VGS = 10 V, ID = 4 A VGS = 10 V, ID = 4.5 A Q1 Q2 0.018 0.012 0.022 0.015 Ω Ω RDS(on) Static drain-source on resistance VGS = 4.5 V, ID = 4 A VGS = 4.5 V, ID = 4.5 A Q1 Q2 0.020 0.014 0.025 0.0175 Ω Ω Test conditions Type Typ. Max. V(BR)DSS Table 5. Symbol 4/14 On/off states V V 1 1 V V Dynamic Parameter Min. Unit Q1 Q2 857 1070 pF pF Q1 Q2 147 290 pF pF Reverse transfer capacitance Q1 Q2 20 34 pF pF Qg Total gate charge Q1 Q2 7 8 Qgs Gate-source charge Q1 Q2 2.5 2 nC nC Qgd Gate-drain charge Q1 Q2 2.3 2.8 nC nC Ciss Input capacitance Coss Output capacitance Crss VDS = 25 V, f = 1 MHz, VGS = 0 VDD = 15 V, ID = 8 A, VGS = 4.5 V (see Figure 25) 10 11 nC nC STS9D8NH3LL Electrical characteristics Table 6. Symbol Switching times Parameter Test conditions Turn-on delay time Rise time VDD=15 V, ID=4 A, RG=4.7 Ω, VGS= 4.5 V (see Figure 27) Q1 Q2 Q1 Q2 12 8.2 14.5 6 ns ns ns ns Turn-off delay time Fall time VDD=15 V, ID=4 A, RG=4.7 Ω, VGS= 4.5V (see Figure 27) Q1 Q2 Q1 Q2 23 27.8 8 3.6 ns ns ns ns td(on) tr td(off) tf Table 7. Symbol Type Min. Typ. Max. Unit Source drain diode Parameter Test conditions Type Min Typ. Max Unit ISD Source-drain current VDD=15 V, ID=4 A RG=4.7 Ω, VGS=4.5 V ISDM (1) Source-drain current (pulsed) VDD=15 V, ID= 4A RG=4.7 Ω, VGS=4.5 V Q1 Q2 32 36 A A VSD (2) Forward on voltage ISD = 8 A, VGS = 0 Q1 Q2 1.5 1.5 V V trr Qrr IRRM Reverse recovery time ISD = 8 A, VDD = 15 V Reverse recovery charge di/dt = 100 A/µs, T = 150°C Reverse recovery current j (see Figure 26) Q1 Q2 8 9 A A Q1 Q2 Q1 Q2 Q1 Q2 15 22.8 5.7 14.9 0.76 1.3 ns ns nC nC A A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 5/14 Electrical characteristics STS9D8NH3LL 2.1 Electrical characteristics (curves) Figure 2. Safe operating area for Q1 Figure 3. Safe operating area for Q2 Figure 4. Thermal impedance for Q1 Figure 5. Thermal impedance for Q2 Figure 6. Output characteristics for Q1 Figure 7. Output characteristics for Q2 6/14 STS9D8NH3LL Figure 8. Transfer characteristics for Q1 Electrical characteristics Figure 9. Transfer characteristics for Q2 Figure 10. Static drain-source on resistance for Q1 Figure 11. Static drain-source on resistance for Q2 Figure 12. Normalized BVDSS vs temperature for Q1 Figure 13. Normalized BVDSS vs temperature for Q2 7/14 Electrical characteristics STS9D8NH3LL Figure 14. Gate charge vs gate-source voltage Figure 15. Gate charge vs gate-source voltage for Q1 for Q2 Figure 16. Capacitance variations for Q1 Figure 17. Capacitance variations for Q2 Figure 18. Normalized gate threshold voltage vs temperature for Q1 Figure 19. Normalized gate threshold voltage vs temperature for Q2 8/14 STS9D8NH3LL Electrical characteristics Figure 20. Normalized on resistance vs temperature for Q1 Figure 21. Normalized on resistance vs temperature for Q2 Figure 22. Source-drain diode forward characteristics for Q1 Figure 23. Source-drain diode forward characteristics for Q2 9/14 Test circuit 3 STS9D8NH3LL Test circuit Figure 24. Switching times test circuit for resistive load Figure 25. Gate charge test circuit Figure 26. Test circuit for inductive load Figure 27. Unclamped Inductive load test switching and diode recovery times circuit Figure 28. Unclamped inductive waveform 10/14 Figure 29. Switching time waveform STS9D8NH3LL 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/14 Package mechanical data STS9D8NH3LL SO-8 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. TYP. 1.75 0.1 MAX. 0.068 0.25 a2 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 c1 45 (typ.) 1.27 e e3 3.81 0.150 3.8 4.0 0.14 L 0.4 1.27 0.015 S 0.244 0.050 F M 12/14 MIN. 0.6 0.157 0.050 0.023 8 (max.) STS9D8NH3LL 5 Revision history Revision history Table 8. Document revision history Date Revision Changes 05-Jan-2007 1 First release 06-Mar-2007 2 Some value changed on Table 4 (RDS(on) for Q2) 10-Dec-2007 3 Added EAS value on Table 2: Absolute maximum ratings 13/14 STS9D8NH3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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