STW45NM50 N-CHANNEL 550V @ Tjmax - 0.08Ω - 45A TO-247 MDmesh™ MOSFET Table 1: General Features TYPE VDSS (@Tjmax) RDS(on) ID 550V < 0.1Ω 45 A STW45NM50 ■ ■ ■ ■ ■ ■ Figure 1: Package TYPICAL RDS(on) = 0.08Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. 3 2 1 TO-247 Figure 2: Internal Schematic Diagram APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STW45NM50 W45NM50 TO-247 TUBE Rev. 2 March 2005 1/9 STW45NM50 Table 3: Absolute Maximum ratings Symbol VGS Parameter Gate- source Voltage Value Unit ±30 V ID Drain Current (continuous) at TC = 25°C 45 A ID Drain Current (continuous) at TC = 100°C 28.4 A IDM (*) Drain Current (pulsed) 180 A PTOT Total Dissipation at TC = 25°C 417 W Derating Factor 2.08 W/°C 15 V/ns –65 to 150 °C 150 °C 0.3 °C/W dv/dt (1) Tstg Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (*)Pulse width limited by safe operating area (1)ISD ≤45A, di/dt ≤400A/µs, VDD ≤ V(BR)DSS, T j ≤ T JMAX. Table 4: Thermal Data Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 30 °C/W 300 °C Max Value Unit Table 5: Avalanche Characteristics Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 20 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 810 mJ ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off Symbol Test Conditions Min. Typ. Max. Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 10 µA VDS = Max Rating, TC = 125 °C 100 µA Gate-body Leakage Current (VDS = 0) VGS = ±30 V ±100 nA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 22.5 A 0.08 0.1 Ω IGSS 500 Unit ID = 250 µA, VGS = 0 IDSS 2/9 Parameter Drain-source Breakdown Voltage V(BR)DSS 3 V STW45NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (2) Parameter Test Conditions Unit VDS = 25V, f = 1 MHz, VGS = 0 3700 610 80 pF pF pF Equivalent Output Capacitance VGS = 0V, VDS = 0V to 400V 325 pF Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 1.7 Ω td(on) tr Turn-on Delay Time Rise Time VDD = 250V, ID = 24 A RG = 4.7Ω VGS = 10 V (see Figure 14) 40 35 ns ns td(off) tf tc Turn-off Delay Time Fall Time Cross-over Time VDD = 400 V, ID = 45 A, RG = 4.7Ω, VGS = 10 V (see Figure 14) 18 23 44 ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 400V, ID = 45 A, VGS = 10V (see Figure 18) 87 23 42 117 nC nC nC Typ. Max. Unit RG Input Capacitance Output Capacitance Reverse Transfer Capacitance Max. S Coss eq. (3) VDS > ID(on) x RDS(on)max,ID = 22.5A Typ. 20 Ciss Coss Crss Forward Transconductance Min. Table 8: Source Drain Diode Symbol ISD Parameter Test Conditions Min. Source-drain Current 45 A ISDM (3) Source-drain Current (pulsed) 180 A VSD (2) Forward On Voltage ISD = 45 A, VGS = 0 1.5 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100A/µs, VDD = 100 V, Tj = 25°C (see Figure 16) 520 7.8 30 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100A/µs, VDD = 100 V, Tj = 150°C (see Figure 16) 680 11.2 33 ns µC A trr Qrr IRRM trr Qrr IRRM (2)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (3)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/9 STW45NM50 Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/9 STW45NM50 Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics 5/9 STW45NM50 Figure 14: Unclamped Inductive Load Test Circuit Figure 17: Unclamped Inductive Wafeform Figure 15: Switching Times Test Circuit For Resistive Load Figure 18: Gate Charge Test Circuit Figure 16: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/9 STW45NM50 TO-247 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 0.134 b2 3.0 3.40 0.118 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 e 5.45 L 14.20 14.80 0.560 L1 3.70 4.30 0.14 L2 0.620 0.214 18.50 0.582 0.17 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S 5.50 0.216 7/9 STW45NM50 Table 9: Revision History 8/9 Date Revision 30/Mar/2005 2 Description of Changes Modified value in table 7 STW45NM50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 9/9