STMICROELECTRONICS STW26NM50

STW26NM50
N-CHANNEL 500V - 0.10Ω - 30A TO-247
MDmesh™ MOSFET
Table 1: General Features
TYPE
STW26NM50
■
■
■
■
Figure 1: Package
VDSS
RDS(on)
ID
500 V
< 0.120 Ω
30 A
TYPICAL RDS(on) = 0.10 Ω
HIGH dv/dt AND AVALANCHE CAPABILITIES
IMPROVED ESD CAPABILITY
LOW INPUT CAPACITANCE AND GATE
CHARGE
DESCRIPTION
The MDmesh™ is a new revolutionary MOSFET
technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an
outstanding low on-resistance, impressively high
dv/dt and excellent avalanche characteristics. The
adoption of the Company’s proprietary strip technique yields overall dynamic performance that is
significantly better than that of similar competition’s products.
TO-247
Figure 2: Internal Schematic Diagram
APPLICATIONS
The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies.
Table 2: Order Codes
SALES TYPE
MARKING
PACKAGE
PACKAGING
STW26NM50
W26NM50
TO-247
TUBE
Rev. 9
February 2005
1/9
STW26NM50
Table 3: Absolute Maximum ratings
Symbol
VDS
VDGR
VGS
Parameter
Value
Unit
Drain-source Voltage (VGS = 0)
500
V
Drain-gate Voltage (RGS = 20 kΩ)
500
V
Gate- source Voltage
± 30
V
ID
Drain Current (continuous) at TC = 25°C
30
A
ID
Drain Current (continuous) at TC = 100°C
18.9
A
IDM ()
PTOT
VESD(G-S)
dv/dt (1)
Tj
Tstg
Drain Current (pulsed)
120
A
Total Dissipation at TC = 25°C
313
W
Derating Factor
2.5
W/°C
Gate source ESD(HBM-C=100pF, R=1.5KΩ)
6000
V
15
V/ns
-55 to 150
°C
Peak Diode Recovery voltage slope
Operating Junction Temperature
Storage Temperature
( ) Pulse width limited by safe operating area
(1) ISD ≤26A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ T JMAX.
Table 4: Thermal Data
Rthj-case
Thermal Resistance Junction-case Max
0.4
°C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
°C/W
Maximum Lead Temperature For Soldering Purpose
300
°C
Tl
Table 5: Avalanche Characteristics
Symbol
Parameter
Max Value
Unit
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
13
A
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
740
mJ
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 6: Gate-Source Zener Diode
Symbol
BVGSO
Parameter
Gate-Source Breakdown
Voltage
Test Conditions
Igss=± 1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/9
STW26NM50
Table 7: On /Off
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
500
Unit
V(BR)DSS
Drain-source Breakdown
Voltage
ID = 250 mA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating, TC = 125°C
10
100
µA
µA
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20 V
± 10
µA
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on
Static Drain-source On
Resistance
VGS = 10 V, ID = 13 A
3
V
4
5
V
0.10
0.12
Ω
Typ.
Max.
Unit
Table 8: Dynamic
Symbol
gfs (1)
Parameter
Test Conditions
Min.
Forward Transconductance
VDS = 15 V , ID = 13 A
20
S
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25 V, f = 1 MHz,
VGS = 0
3000
700
50
pF
pF
pF
Equivalent Output
Capacitance
VGS = 0 V, VDS = 0 to 400 V
300
pF
td(on)
tr
td(off)
tf
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
VDD = 250 V, ID = 13 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 15)
28
15
13
19
ns
ns
ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 400 V, ID = 26 A,
VGS = 10 V
(see Figure 18)
76
20
36
106
nC
nC
nC
Typ.
Max.
Unit
26
104
A
A
1.5
V
Ciss
Coss
Crss
COSS eq (3).
Table 9: Source Drain Diode
Symbol
Parameter
ISD
ISDM (2)
Source-drain Current
Source-drain Current (pulsed)
VSD (1)
Forward On Voltage
ISD = 26 A, VGS = 0
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 26 A, di/dt = 100 A/µs
VDD = 100V
(see Figure 16)
400
5.5
27.8
ns
µC
A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 26 A, di/dt = 100 A/µs
VDD = 100V, Tj = 150°C
(see Figure 16)
492
7
28.8
ns
µC
A
trr
Qrr
IRRM
trr
Qrr
IRRM
Test Conditions
Min.
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
(3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
3/9
STW26NM50
Figure 3: Safe Operating Area
Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
4/9
STW26NM50
Figure 9: Gate Charge vs Gate-source Voltage
Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temperature
Figure 11: Dource-Drain Diode Forward Characteristics
5/9
STW26NM50
Figure 14: Unclamped Inductive Load Test Circuit
Figure 17: Unclamped Inductive Wafeform
Figure 15: Switching Times Test Circuit For
Resistive Load
Figure 18: Gate Charge Test Circuit
Figure 16: Test Circuit For Inductive Load
Switching and Diode Recovery Times
6/9
STW26NM50
TO-247 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
inch
MAX.
MIN.
TYP.
MAX.
A
4.85
5.15
0.19
0.20
A1
2.20
2.60
0.086
0.102
b
1.0
1.40
0.039
0.055
b1
2.0
2.40
0.079
0.094
0.134
b2
3.0
3.40
0.118
c
0.40
0.80
0.015
0.03
D
19.85
20.15
0.781
0.793
E
15.45
15.75
0.608
e
5.45
L
14.20
14.80
0.560
L1
3.70
4.30
0.14
L2
0.620
0.214
18.50
0.582
0.17
0.728
øP
3.55
3.65
0.140
0.143
øR
4.50
5.50
0.177
0.216
S
5.50
0.216
7/9
STW26NM50
Table 10: Revision History
8/9
Date
Revision
24-June-2004
9
Description of Changes
New Stylesheet.
STW26NM50
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2005 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
9/9