TSM103/A DUAL OPERATIONAL AMPLIFIER AND VOLTAGE REFERENCE NOT FOR NEW DESIGN - REPLACED BY TSM103W OPERATIONAL AMPLIFIER ■ LOW INPUT OFFSET VOLTAGE : 0.5mV typ.for TSM103A ■ LOW SUPPLY CURRENT : 350µA/op. (@ V CC = 5V) ■ MEDIUM BANDWIDTH (unity gain) : 0.9MHz ■ LARGE OUTPUT VOLTAGE SWING : 0V to (VCC - 1.5V) ■ INPUT COMMON MODE VOLTAGE RANGE D SO8 (Plastic Micropackage) INCLUDES GROUND ■ WIDE POWER SUPPLY RANGE : 3 to 32V ±1.5 TO ±16V VOLTAGE REFERENCE ■ FIXED OUTPUT VOLTAGE REFERENCE 2.5V ■ 0.4% AND 1% VOLTAGE PRECISION ■ SINK CURRENT CAPABILITY : 1 to 100mA ■ TYPICAL OUTPUT IMPEDANCE : 0.2Ω PIN CONNECTIONS (top view) DESCRIPTION The TSM103 is a monolithic IC that includes one independent op-amp and another op-amp for which the non inverting input is wired to a 2.5V fixed Voltage Reference. This device is offering space and cost saving in many applications like power supply management or data acquisition systems. Output 1 1 OP2 Inverting Input 1 2 Non-inverting Input 1 3 V - 4 CC ORDER CODE OP1 - + VRef 8 VCC+ 7 Output 2 6 Inverting Input 2 + - 5 Non-inverting Input 2 Package Part Number Temperature Range D TSM103I/AI -40°C, +105°C • D = Small Outline Package (SO) - also available in Tape & Reel (DT) January 2003 1/9 TSM103/A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage 36 V Vid Differential Input Voltage 36 V Vi Input Voltage -03. to +36 V Operating Free-air Temperature Range Toper Tj Rthja -55 to +125 °C Maximum Junction Temperature 150 °C Thermal Resistance Junction to Ambient (SO package) 175 °C/W ELECTRICAL CHARACTERISTICS Symbol ICC 2/9 Parameter Total Supply Current, excluding Current in the Voltage Reference VCC+ = 5V, no load Tmin. < Tamb < Tmax. VCC+ = 30V, no load Tmin. < Tamb < Tmax Min. Typ. Max. Unit 1.2 mA 0.7 2 TSM103/A OPERATOR 2 (independent op-amp) VCC+ = +5V, VCC = Ground, V o = 1.4V,T amb = 25°C (unless otherwise specified) Symbol Vio Parameter Min. Input Offset Voltage TSM103, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. TSM103A, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. Typ. Max. 1 4 5 2 3 Unit mV 0.5 µV/°C Input Offset Voltage Drift 7 Iio Input Offset Current Tmin. ≤ Tamb ≤ Tmax. 2 30 50 nA Iib Input Bias Current Tmin. ≤ Tamb ≤ Tmax 20 150 200 nA DVio Avd SVR Vicm V/mV Large Signal Voltage Gain VCC = 15V, RL = 2k, Vo = 1.4V to 11.4V Tmin. ≤ Tamb ≤ Tmax. 50 25 100 Supply Voltage Rejection Ratio VCC = 5V to 30V 65 100 dB Input Common Mode Voltage Range VCC = +30V - see note 1) Tmin. ≤ Tamb ≤ Tmax. 0 0 CMR Common Mode Rejection Ratio Tmin. ≤ Tamb ≤ Tmax. 70 60 85 Isource Output Current Source VCC = +15V, Vo = 2V, Vid = +1V 20 40 Io Isink VOH VOL High Level Output Voltage VCC+ = 30V Tamb = 25°C, RL = 10k Tmin. ≤ Tamb ≤ Tmax. GBP THD (VCC+) -2 dB mA 40 60 mA 10 20 V 27 27 28 Low Level Output Voltage mV 5 RL = 10k Tmin. ≤ Tamb ≤ Tmax. SR Slew Rate at Unity Gain Vi = 0.5 to 3V, VCC = 15V RL = 2k, CL = 100pF, unity gain 0.2 0.4 Gain Bandwidth Product VCC = 30V,RL = 2k, CL = 100pF f = 100kHz, Vin = 10mV 0.5 0.9 Total Harmonic Distortion f = 1kHz AV = 20dB,RL = 2k, VCC = 30V CL = 100pF, Vo = 2Vpp V mA Short Circuit to Ground VCC = +15V Output Current Sink Vid = -1V, VCC = +15V, Vo = 2V (VCC+) -1.5 20 20 V/µs MHz % 0.02 1. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode voltage range is VCC+ - 1.5V. But either of both inputs can go to +36V without damage. 3/9 TSM103/A OPERATOR 1 (op-amp with non-inverting input connected to the internal Vref) VCC+ = +5V, VCC- = Ground, Tamb = 25°C (unless otherwise specified) Symbol Vio DVio Iib Avd SVR Isource Io Parameter Input Offset Voltage Vicm = 0V TSM103, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. TSM103A, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. 1 0.5 Output Current Source Vo = 2V VCC = +15V, Vid = +1V VOH High Level Output Voltage VCC+ = 30V Tamb = 25°C, RL = 10k Tmin. ≤ Tamb ≤ Tmax. GBP THD 4/9 4 5 2 3 µV/°C nA V/mV 100 dB 65 100 mA 20 40 mA 40 60 mA 10 20 V 27 27 28 mV Low Level Output Voltage 5 RL = 10k Tmin. ≤ Tamb ≤ Tmax. SR Slew Rate at Unity Gain Vi = 0.5 to 2V, VCC = 15V RL = 2k, CL = 100pF, unity gain 0.2 0.4 Gain Bandwidth Product VCC = 30V,RL = 2k, CL = 100pF f = 100kHz, Vin = 10mV 0.5 0.9 Total Harmonic Distortion f = 1kHz AV = 20dB,RL = 2k, VCC = 30V CL = 100pF, Vo = 2Vpp Unit 20 Short Circuit to Ground VCC = +15V Output Current Sink Vid = -1V, VCC = +15V, Vo = 2V Max. 7 Input Bias Current negative input Large Signal Voltage Gain Vicm = 0V VCC = 15V, RL = 2k Supply Voltage Rejection Ratio Vicm = 0V VCC+ = 5V to 30V Typ. mV Input Offset Voltage Drift Isink VOL Min. 20 20 V/µs MHz % 0.02 TSM103/A VOLTAGE REFERENCE Symbol Ik Symbol Vref ∆Vref Imin |ZKA| Parameter Cathode Current Parameter Reference Input Voltage TSM103, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. TSM103A, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. Reference Input Voltage Deviation Over Temperature Range VKA = Vref; Ik = 10mA Tmin. ≤ Tamb ≤ Tmax. Minimum Cathode Current for Regulation VKA = Vref Dynamic Impedance - note 1) VKA = Vref, ∆IK = 1 to 100mA, f < 1kHz Value Unit 1 to 100 mA Min. Typ. Max. 2.475 2.45 2.49 2.48 2.5 2.525 2.55 2.51 2.52 Unit V 2.5 mV 7 30 0.5 1 0.2 0.5 mA Ω 1. The dynamic impedance is defined as [Z KA| = ∆VKA/∆IK 5/9 TSM103/A OPERATIONAL AMPLIFIERS Unit Frequency = F(I) Vcc=+/-15V, RL=2k, CL=100pF 1000 Unit Freq Thousands 800 600 400 200 0 -0.01 -0.005 0 source <= 0.005 I (A) 0.01 0.015 0.01 0.015 => sink GBP = F(I) Vcc=+/-15V, RL=2k, CL=100pF 800 Thousands GBP 700 600 500 400 300 200 100 0 -0.01 -0.005 0 source <= 0.005 I (A) => sink Phase and Gain Margin = F(I) 60 0 50 -2 -4 40 -6 30 -8 20 -10 10 -12 0 -0.01 -0.005 source <= 6/9 0 I (A) 0.005 => sink 0.01 -14 0.015 Gain Margin (dB) Phase Margin (deg) Vcc=+/-15V, RL=2k, CL=100pF TSM103/A Total Harmonic Distorsion THD = F(freq) 0.014 0.013 0.012 THD(%) 0.011 0.01 0.009 0.008 0.007 0.006 0.005 10 100 1000 10000 Frequency (Hz) Noise = F(frequency) 70 Noise(nV/SQR(Hz)) 60 50 40 30 20 10 0 0.01 0.1 1 10 100 Frequency (Hz) Vio Distribution - Operator 1 Vcc+=5V, Vcc-=0V 70 Distribution (%) 60 50 40 30 20 10 0 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Vio (mV) 7/9 TSM103/A Vio Distribution - Operator 2 Vcc+=5V, Vcc-=0V 70 Distribution (%) 60 50 40 30 20 10 0 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Vio (mV) Vref = F(Ik) 3 Vref (V) 2.5 2 1.5 1 0.5 0.0002 0.002 0.02 0.2 Cathode Current Ik (Amps) Vref Stability = f(I,C) 0.06 Current (Amps) 0.05 Stable 0.04 0.03 Unstable 0.02 0.01 0 1E-10 1E-9 1E-8 1E-7 Capacitor(F) 8/9 1E-6 1E-5 TSM103/A PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) Millimeters Inches Dim. Min. A a1 a2 a3 b b1 C c1 D E e e3 F L M S Typ. Max. 0.65 0.35 0.19 0.25 1.75 0.25 1.65 0.85 0.48 0.25 0.5 4.8 5.8 5.0 6.2 0.1 Min. Typ. Max. 0.026 0.014 0.007 0.010 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.189 0.228 0.197 0.244 0.004 45° (typ.) 1.27 3.81 3.8 0.4 0.050 0.150 4.0 1.27 0.6 0.150 0.016 0.157 0.050 0.024 8° (max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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