TLV3501 TLV3502 SBOS321D − MARCH 2005 − REVISED JULY 2005 4.5ns Rail-to-Rail, High-Speed Comparator in Microsize Packages FEATURES D D D D D D D DESCRIPTION HIGH SPEED: 4.5ns RAIL-TO-RAIL I/O SUPPLY VOLTAGE: +2.7V to +5.5V PUSH-PULL CMOS OUTPUT STAGE SHUTDOWN (TLV3501 only) MICRO PACKAGES: SOT23-6 (single) SOT23-8 (dual) LOW SUPPLY CURRENT: 3.2mA The TLV350x family of push-pull output comparators feature a fast 4.5ns propagation delay and operation from +2.7V to +5.5V. Beyond-the-rails input common-mode range makes it an ideal choice for low-voltage applications. The rail-to-rail output directly drives either CMOS or TTL logic. Microsize packages provide options for portable and space-restricted applications. The single (TLV3501) is available in SOT23-6 and SO-8 packages. The dual (TLV3502) comes in the SOT23-8 and SO-8 packages. APPLICATIONS PROPAGATION DELAY vs OVERDRIVE VOLTAGE 9 AUTOMATIC TEST EQUIPMENT WIRELESS BASE STATIONS THRESHOLD DETECTOR ZERO-CROSSING DETECTOR WINDOW COMPARATOR TLV350x RELATED PRODUCTS FEATURES VCM = 1V VS = 5V CLOAD = 17pF 8 Propagation Delay (ns) D D D D D 6 Fall 5 4 PRODUCT Precision Ultra-Fast, Low-Power Comparator Differential Output Comparator High-Speed Op Amp, 16-Bit Accurate, 150MHz High-Speed Op Amp, Rail-to-Rail, 38MHz High-Speed Op Amp with Shutdown, 250MHz Rise 7 TLC3016 TL712 OPA300 OPA350 OPA357 3 0 20 40 60 80 100 Overdrive Voltage (mV) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2005, Texas Instruments Incorporated ! ! www.ti.com "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V Signal Input Terminals, Voltage(2) . . . . . (V−) − 0.3V to (V+) + 0.3V Signal Input Terminals, Current(2) . . . . . . . . . . . . . . . . . . . . . 10mA Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74mA Operating Temperature . . . . . . . . . . . . . . . . . . . . . −40°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . 3000V Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . 500V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input terminals are diode-clamped to the power-supply rails. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Input signals that can swing more than 0.3V beyond the supply rails should be current limited to 10mA or less. (3) Short-circuit to ground, one comparator per package. ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING TLV3501 SOT23-6 DBV NXA TLV3501A TLV3501 SO-8 D TLV3502 SOT23-8 DCN NXC TLV3502 SO-8 D TLV3502A (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATIONS TLV3501 TLV3502 TLV3501 V− +IN 1 NXA −IN 2 6 5 3 4 SHDN NC(2) 1 8 SHDN +IN A −IN 2 7 V+ −IN A 2 +IN 3 6 OUT +IN B 3 V− 4 5 NC(2) −IN B 1 V+ 7 OUT A 6 OUT B 5 V− OUT V+ B 4 SOT23−6(1) SO−8 (1) Pin 1 of the SOT23-6 is determined by orienting the package marking as indicated on the diagram. (2) NC indicates no internal connection. 2 8 A SOT23−8, SO−8 "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = −40°C to +125°C. At TA = +25°C and VS = +2.7V to +5.5V, unless otherwise noted. TLV3501, TLV3502 PARAMETER OFFSET VOLTAGE Input Offset Voltage(1) vs Temperature vs Power Supply Input Hysteresis INPUT BIAS CURRENT Input Bias Current Input Offset Current(2) INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection TYP MAX UNITS VCM = 0V, IO = 0mA TA = −40°C to +125°C VS = 2.7V to 5.5V ±1 ±5 100 6 ±6.5 mV µV/°C µV/V mV VCM = VCC/2 VCM = VCC/2 ±2 ±2 ±10 ±10 pA pA (V+) + 0.2V 70 V dB dB 1013 2 1013 4 Ω pF Ω pF CONDITION VOS dVOS/dT PSRR IB IOS VCM CMRR VCM = −0.2V to (V+) + 0.2V VCM = −0.2V to (V+) + 0.2V MIN (V−) − 0.2V 57 55 INPUT IMPEDANCE Common-Mode Differential SWITCHING CHARACTERISTICS Propagation Delay Time(3) Propagation Delay Skew(4) Maximum Toggle Frequency Rise Time(5) Fall Time(5) OUTPUT Voltage Output from Rail T(pd) ∆t(SKEW) fMAX tR tF VOH,VOL ∆VIN = 100mV, Overdrive = 20mV ∆VIN = 100mV, Overdrive = 20mV ∆VIN = 100mV, Overdrive = 5mV ∆VIN = 100mV, Overdrive = 5mV ∆VIN = 100mV, Overdrive = 20mV Overdrive = 50mV, VS = 5V 4.5 IOUT = ±1mA 30 SHUTDOWN tOFF tON VL (comparator is enabled)(6) VH (comparator is disabled)(6) Input Bias Current of Shutdown Pin IQSD (quiescent current in shutdown) POWER SUPPLY Specified Voltage Operating Voltage Range Quiescent Current TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SOT23-5 SOT23-8 SO-8 7.5 400 6.4 7 10 12 ns ns ns ns ns MHz ns ns 50 mV 0.5 80 1.5 1.5 30 100 (V+) − 1.7V (V+) − 0.9V 2 2 VS IQ +2.7 +5.5 2.2 to 5.5 3.2 VS = 5V, VO = High −40 −40 −65 qJA 200 200 150 ns ns V V pA µA 5 V V mA +125 +125 +150 °C °C °C °C/W °C/W °C/W (1) VOS is defined as the average of the positive and the negative switching thresholds. (2) The difference between IB+ and IB−. (3) Propagation delay cannot be accurately measured with low overdrive on automatic test equipment. This parameter is ensured by characterization and testing at 100mV overdrive. (4) The difference between the propagation delay going high and the propagation delay going low. (5) Measured between 10% of VS and 90% of VS. (6) When the shutdown pin is within 0.9V of the most positive supply, the part is disabled. When it is more than 1.7V below the most positive supply, the part is enabled. 3 "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, and Input Overdrive = 100mV, unless otherwise noted. OUTPUT RESPONSE FOR VARIOUS OVERDRIVE VOLTAGES (falling) Input 0 VIN (V) VIN (V) OUTPUT RESPONSE FOR VARIOUS OVERDRIVE VOLTAGES (rising) Input 0 5 VOD = 100mV 3 2 VOD = 50mV 4 VOD = 20mV 3 VOUT (V) VOUT (V) VOD = 50mV 5 4 VOD = 5mV 1 0 VOD = 20mV VOD = 100mV VOD = 5mV 2 1 0 −1 −10 0 10 20 30 −1 −10 40 0 10 20 30 40 Time (ns) Time (ns) PROPAGATION DELAY vs TEMPERATURE (VOD = 20mV) PROPAGATION DELAY vs TEMPERATURE (VOD = 50mV) 5.0 5.0 Propagation Delay (ns) Propagation Delay (ns) Fall 4.5 Rise 4.0 3.5 4.5 4.0 Fall 3.5 Rise 3.0 −40 −25 0 25 50 75 100 3.0 −40 −25 125 0 25 Temperature (_ C) 75 100 125 PROPAGATION DELAY vs CAPACITIVE LOAD (VOD = 50mV) PROPAGATION DELAY vs CAPACITIVE LOAD (VOD = 20mV) 9 9 8 8 Propagation Delay (ns) Propagation Delay (ns) 50 Temperature (_ C) 7 6 Fall 5 Rise 7 6 5 Fall 4 4 3 3 Rise 0 20 40 60 Capacitive Load (pF) 4 80 100 0 20 40 60 Capacitive Load (pF) 80 100 "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = +5V, and Input Overdrive = 100mV, unless otherwise noted. PROPAGATION DELAY vs SUPPLY VOLTAGE (VCM = 1V, VOD = 20mV) WAKE−UP DELAY vs TEMPERATURE 110 9 Wake−Up Delay (ns) Propagation Delay (ns) 8 7 6 5 90 70 Fall 4 Rise 3 2 3 4 5 50 −40 −25 6 0 25 75 100 125 RESPONSE TO 100MHz SINE WAVE (±2.5V dual supply into 50Ω oscilloscope input) VIN (mV) 10 0 −10 500 0 5 −500 4 2 3 VOUT (V) VOUT (V) VIN (mV) RESPONSE TO 50MHz SINE WAVE (VDD = 5V, VIN = 20mVPP) 2 1 0 −1 1 0 −1 −2 0 20 40 60 80 100 0 2 4 6 8 Time (ns) 10 12 14 16 18 20 Time (ns) QUIESCENT CURRENT vs SUPPLY VOLTAGE QUIESCENT CURRENT vs TEMPERATURE 4.0 4.0 3.8 3.8 3.6 3.6 Quiescent Current (mA) Quiescent Current (mA) 50 Temperature (_ C) Supply Voltage (V) 3.4 3.2 3.0 2.8 2.6 3.4 3.2 3.0 2.8 2.6 2.4 2.4 2.2 2.2 2.0 2.0 2 3 4 Supply Voltage (V) 5 6 −40 −25 0 25 50 75 100 125 Temperature (_ C) 5 "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = +5V, and Input Overdrive = 100mV, unless otherwise noted. QUIESCENT CURRENT vs SHUTDOWN VOLTAGE QUIESCENT CURRENT vs FREQUENCY 3.5 25 CLOAD = 50pF Quiescent Current (mA) Quiescent Current (mA) 3.0 2.5 2.0 5V (from off to on) 2.7V (from off to on) 1.5 5V (from on to off) 1.0 2.7V (from on to off) 0.5 CLOAD = 20pF 15 10 CLOAD = 10pF 5 CLOAD = 0.5pF 0 0 0 1 2 3 Shutdown Voltage (V) 6 20 4 5 0 20 40 60 Frequency (MHz) 80 100 "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 APPLICATIONS INFORMATION The TLV3501 and TLV3502 both feature high-speed response and includes 6mV of internal hysteresis for improved noise immunity with an input common-mode range that extends 0.2V beyond the power-supply rails. SHUTDOWN A shutdown pin allows the device to go into idle when it is not in use. When the shutdown pin is high, the device draws about 2µA and the output goes to high impedance. When the shutdown pin is low, the TLV3501 is active. When the TLV3501 shutdown feature is not used, simply connect the shutdown pin to the most negative supply, as shown in Figure 1. It takes about 100ns to come out of shutdown mode. The TLV3502 does not have the shutdown feature. input. Figure 2 shows a typical topology used to introduce 25mV of additional hysteresis, for a total of 31mV hysteresis when operating from a single 5V supply. Total hysteresis is approximated by Equation 1: ( V)) R 1 ) 6mV R1 ) R 2 V HYST + (1) VHYST sets the value of the transition voltage required to switch the comparator output by enlarging the threshold region, thereby reducing sensitivity to noise. VS = 5V 0.1µF 2.2µF VIN VOUT TLV3501 VS 0.1µF R1 = 51Ω 2.2µF R 2 = 10kΩ VREF VIN TLV3501 VOUT VREF Figure 1. Basic Connections for the TLV3501 OPERATING VOLTAGE TLV3501 comparators are specified for use on a single supply from +2.7V to +5.5V (or a dual supply from ±1.35V to ±2.75V) over a temperature range of −40°C to +125°C. The device continues to function below this range, but performance is not specified. Figure 2. Adding Hysteresis to the TLV350x INPUT OVER-VOLTAGE PROTECTION Device inputs are protected by ESD diodes that will conduct if the input voltages exceed the power supplies by more than approximately 300mV. Momentary voltages greater than 300mV beyond the power supply can be tolerated if the input current is limited to 10mA. This limiting is easily accomplished with a small input resistor in series with the comparator, as shown in Figure 3. ADDING EXTERNAL HYSTERESIS The TLV350x has a robust performance when used with a good layout. However, comparator inputs have little noise immunity within the range of specified offset voltage (±5mV). For slow moving or noisy input signals, the comparator output may display multiple switching as input signals move through the switching threshold. In such applications, the 6mV of internal hysteresis of the TLV350x might not be sufficient. In cases where greater noise immunity is desired, external hysteresis may be added by connecting a small amount of feedback to the positive VS 0.1µF R 2.2µF VIN TLV3501 VOUT VREF Figure 3. Input Current Protection for Voltages Exceeding the Supply Voltage 7 "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 RELAXATION OSCILLATOR The TLV350x can easily be configured as a simple and inexpensive relaxation oscillator. In Figure 4, the R2 network sets the trip threshold at 1/3 and 2/3 of the supply. Since this is a high-speed circuit, the resistor values are rather low in order to minimize the effect of parasitic capacitance. The positive input alternates between 1/3 of V+ and 2/3 of V+ depending on whether the output is low or high. The time to charge (or discharge) is 0.69R1C. Therefore, the period is 1.38R1C. For 62pF and 1kΩ as shown in Figure 4, the output is calculated to be 10.9MHz. An implementation of this circuit oscillated at 9.6MHz. Parasitic capacitance and component tolerances explain the difference between theory and actual performance. VHI TLV3502a VIN VOUT SN74LVC1G02 TLV3502b VLO V VOUT VIN VHI VLO VC 2/3 (V+) t 1/3 (V+) Time V+ 1.38R1C VS = 5V R 1 1kΩ C 62pF Figure 5. Window Comparator—Active High VOUT VLO R2 5kΩ R2 5kΩ TLV3502a t f = 10MHz V+ VIN R2 5kΩ VOUT SN74AHC00 TLV3502b VHI V VOUT Figure 4. Relaxation Oscillator VIN HIGH-SPEED WINDOW COMPARATOR A window comparator circuit is used to determine when a signal is between two voltages. The TLV3502 can readily be used to create a high-speed window comparator. VHI is the upper voltage threshold, and VLO is the lower voltage threshold. When VIN is between these two thresholds, the output in Figure 5 is high. Figure 6 shows a simple means of obtaining an active low output. Note that the reference levels are connected differently between Figure 5 and Figure 6. The operating voltage range of either circuit is 2.7V to 5.5V. VHI VLO Time Figure 6. Window Comparator—Active Low 8 "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 PCB LAYOUT In a high-speed circuit, fast rising and falling switching transients create voltage differences across lines that would be at the same potential at DC. To reduce this effect, a ground plane is often used to reduce difference in voltage potential within the circuit board. A ground plane has the advantage of minimizing the effect of stray capacitances on the circuit board by providing a more desirable path for the current to flow. With a signal trace over a ground plane, at high-frequency the return current (in the ground plane) tends to flow right under the signal trace. Breaks in the ground plane (as simple as through-hole leads and vias) increase the inductance of the plane, making it less effective at higher frequencies. Breaks in the ground plane for necessary vias should be spaced randomly. For any high-speed comparator or amplifier, proper design and printed circuit board (PCB) layout are necessary for optimal performance. Excess stray capacitance on the active input, or improper grounding, can limit the maximum performance of high-speed circuitry. Minimizing resistance from the signal source to the comparator input is necessary in order to minimize the propagation delay of the complete circuit. The source resistance along with input and stray capacitance creates an RC filter that delays voltage transitions at the input, and reduces the amplitude of high-frequency signals. The input capacitance of the TLV350x along with stray capacitance from an input pin to ground results in several picofarads of capacitance. Figure 7 shows an evaluation layout for the TLV3501 SO-8 package; Figure 8 is for the SOT23-5 package. They are shown with SMA connectors bringing signals on and off the board. RT1 and RT2 are termination resistors for +VIN and −VIN, respectively. C1 and C2 are power-supply bypass capacitors. Place the 0.1µF capacitor closest to the comparator. The ground plane is not shown, but the pads that the resistors and capacitors connect to are shown. Figure 9 shows a schematic of this circuit. The location and type of capacitors used for power-supply bypassing are critical to high-speed comparators. The suggested 2.2µF tantalum capacitor do not need to be as close to the device as the 0.1µF capacitor, and may be shared with other devices. The 2.2µF capacitor buffers the power-supply line against ripple, and the 0.1µF capacitor provides a charge for the comparator during highfrequency switching. −VIN SD C2 C1 RT2 VOUT RT1 DUT +VIN GND +VS Figure 7. TLV3501D (SO-8) Sample Layout 9 "#$%&' "#$%&( www.ti.com SBOS321D − MARCH 2005 − REVISED JULY 2005 −VIN SD VOUT RT2 RT1 DUT C1 C2 +VS GND +VIN Figure 8. TLV3501DBV (SOT23) Sample Layout +VS −VIN C1 100nF RT2 50Ω TLV3501 C2 2.2µF VOUT +VIN RT1 50Ω Shutdown Figure 9. Schematic for Figure 7 and Figure 8 10 PACKAGE OPTION ADDENDUM www.ti.com 26-Jul-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV3501AID ACTIVE SOIC D 8 TLV3501AIDBVR ACTIVE SOT-23 DBV TLV3501AIDBVT ACTIVE SOT-23 TLV3501AIDG4 ACTIVE TLV3501AIDR 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3501AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3502AID ACTIVE SOIC D 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLV3502AIDCNR ACTIVE SOT23 DCN 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3502AIDCNT ACTIVE SOT23 DCN 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV3502AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 75 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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