SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 FEATURES • • • • • • • • • • DCT OR DCU PACKAGE (TOP VIEW) Available in the Texas Instruments NanoStar™ and NanoFree™ Packages 1.65-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 0.8 ns at 3.3 V High On-Off Output Voltage Ratio High Degree of Linearity High Speed, Typically 0.5 ns (VCC = 3 V, CL = 50 pF) Rail-to-Rail Input/Output Low On-State Resistance, Typically ≈6 Ω (VCC = 4.5 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 1A 1B 2C GND 1 8 2 7 3 6 4 5 VCC 1C 2B 2A YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW) GND 2C 1B 1A 4 5 3 6 2 7 1 8 2A 2B 1C VCC DESCRIPTION/ORDERING INFORMATION This dual bilateral analog switch is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G66 can handle both analog and digital signals. The device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION PACKAGE (1) TA ORDERABLE PART NUMBER NanoStar™ – WCSP (DSBGA) 0.17-mm Small Bump – YEA NanoFree™ – WCSP (DSBGA) 0.17-mm Small Bump – YZA (Pb-free) –40°C to 85°C NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP SN74LVC2G66YEAR SN74LVC2G66YZAR Reel of 3000 VSSOP – DCU (1) (2) _ _ _C6_ SN74LVC2G66YEPR NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) SSOP – DCT TOP-SIDE MARKING (2) SN74LVC2G66YZPR Reel of 3000 SN74LVC2G66DCTR Reel of 3000 SN74LVC2G66DCUR Reel of 250 SN74LVC2G66DCUT C66_ _ _ C66_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2005, Texas Instruments Incorporated SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 FUNCTION TABLE (EACH SECTION) CONTROL INPUT (C) SWITCH L Off H On LOGIC DIAGRAM, EACH SWITCH (POSITIVE LOGIC) 1A 1C 1 2 1B 7 One of Two Switches Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range (2) –0.5 6.5 V VI Input voltage range (2) (3) –0.5 6.5 V VO Switch I/O voltage range (2) (3) (4) –0.5 VCC + 0.5 IIK Control input clamp current VI < 0 –50 mA II/OK I/O port diode current VI/O < 0 or VI/O > VCC –50 mA IT On-state switch current VI/O = 0 to VCC ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (5) Tstg Storage temperature range DCT package 220 DCU package 227 YEA/YZA package 140 YEP/YZP package (1) (2) (3) (4) (5) 2 UNIT V °C/W 102 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 Recommended Operating Conditions (1) MIN VCC Supply voltage VI/O I/O port voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage, control input Low-level input voltage, control input VI 5.5 V 0 VCC V VCC × 0.65 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 ∆t/∆v Input transition rise/fall time TA Operating free-air temperature VCC × 0.35 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC = 4.5 V to 5.5 V VCC × 0.3 0 5.5 VCC = 1.65 V to 1.95 V 20 VCC = 2.3 V to 2.7 V 20 VCC = 3 V to 3.6 V 10 VCC = 4.5 V to 5.5 V (1) V VCC = 2.3 V to 2.7 V Control input voltage UNIT 1.65 VCC = 1.65 V to 1.95 V VIL MAX V V ns/V 10 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER ron TEST CONDITIONS On-state switch resistance ron(p) Peak on-state resistance Difference of on-state resistance between switches ∆ron VI = VCC or GND, VC = VIH (see Figure 1 and Figure 2) VI = VCC to GND, VC = VIH (see Figure 1 and Figure 2) VI = VCC to GND, VC = VIH (see Figure 1 and Figure 2) VCC MIN TYP (1) MAX IS = 4 mA 1.65 V 12.5 30 IS = 8 mA 2.3 V 9 20 IS = 24 mA 3V 7.5 15 IS = 32 mA 4.5 V 6 10 IS = 4 mA 1.65 V 85 120 (1) IS = 8 mA 2.3 V 22 30 (1) IS = 24 mA 3V 12 20 IS = 32 mA 4.5 V 7.5 15 IS = 4 mA 1.65 V 7 IS = 8 mA 2.3 V 5 IS = 24 mA 3V 3 IS = 32 mA 4.5 V 2 Ω Ω Ω IS(off) Off-state switch leakage current VI = VCC and VO = GND or VI = GND and VO = VCC, VC = VIL (see Figure 3) 5.5 V IS(on) On-state switch leakage current VI = VCC or GND, VC = VIH, VO = Open (see Figure 4) 5.5 V II Control input current VC = VCC or GND 5.5 V ICC Supply current VC = VCC or GND 5.5 V ∆ICC Supply-current change VC = VCC – 0.6 V 5.5 V Cic Control input capacitance 5V 3.5 pF Cio(off) Switch input/output capacitance 5V 6 pF Cio(on) Switch input/output capacitance 5V 14 pF (1) ±1 UNIT ±0.1 (1) ±1 ±0.1 (1) ±1 ±0.1 (1) 10 1 (1) 500 µA µA µA µA µA TA = 25°C Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5) PARAMETER tpd (1) (2) (3) 4 TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN 2 MAX VCC = 3.3 V ± 0.3 V MIN 1.2 MAX A or B B or A (2) C A or B 2.3 10 1.6 5.6 1.5 4.4 tdis (3) C A or B 2.5 10.5 1.2 6.9 2 7.2 ten (1) FROM (INPUT) VCC = 5 V ± 0.5 V MIN 0.8 UNIT MAX 0.6 ns 1.3 3.9 ns 1.1 6.3 ns tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). tPZL and tPZH are the same as ten. tPLZ and tPHZ are the same as tdis. SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 Analog Switch Characteristics TA = 25°C PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC CL = 50 pF, RL = 600 Ω, fin = sine wave (see Figure 6) Frequency response (switch on) A or B B or A CL = 5 pF, RL = 50 Ω, fin = sine wave (see Figure 6) CL = 50 pF, RL = 600 Ω, fin = 1 MHz (sine wave) (see Figure 7) Crosstalk (1) (between switches) A or B B or A CL = 5 pF, RL = 50 Ω, fin = 1 MHz (sine wave) (see Figure 7) Crosstalk (control input to signal output) C CL = 50 pF, RL = 600 Ω, fin = 1 MHz (square wave) (see Figure 8) A or B CL = 50 pF, RL = 600 Ω, fin = 1 MHz (sine wave) (see Figure 9) Feedthrough attenuation (switch off) A or B B or A CL = 5 pF, RL = 50 Ω, fin = 1 MHz (sine wave) (see Figure 9) CL = 50 pF, RL = 10 kΩ, fin = 1 kHz (sine wave) (see Figure 10) Sine-wave distortion A or B B or A CL = 50 pF, RL = 10 kΩ, fin = 10 kHz (sine wave) (see Figure 10) (1) TYP 1.65 V 35 2.3 V 120 3V 175 4.5 V 195 1.65 V >300 2.3 V >300 3V >300 4.5 V >300 1.65 V –58 2.3 V –58 3V –58 4.5 V –58 1.65 V –42 2.3 V –42 3V –42 4.5 V –42 1.65 V 35 2.3 V 50 3V 70 4.5 V 100 1.65 V –58 2.3 V –58 3V –58 4.5 V –58 1.65 V –42 2.3 V –42 3V –42 4.5 V –42 1.65 V 0.1 2.3 V 0.025 3V 0.015 4.5 V 0.01 1.65 V 0.15 2.3 V 0.025 3V 0.015 4.5 V 0.01 UNIT MHz dB mV dB % Adjust fin voltage to obtain 0 dBm at input. Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 8 9 9.5 11 UNIT pF 5 SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCC VCC B or A A or B VI = VCC or GND VO C VC VIH (On) GND IS r on V VI - VO Figure 1. On-State Resistance Test Circuit 100 VCC = 1.65 V ron - Ω VCC = 2.3 V VCC = 3.0 V 10 1 0.0 VCC = 4.5 V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN - V Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC 6 VI VO IS SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCC VCC VI B or A A or B A VO C VC VIL (Off) GND Condition 1: VI = GND, VO = VCC Condition 2: VI = VCC, VO = GND Figure 3. Off-State Switch Leakage-Current Test Circuit VCC VCC VI = VCC or GND A B or A A or B VO VO = Open VIH C VC (On) GND Figure 4. On-State Leakage-Current Test Circuit 7 SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC VCC VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 VCC/2 VCC/2 2 × VCC 2 × VCC 2 × VCC 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 5. Load Circuit and Voltage Waveforms 8 SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCC VCC 0.1 µF C VC VIH 50 Ω fin B or A A or B VO RL (On) GND CL VCC/2 RL/CL: 600 Ω/50 pF RL/CL: 50 Ω/5 pF Figure 6. Frequency Response (Switch On) VCC VCC 0.1 µF Rin 600 Ω fin 1B or 1A 1A or 1B VIH 50 Ω VO1 RL 600 Ω C VC CL 50 pF (On) VCC/2 2B or 2A 2A or 2B Rin 600 Ω VIL VO2 RL 600 Ω C VC (Off) GND CL 50 pF VCC/2 20log10(VO2/VI1) or 20log10(VO1/VI2) Figure 7. Crosstalk (Between Switches) 9 SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCC VCC B or A A or B VCC/2 VO Rin 600 Ω RL 600 Ω C VC 50 Ω GND CL 50 pF VCC/2 Figure 8. Crosstalk (Control Input, Switch Output) VCC VCC 0.1 µF fin 50 Ω B or A A or B RL VIL C VC RL (Off) VCC/2 RL/CL: 600 Ω/50 pF RL/CL: 50 Ω/5 pF Figure 9. Feedthrough (Switch Off) 10 VO GND VCC/2 CL SN74LVC2G66 DUAL BILATERAL ANALOG SWITCH www.ti.com SCES325H – JULY 2001 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCC VCC 10 µF fin 600 Ω VIH 10 µF B or A A or B VO RL 10 kΩ C VC (On) GND CL 50 pF VCC/2 VCC = 1.65 V, VI = 1.4 VP-P VCC = 2.3 V, VI = 2 VP-P VCC = 3 V, VI = 2.5 VP-P VCC = 4.5 V, VI = 4 VP-P Figure 10. Sine-Wave Distortion 11 PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC2G66DCTR ACTIVE SM8 DCT 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G66DCTRE4 ACTIVE SM8 DCT 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G66DCUR ACTIVE US8 DCU 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G66DCURE4 ACTIVE US8 DCU 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G66DCUT ACTIVE US8 DCU 8 250 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G66DCUTE4 ACTIVE US8 DCU 8 250 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G66YEAR ACTIVE WCSP YEA 8 3000 TBD SNPB Level-1-260C-UNLIM SN74LVC2G66YEPR ACTIVE WCSP YEP 8 3000 TBD SNPB Level-1-260C-UNLIM SN74LVC2G66YZAR ACTIVE WCSP YZA 8 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM SN74LVC2G66YZPR ACTIVE WCSP YZP 8 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. 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