AKM AKD4383

ASAHI KASEI
[AK4383]
AK4383
192kHz 24-Bit 2ch ∆Σ DAC with DSD input
GENERAL DESCRIPTION
The AK4383 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator the AK4383 delivers a wide dynamic range while preserving linearity for
improved THD+N performance. The AK4383 has full differential SCF outputs, removing the need for AC
coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4383
accepts 192kHz PCM data and 1-Bit DSD data, ideal for a wide range of applications including DVDAudio and SACD. The AK4383 is offered in a space saving 20pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
24-Bit 8 times FIR Digital Filter
On chip SCF
Digital de-emphasis for 32k, 44.1k and 48kHz sampling
Soft mute
Digital Attenuator (Linear 256 steps)
PCM I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
Master clock: 256fs, 384fs, 512fs or 768fs (PCM Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (PCM Double Speed Mode)
128fs or 192fs (PCM Quad Speed Mode)
512fs or 768fs (DSD Mode)
THD+N: -94dB
Dynamic Range: 110dB
DSD Data Input Mode
High Tolerance to Clock Jitter
Power supply: 4.75 to 5.25V
Very Small Package: 20pin TSSOP (0.65mm pitch)
AK4382 Pin Compatible
MCLK
VDD
CSN
CCLK
µP
Interface
De-emphasis
Control
Clock
Divider
VSS
DZFL
CDTI
DZFR
LRCK/DSDR
BICK/DCLK
SDTI/DSDL
PCM
Data
Interface
8X
Interpolator
S&H
∆Σ Modulator
SCF
8X
Interpolator
S&H
∆Σ Modulator
SCF
AOUTL+
AOUTLAOUTR+
AOUTR-
DCLK
DSDL
DSDR
DSD
Data
Interface
PDN
DSDM
MS0090-E-00
2001/4
-1-
ASAHI KASEI
[AK4383]
Ordering Guide
AK4383VT
AKD4383
-40 ∼ +85°C
20pin TSSOP (0.65mm pitch)
Evaluation Board for AK4383
Pin Layout
MCLK
1
20
DZFL
BICK/DCLK
2
19
DZFR
SDTI/DSDL
3
18
VDD
LRCK/DSDR
4
17
VSS
PDN
5
16
AOUTL+
CSN
6
15
AOUTL-
CCLK
7
14
AOUTR+
CDTI
8
13
AOUTR-
DCLK
9
12
DSDM
DSDL
10
11
DSDR
Top
View
MS0090-E-00
2001/4
-2-
ASAHI KASEI
[AK4383]
PIN/FUNCTION
No.
1
Pin Name
MCLK
I/O
I
2
3
4
5
BICK/DCLK
SDTI/DSDL
LRCK/DSDR
PDN
I
I
I
I
6
7
8
9
10
11
12
CSN
CCLK
CDTI
DCLK
DSDL
DSDR
DSDM
I
I
I
I
I
I
I
13
14
15
16
17
18
19
20
AOUTRAOUTR+
AOUTLAOUTL+
VSS
VDD
DZFR
DZFL
O
O
O
O
O
O
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
Audio Serial Data Clock Pin / DSD Clock Pin
Audio Serial Data Input Pin / DSD Lch Data Input Pin
L/R Clock Pin / DSD Rch Data Input Pin
Power-Down Mode Pin
When at “L”, the AK4383 is in the power-down mode and is held in reset.
The AK4383 should always be reset upon power-up.
Chip Select Pin
Control Data Input Pin
Control Data Input Pin in serial mode
DSD Clock Pin
(Pull-down Pin)
DSD Lch Data Input Pin
(Pull-down Pin)
DSD Rch Data Input Pin
(Pull-down Pin)
DSD Mode Enable Pin
(Pull-down Pin)
“0”: PCM data is input from Pin 2-4. And the mode can be switched between
PCM and DSD mode by register.
“1”: DSD data is input from Pin 9-11.
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Ground Pin
Power Supply Pin
Rch Data Zero Input Detect Pin
Lch Data Zero Input Detect Pin
Note: All input pins except pull-up pin should not be left floating.
MS0090-E-00
2001/4
-3-
ASAHI KASEI
[AK4383]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Symbol
VDD
IIN
VIND
Ta
Tstg
min
-0.3
-0.3
-40
-65
max
6.0
±10
VDD+0.3
85
150
Units
V
mA
V
°C
°C
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
min
4.75
typ
5.0
max
5.25
Units
V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0090-E-00
2001/4
-4-
ASAHI KASEI
[AK4383]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥2kΩ; PCM Mode; unless otherwise specified)
Parameter
min
typ
max
Resolution
24
Dynamic Characteristics
(Note 3)
THD+N
fs=44.1kHz
0dBFS
-94
-87
BW=20kHz
-60dBFS
-48
fs=96kHz
0dBFS
-92
-84
BW=40kHz
-60dBFS
-45
fs=192kHz
0dBFS
-92
BW=40kHz
-60dBFS
-45
Dynamic Range (-60dBFS with A-weighted)
(Note 4)
102
110
S/N
(A-weighted)
(Note 5)
102
110
Interchannel Isolation (1kHz)
90
110
Interchannel Gain Mismatch
0.2
0.5
DC Accuracy
Gain Drift
100
Output Voltage
(Note 6)
±2.3
±2.5
±2.7
Load Resistance
(Note 7)
2
Power Supplies
Power Supply Current (VDD)
20
34
Normal Operation (PDN = “H”, fs≤96kHz)
25
42
Normal Operation (PDN = “H”, fs=192kHz)
10
100
Power-Down Mode (PDN = “L”)
(Note 8)
Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
4. 100dB at 16bit data.
5. S/N does not depend on input bit length.
6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF,
AOUT ([email protected])=(AOUT+)-(AOUT-)=±2.5Vpp × VREF/5.
7. For AC-load. 4kΩ for DC-load.
8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.
MS0090-E-00
Units
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
kΩ
mA
mA
µA
2001/4
-5-
ASAHI KASEI
[AK4383]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW= “0”; PCM Mode)
Parameter
Symbol
min
typ
max
Units
Digital filter
PB
0
20.0
kHz
Passband
±0.05dB (Note 9)
22.05
kHz
-6.0dB
Stopband
(Note 9)
SB
24.1
kHz
Passband Ripple
PR
dB
± 0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 10)
GD
19.3
1/fs
Digital Filter + SCF
Frequency Response 20.0kHz fs=44.1kHz
FR
dB
± 0.2
40.0kHz fs=96kHz
FR
dB
± 0.3
80.0kHz fs=192kHz
FR
dB
+0/-0.6
Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”; PCM Mode)
Parameter
Symbol
min
PB
0
39.2
typ
max
Units
18.2
8.1
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 11)
(Note 11)
(Note 10)
SB
PR
SA
GD
72
-
19.3
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-5
+0/-4
+0/-5
-
dB
dB
dB
± 0.005
Digital Filter + SCF
Frequency Response
FR
20.0kHz fs=44.kHz
fs=96kHz
40.0kHz
FR
80.0kHz fs=192kHz
FR
Note: 11. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
DC CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
typ
max
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
0.8
High-Level Output Voltage (Iout=-80µA)
VOH
VDD-0.4
Low-Level Output Voltage
(Iout=80µA)
VOL
0.4
Input Leakage Current
(Note 12)
Iin
± 10
Note: 12. DSDM, DCLK, DSDL and DSDR pins have internal pull-down devices, nominally 100kΩ.
MS0090-E-00
Units
V
V
V
V
µA
2001/4
-6-
ASAHI KASEI
[AK4383]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD = 4.75 ∼ 5.25V; CL = 20pF)
Parameter
Symbol
min
fCLK
2.048
Master Clock Frequency
Duty Cycle
dCLK
40
LRCK Frequency
8
fsn
Normal Speed Mode
60
fsd
Double Speed Mode
120
fsq
Quad Speed Mode
45
Duty
Duty Cycle
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
1/128fs
tBCK
Double/Quad Speed Mode
1/64fs
tBCK
BICK Pulse Width Low
30
tBCKL
Pulse Width High
30
tBCKH
20
tBLR
BICK “↑” to LRCK Edge
(Note 13)
20
tLRB
LRCK Edge to BICK “↑”
(Note 13)
20
tSDH
SDTI Hold Time
20
tSDS
SDTI Setup Time
DSD Audio Interface Timing
DCLK Period
1/64fs
tDCK
DCLK Pulse Width Low
160
tDCKL
Pulse Width High
160
tDCKH
DCLK Edge to DSDL/R
(Note 14)
-20
tDDD
Control Interface Timing
CCLK Period
200
tCCK
CCLK Pulse Width Low
80
tCCKL
Pulse Width High
80
tCCKH
CDTI Setup Time
40
tCDS
CDTI Hold Time
40
tCDH
CSN High Time
150
tCSW
50
tCSS
CSN “↓” to CCLK “↑”
50
tCSH
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
(Note 15)
tPD
150
Notes: 13. BICK rising edge must not occur at the same time as LRCK edge.
14. DSD data transmitting device must meet this time.
15. The AK4383 can be reset by bringing PDN= “L”.
MS0090-E-00
typ
11.2896
max
36.864
60
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2001/4
-7-
ASAHI KASEI
[AK4383]
Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDTI
VIL
Audio Serial Interface Timing (PCM Mode)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB = “0”)
MS0090-E-00
2001/4
-8-
ASAHI KASEI
[AK4383]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB = “0”)
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing
MS0090-E-00
2001/4
-9-
ASAHI KASEI
[AK4383]
OPERATION OVERVIEW
D/A Converion Mode
The AK4383 can perform D/A conversion for both PCM data and DSD data. When DSDM pin is “H”, DSD data can be
input from DCLK, DSDL and DSDR pins. PCM data can be input from BICK/DCLK, SDTI/DSDL and LRCK/DSDR
pins by setting DSDM pin to “L”. In this case, BICK/DCLK, SDTI/DSDL and LRCK/DSDR pins can accept DSD data by
enabling DSD mode via the register (D/P = “1”). When PCM/DSD mode changes by DSDM pin or D/P bit, the AK4383
should be reset by PDN pin or RSTN bit. (Refer to D/A conversion mode switching timing.)
DSDM pin
L
D/P bit
0
1
0
1
H
Pin 2-4
PCM
DSD
*
*
Pin 9-11
*
*
DSD
DSD
DAC Output
PCM
DSD
DSD
DSD
Table 1. DSD/PCM Mode Control(* Don’t care.)
System Clock
1) PCM Mode
The external clocks, which are required to operate the AK4383, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 2). The frequency of MCLK at each sampling speed is set
automatically. (Table 3~5). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically
(Table 6), and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to set DFS0/1.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4383 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4383 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4383 should be reset by PDN= ”L” after threse clocks are provided. If the
external clocks are not present, the AK4383 should be in the power-down mode (PDN= ”L”). After exiting reset at
power-up etc., the AK4383 is in the power-down mode until MCLK is input.
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
8kHz~48kHz
0
1
Double Speed Mode
60kHz~96kHz
1
0
Quad Speed Mode
Default
120kHz~192kHz
Table 2. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
256fs
8.1920MHz
11.2896MHz
12.2880MHz
384fs
12.2880MHz
16.9344MHz
18.4320MHz
512fs
16.3840MHz
22.5792MHz
24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
MS0090-E-00
2001/4
- 10 -
ASAHI KASEI
[AK4383]
LRCK
fs
88.2kHz
96.0kHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
128fs
11.2896MHz
12.2880MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
176.4kHz
192.0kHz
MCLK
128fs
22.5792MHz
24.5760MHz
BICK
64fs
11.2896MHz
12.2880MHz
192fs
33.8688MHz
36.8640MHz
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
Sampling Speed
Normal
Double
Quad
Table 6. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
MCLK (MHz)
256fs
384fs
22.5792
33.8688
24.5760
36.8640
-
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
Sampling Speed
Normal
Double
Quad
Table 7. System Clock Example (Auto Setting Mode)
2) DSD Mode
The external clocks, which are required to operate the AK4383, are MCLK and DCLK. The master clock (MCLK) should
be synchronized with DSD clock (DCLK) but the phase is not critical. The frequency of MCLK is set by DCKS bit.
DCKS
MCLK
DCLK
0
512fs
64fs
1
768fs
64fs
Table 8. System Clock (fs=44.1kHz)
MS0090-E-00
2001/4
- 11 -
ASAHI KASEI
[AK4383]
Audio Serial Interface Format
1) PCM Mode
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial
data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I2S Compatible
24bit LSB Justified
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Default
Table 9. Audio Data Formats
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
1
0
5
14
4
15
3
16
2
17
1
0
31
15
0
14
6
5
14
1
4
15
3
16
2
17
1
0
31
15
14
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
MS0090-E-00
2001/4
- 12 -
ASAHI KASEI
[AK4383]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
0
1
Don’t care
23
22
0
1
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
BICK
(64fs)
SDTI
1
23 22
0
Don’t care
23
22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
2) DSD Mode
In case of DSD mode, DIF0-2 are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can invert the polarity of
DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
DSDL,DSDR
Phase Modulation
D0
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 5. DSD Mode Timing
MS0090-E-00
2001/4
- 13 -
ASAHI KASEI
[AK4383]
De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with
DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Default
Table 8. De-emphasis Filter Control (Normal Speed Mode)
Output Volume
The AK4383 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. Table 11 shows
transition times of 1 level and 256 levels. The setting value of the register is held when switching between PCM mode and
DSD mode. The transition time at DSD mode is the same as Normal Speed Mode.
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
8LRCK
2040LRCK
16LRCK
4080LRCK
Table 11. ATT Transition Time
Zero Detection
The AK4383 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for
8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data
of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pins of both
channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go to “H”
only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be
disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF pin.
MS0090-E-00
2001/4
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ASAHI KASEI
[AK4383]
Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by -∞
during ATT_DATA×ATT transition time (Table 11) from the current ATT level. When the SMUTE bit is returned to “0”,
the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition
time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the
signal transmission.
SMUTE bit
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA×ATT transition time (Table 11). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 6. Soft Mute and Zero Detection
MS0090-E-00
2001/4
- 15 -
ASAHI KASEI
[AK4383]
System Reset
The AK4383 should be reset once by bringing PDN= ”L” upon power-up. The analog section exits power-down mode by
MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs.
Power-down
The AK4383 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
7 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
DZFL/DZFR
External
MUTE
(6)
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 7. Power-down/up Sequence Example
MS0090-E-00
2001/4
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ASAHI KASEI
[AK4383]
Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM
voltage and DZFL/DZFR pins go to “H”. Figure 8 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
D/A In
(Digital)
“0” data
(1)
D/A Out
(Analog)
Normal Operation
Digital Block Power-down
GD
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK,LRCK,BICK
2/fs(5)
DZF
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Figure 8. Reset Sequence Example
MS0090-E-00
2001/4
- 17 -
ASAHI KASEI
[AK4383]
D/A conversion mode switching timing
RSTN bit
≥4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 9. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 10. D/A Mode Switching Mode Timing (DSD to PCM)
Caution: In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not
recommended by SACD format book (Scarlet Book).
MS0090-E-00
2001/4
- 18 -
ASAHI KASEI
[AK4383]
Mode Control Interface
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of
Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits)
and Control Data (MSB first, 8bits). The AK4383 latches the data on the rising edge of CCLK, so data should clocked in
on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max). The CSN
and CCLK must be fixed to “H” when the register does not be accessed.
PDN = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are
not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 11. Control I/F Timing
*The AK4383 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4383 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register
is inhibited.
Register Map
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
D6
D5
D4
D3
D2
D1
D0
ACKS
DZFE
0
ATT7
ATT7
0
DZFM
0
ATT6
ATT6
0
SLOW
DCKS
ATT5
ATT5
DIF2
DFS1
D/P
ATT4
ATT4
DIF1
DFS0
DCKB
ATT3
ATT3
DIF0
DEM1
DZFB
ATT2
ATT2
PW
DEM0
0
ATT1
ATT1
RSTN
SMUTE
0
ATT0
ATT0
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values.
All data can be written to the register even if PW or RSTN bit is “0”.
MS0090-E-00
2001/4
- 19 -
ASAHI KASEI
[AK4383]
Register Definitions
Addr
00H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
ACKS
0
0
DIF2
DIF1
DIF0
PW
RSTN
default
1
0
0
0
1
0
1
1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes, the AK4383 should be reset by PDN pin or RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 9, PCM only)
Initial: “010”, Mode 3
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr
01H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
DZFE
DZFM
SLOW
DFS1
DFS0
DEM1
DEM0
SMUTE
default
0
0
0
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 10, PCM only)
Initial: “01”, OFF
DFS1-0: Sampling speed control (PCM only)
00: Normal Speed Mode
01: Double Speed Mode
10: Quad Speed Mode
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs.
SLOW: Slow Roll-off Filter Enable (PCM only)
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
MS0090-E-00
2001/4
- 20 -
ASAHI KASEI
[AK4383]
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
Addr
02H
Register Name
Control 3
D7
0
D6
0
D5
DCKS
D4
D/P
D3
DCKB
D2
DZFB
D1
0
D0
0
default
0
0
0
0
0
0
0
0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
DCKB: Polarity of DCLK (DSD only)
0: DSD data is output from DCLK falling edge
1: DSD data is output from DCLK rising edge
D/P: DSD/PCM Mode Select
0: PCM Mode. SCLK, SDTI, LRCK input on Pin 2-4.
1: DSD Mode. DCLK, DSDL, DSDR input on Pin 2-4.
When D/P changes, the AK4383 should be reset by PDN pin or RSTN bit.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs
1: 768fs
Addr
03H
04H
Register Name
Lch ATT
Rch ATT
default
D7
ATT7
ATT7
D6
ATT6
ATT6
D5
ATT5
ATT5
D4
ATT4
ATT4
D3
ATT3
ATT3
D2
ATT2
ATT2
D1
ATT1
ATT1
D0
ATT0
ATT0
1
1
1
1
1
1
1
1
ATT = 20 log (ATT_DATA / 255) [dB]
00H: Mute
MS0090-E-00
2001/4
- 21 -
ASAHI KASEI
[AK4383]
SYSTEM DESIGN
Figure 12 shows the system connection diagram. An evaluation board (AKD4383) is available in order to allow an easy
study on the layout of a surrounding circuit.
Master Clock
PCM/DSD
Data
Controller
1
MCLK
DZFL
20
2
BICK/DCLK
DZFR
19
3
SDTI/DSDL
VDD
18
0.1u
4
LRCK/DSDR
5
PDN
6
CSN
7
VSS
17
AOUTL+
16
AOUTL-
15
CCLK
AOUTR+
14
8
CDTI
AOUTR-
13
9
DCLK
DSDM
12
DSD Data
Controller
10
DSDL
DSDR
11
Digital Ground
Analog Ground
Reset & Power down
MicroController
AK4383
+
Analog
Supply 5V
10u
Lch
LPF
Lch
MUTE
Lch Out
Rch
LPF
Rch
MUTE
Rch Out
Figure 12. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down pins should not be left floating.
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor,
especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD as possible. The differential
Voltage between VDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are full-differential outputs and 0.5 x VDD Vpp (typ) centered around the internal common voltage
(about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and
AOUT-. If the summing gain is 1, the output range is 5.0Vpp (typ @VDD=5V). The bias voltage of the external summing
circuit is supplied externally. The input data format is 2’s complement. The output voltage (VAOUT) is a positive full scale
for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H (@24bit).
The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analog outputs
are differential.
MS0090-E-00
2001/4
- 22 -
ASAHI KASEI
[AK4383]
3. External Analog Filter
It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass
filter with a cut-off frequency of maximum 50kHz and a slop of minimum 30dB/Oct. The AK4383 can achieve this filter
response by combination of the internal filter (Table 12) and an external filter (Figure 11).
Frequency
20kHz
50kHz
100kHz
Gain
-0.4dB
-2.8dB
-15.5dB
Table 12. Internal Filter Response at DSD mode
47u
2.0k
AOUT-
1.8k
4.3k
1.0k
2.5Vpp
270p
2200p
+Vop
3300p
47u
2.0k
1.8k
-
1.0k
AOUT+
Analog
Out
+
4.3k
2.5Vpp
5.65Vpp
-Vop
270p
Figure 13. External 3rd order LPF Circuit Example
Frequency
Gain
20kHz
-0.05dBr
50kHz
-0.51dBr
100kHz
-16.8dBr
DC gain = 1.07dB
Table 13. 3rd order LPF (Figure 13) Response
Application Example
1) Connection with DSD Decoder, CXD2751Q
CXD2751Q
BCKD
DCLK
DSAL
DSDL
DSAR
DSDR
AK4383
DSDM
MCLK
MCKI
22.579M
/33.868M
Phase Modulation Mode
MS0090-E-00
2001/4
- 23 -
ASAHI KASEI
[AK4383]
PACKAGE
20pin TSSOP (Unit: mm)
6.5
20
1.10max
11
4.4
6.4±0.2
A
1
0.22±0.1
10
0.17±0.05
0.65
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
0∼10°
Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate
MS0090-E-00
2001/4
- 24 -
ASAHI KASEI
[AK4383]
MARKING
AKM
4383VT
XXYYY
1)
2)
3)
4)
Asahi Kasei Logo
Marketing Code : 4383VT
Date Code : XXYYY (5 digits)
XX:
lot#
YYY: Date Code
Pin #1 indication
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS0090-E-00
2001/4
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