APLUS ASM0402C

A
PLUS MAKE YOUR PRODUCTION A-PLUS
ASM0402C
DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
Sales E-mail: Mr. Jason
sales@aplusinc.com.tw
TEL: 886-2-2782-9266
Technology E-mail: Mr. George
service@aplusinc.com.tw
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
ASM0402C
ASM0402C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
1.0 General Description
The ASM0402C is very low cost voice synthesizer with 4-bit microprocessor. It has various features
including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice
synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function
can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction
pipeline. It allows all instructions to be executed in a single cycle, except for program branches and
data table read instructions (which need two instruction cycles).
1.1 Feature
‹ Single power supply can operate from 2.4V through 5V
‹ Internal Program ROM: 2K x 10-bit
‹ 1 sets of 14-bit DPR can access up to 16K x 10 bits data memory space
‹ Data Registers:
• 48 x 4-bit data RAM (00-1Fh plus 40h-4Fh)
• Unbanked special function registers (SFR) range: 20h-3Fh
‹ I/O Ports:
• PRA: 2-bit I/O Port A (2Bh)
‹ On-chip clock generator: Resistive Clock Drive(RM)
‹ Timer: 1
‹
‹
‹
‹
‹
‹
• Timer0: a 9-bit auto-reload timer/counter
Stack: 2-level subroutine nesting
HALT and Release from HALT function to reduce power consumption
Watch Dog Timer (WDT)
Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
Number of instruction: 22
The Voice function can be implemented by microprocessor instruction
•
One 8-bit COUT output for ASMxxxxx
1
Rev 1.0
ASM0402C
FIGURE 1.1 : Block Diagram of ASM0402C
Data Bus[3:0]
ROM Latch
PCLATCH(8)
PCL(4)
Stack(12)
PC[11:0]
(ADDR[13:12])
=00b
(2-Level)
ADDR[13:0]
0 ROM_ADDR[13:0]
Instruction Bus [9:0]
1
DPR3,2,1
Instruction
Latch
Program
(Data)
ROM
DPR[13:0]
Instruction
Decoder
Control Signal
DLATCH(10)
ROM_Data[9:0]
Data Bus[3:0]
Instruction Bus [9:0]
Instruction Bus [9:0]
PCH(8)
Accumlator(4)
SRAM
ALU(4)
Immediate(4)
(48 x 4)
PRA(2)
Timer0(9)
00h-1Fh
40h-4Fh
Register(4)
weak or strong
pull-low for PRA
enter test mode
One-Channel
( Voice synthesizer )
Reset Chip
Reset Chip
Clock Generator
PRASL(2)
VDD/GND
Power on Reset
RESET pin
COUT
OSC
Test select
PRA0
P1,P2,P3,P4
COUT
2
Rev 1.0
ASM0402C
FIGURE 1.2 : External ROM Map of ASM0402C
PC[11:0]
12bit x 2 STACK
14-bit Data Pointer
Reset Vector
00000h
00080h
Reserved for Testing
00080h-003FFh
00400h
Program and data ROM
00000h-007FFh
007FFh(2K)
Data ROM
00000h-03FFFh
03FFFh(16Kx10-bits)
3
Rev 1.0
ASM0402C
1.2 Pin-Out
ASM0402C Pin-Out
VDD
PRA1
I
I/O
PRA0/RESET
I/O
OSC
COUT
GND
TEST
I
O
I
O
Power supply during operation
STI
I/O port with programmable strong pull-low or weak pull-low or fix-inputStd./O.D. floating capability
Output type with standard or Open-Drain output
STI
I/O port with programmable strong pull-low or weak pull-low or fix-inputStd./O.D. floating capability
Output type with standard or Open-Drain output
Mask option selected as an external RESET pin with weak pull-low capability
RM mode Oscillator input
Current Output of Audio
Circuit Ground Potential
Enter Test Mode. ( TEST = High )
1.3 Application circuit
ASM0402C
4
Rev 1.0
ASM0402C
1.4 Bonding Diagram
16K x 10 bit ROM
Y=1030+100 (um)
ASM0402C
CHIP SIZE: X= 1560+100(um) , Y= 1030+100(um)
1
2
3
4
5
6
7
X = 1560+100(um)
ASM0402C Pad Location
PAD # PAD Name
1
COUT
2
RA_PAD[1]
3
RA_PAD[0]/RESET
4
OSC_PAD
5
GND
Chip Size: X=1560+100 (um), Y=1030+100 (um)
Y
PAD # PAD Name
X
Y
6
TEST_PAD
-509.92 -430.32
507.6 -430.32
7
VDD
-203.2 -430.32
677.52 -430.32
X
-9.04
117.25
-347.6
-430.32
-430.32
-430.32
5
Rev 1.0
ASM0402C
1.5 DC Characteristics for ASMxxxxx
SYMBOL
PARAMETER
OPERATING
VOLTAGE
VDD
Isb
SUPPLY
CURREN
T
Iop
STANDBY
OPERATING
INPUT CURRENT
/Internal pull low
Iih
OUTPUT HIGH
CURRENT
OUTPUT LOW
CURRENT
Ioh
Iol
VDD MIN. TYP. MAX. UNIT
2.4
3
3
5
3
5
3
5
2
7
3
9
5
-5.2
3
5
3
5
-3
-8
7
20
5
V
1
1
uA
CONDITION
depending on Freq.
4MHz, RM
in HALT Mode
4MHz, RM
IO Floating
4MHz, RM
in HALT Mode
(IO Ports with
weak pull-high
pull-low)
mA
uA
4MHz, RM
(IO ports)
mA
dF/F
FREQUENCY
STABILITY
-10
10
%
dF/F
Fosc VARIATION
-20
20
%
Fosc(3v)Fosc(2.4v)
Fosc (3v)
VDD=3V,
Rosc=910k, 4MHz
FIGURE 1.3 : Frequency Range for Rosc in RM mode
Resistor(k ohm)
3v Freq.(MHz)
1200
3.125
1000
3.785
820
4.445
470
7.2
R o sc & Fre q .
Freq. MHz
8
7 .2
6
4 .4 4 5
4
3 .7 8 5
3 .1 2 5
2
0
0
200
400
600
800
1000
1200
R o sc k o h m
6
Rev 1.0
1400