CS8127 CS8127 5V Linear Controller/Driver Features Description lead allows remote sensing of the output voltage for improved regulation. The CS8127 contains all the necessary control circuitry to implement a 5V linear regulator. An external pass device is used to produce superior performance compared to conventional monolithic regulators. The CS8127 with a TIP42 PNP transistor typically provides a 100mV dropout voltage at 500mA, increasing to 350mV at 3A. Quiescent current at 500mA is only 5mA. Monolithic regulators cannot approach these figures because their power transistors do not provide the high beta and excellent saturation characteristics at high currents. The CS8127 is compatible with a wide variety of external transistors, allowing flexibility for thermal, space, and cost management. An active microprocessor RESET function is included on-chip with externally programmable delay time. During power-up, or after detection of any error in the regulated output, the RESET lead will remain in the low state for the duration of the delay. Types of errors include short circuit, low input voltage, overvoltage shutdown, thermal shutdown, or others that cause the output to become unregulated. This function is independent of the input voltage and will function correctly with an output voltage as low as 1V. Hysteresis is included in both the reset and delay comparators for noise immunity and to prevent oscillations. A latching discharge circuit is used to discharge the delay capacitor, even when triggered by a relatively short fault condition. This circuit improves upon the commonly used SCR structure by providing improved noise immunity and full capacitor discharge (0.2V typ). The CS8127 includes thermal shutdown, externally programmable current limit, and over-voltage shutdown, making it suitable for use in automotive and switching regulator post regulator applications. An optional external RC filter added to the CS8127 supply lead provides EMC hardening in addition to the on-chip EMC hardening. The SENSE ■ Externally Set Delay for Reset ■ 60V Peak Transient Capability ■ Internal Thermal Overload Protection ■ 3% Output Accuracy ■ Active RESET ■ Noise Immunity ■ On Chip EMC Hardening Protection Incorporated ■ Externally Set Current Limit Package Options Block Diagram 8L SO & 8L PDIP Pwr Gnd IC Power Gnd Ref Gnd IC Reference Gnd Sense PULLUP VIN Regulated Supply for Circuit Bias 10mA Delay Current Thermal Shutdown Error Amp + PREREGULATOR Over Voltage Shutdown 50mA VOUT VIN 1 8 Sense 2 7 Pwr Gnd Delay 3 6 Pullup RESET 4 5 Ref Gnd VOUT - Bandgap Reference 1.25V + - Delay Reset Comparator Latching Discharge + Vdis Q S R RESET + Delay Comparator Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 2/12/99 1 A ¨ Company CS8127 Absolute Maximum Ratings Power Dissipation.............................................................................................................................................Internally Limited Input Voltage ..................................................................................................................................................................Ð0.3V, 26V Transient Input Voltage ............................................................................................................................................................60V Output Current ...............................................................................................................................................Externally Limited ESD Susceptibility (Human Body Model)..............................................................................................................................2kV Junction Temperature ............................................................................................................................................Ð45¡C to 150¡C Storage Temperature..............................................................................................................................................Ð55¡C to 150¡C Lead Temperature Soldering Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak Electrical Characteristics: TA=-40ûC to +125ûC, TJ=-40ûC to +150ûC, VIN=6 to 26V, IOUT=5 to 500mA, Per Test Circuit (unless otherwise noted) PARAMETER ■ Output Stage (VOUT) Output Voltage Dropout Voltage Supply Current IQ Line Regulation Load Regulation Ripple Rejection VIN Overvoltage Shutdown Drive Current ■ RESET and Delay Functions Delay Charge Current, ICharge RESET Threshold VRTH VRTL RESET Hysteresis VRH Delay Threshold VDTC VDTD Delay Hysteresis, VDH RESET Output Voltage Low RESET Output Leakage Current Delay Capacitor (Vdis) Discharge Voltage Delay Time TEST CONDITIONS IOUT = 500mA, note 1 IOUT ² 10mA IOUT ² 500mA IOUT ² 3A, note 1 6V ² VIN ² 26V, IOUT = 5mA 5V ² IOUT ² 500mA, VIN = 14V f = 120Hz, 7V ² VIN ² 17V, IOUT = 350mA MIN TYP MAX UNIT 4.85 5.00 0.1 4 5 30 12 2 70 5.15 0.6 8 15 V V mA 50 50 mV mV dB 40 V µA mA 60 32 VSENSE = 6V VSENSE = 0V VDelay = 2V VOUT Increasing VOUT Decreasing Charge Discharge VDTC - VDTD 1V < VOUT < VRTL, 3k½ to VOUT VD > VDTC , VOUT > VRTH Discharge Latched "ON", VOUT > VRTH CDelay = 0.1µF, note 2 Note 1: Dependent on characteristics of external transistor. 25 50 250 5 4.65 4.50 150 3.25 2.80 200 10 4.90 4.70 200 3.50 3.00 400 15 VOUT-0.10 VOUT-0.15 250 3.75 3.40 800 0.4 10 µA V V mV V V mV V µA 0.2 0.5 V 32 48 ms 16 Note 2: Delay Time = 2 CDelay x VDTC ICharge = CDelay x 3.5 x 10 5 (Typical) CS8127 Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION 8L SO & PDIP 1 2 VIN Sense Unregulated supply voltage to the IC. Kelvin connection which allows remote sensing of output voltage for improved regulation. 3 Delay Timing CAP for RESET function 4 RESET CMOS/TTL compatible open collector output. RESET goes low whenever VOUT drops below 6% of it's typical value. 5 Ref Gnd Ground connection 6 Pullup Internal pullup transistor for V OUT . Also Sense pin for overvoltage shutdown. 7 Pwr Gnd Ground connection 8 VOUT Supplies base current to PNP pass transistor or threshold voltage to FET pass transistor. Typical Performance Characteristics (per Test Circuit) Temperature Performance of VOUT 2000 IOUT=500mA 5.00V @ 25°C VOUT (V) 5 4.99 4.98 4.97 1600 1400 1200 1000 800 600 400 4.96 200 90.00 4.50 4.00 80.00 2.50 2.00 5 10 15 20 40 0 1.0 0.5 1.5 2.0 IOUT (Amps) 10.00 7 8 9 0.00 10 2.5 3.0 IQ vs. IOUT 40 25°C 35 IOUT = 3A ROUT = 47W 30 VIN=14V 25 20 0 1 2 3 4 5 6 VIN (V) 7 8 15 10 IOUT = 0.5A ROUT = 330W 20.00 5 6 VIN (V) 35 40.00 0.50 4 30 50.00 30.00 3 25 60.00 1.50 1.00 2 50 IQ (mA) 3.00 1 100 70.00 IOUT= 3A IQ (mA) VOUT (V) 100.00 0 150 IQ vs. VIN 5.00 0.00 200 RESET OUTPUT CURRENT (mA) 5.50 IOUT=0.5A ROUT = 47W 250 0 0 VOUT vs. VIN 3.50 300 0 4.95 -40 -20 0 20 40 60 80 100120 140150 JUNCTION TEMPERATURE (°C) 25°C 350 DROPOUT VOLTAGE (mV) 5.01 400 Vin = 5V 1800 RESET OUTPUT VOLTAGE (mV) 5.02 Dropout Voltage vs. IOUT RESET Voltage vs. Output Current 5 9 0 10 0 0.5 1.0 1.5 2.0 2.5 3.0 IOUT (Amps) Line Regulation vs. IOUT 25°C 18 10 5 25°C 70 VIN=14V 16 VIN / VOUT(dB) 15 Ripple Rejection 80 20 25°C 6V£VIN £- 26V LOAD REGULATION (mV) LINE REGULATION (mV) 20 Load Regulation vs. IOUT 14 12 10 8 6 0 0.5 1.0 1.5 2.0 IOUT(Amps) 2.5 3.0 50 40 30 10 2 0 60 20 4 0 IOUT=250mA 0 0.5 1.0 1.5 IOUT(Amps) 3 2.0 2.5 3.0 0 10 100 1K 10K 100K 1M FREQUENCY (Hz) 10M 100M CS8127 RESET Circuit Waveform VOUT (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0V) VRH VRTH VRTL RESET (1) (2) (3) VRL TD Delay VDH VDTC VDTD VDIS (2) RESET Circuit Functional Description The CS8127 RESET function is very precise, has hysteresis on both the RESET and Delay comparators, a latching Delay capacitor discharge circuit, and operation down to 1V. RESET Delay Circuit This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the Low Voltage Inhibit circuit indicates that output voltage is above VRTH . Otherwise, the Delay lead sinks current to ground (used to discharge the Delay capacitor). The discharge current is latched ON when the output voltage falls below VRTL. The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled RESET pulse is generated following the detection of an error condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDTC . The reset circuit output is an open collector type with ON and OFF parameters as specified. The reset output NPN transistor is controlled by the Low Voltage Inhibit and Reset Delay circuits (see Block Diagram). Low Voltage Inhibit Circuit This circuit monitors output voltage, and when output voltage is below VRTL, causes the reset output transistor to be in the ON (saturation) state. When the output voltage is above VRTH, this circuit permits the reset output transistor to go into the OFF state if allowed by the reset Delay circuit. 4 CS8127 Test Circuit VIN TIP42B VOUT (5V) RIN 220W ROUT 220W CO 10mF CIN 0.022mF VOUT VIN Sense Pwr Gnd CS-8127 CDelay 0.022mF Delay PULLUP RESET Ref Gnd RRST 4.7 kW Gnd RESET Application Information may be increased or decreased for a particular application. Overvoltage Shutdown ROUT Resistor - This resistor controls the drive current available to the pass transistor. It also determines regulator start-up current and short circuit current limit. For bipolar pass transistors, it can be selected by use of the following formulae: VIN(min) Ð 1V x §Q1*** ROUT = IOUT(max) The CS8127 includes an over voltage shutdown circuit. Shutdown typically occurs at 36V. Thermal Shutdown The CS8127 includes a thermal shutdown circuit that disables the output when junction temperature exceeds approximately 180ûC. This is a self-protection feature designed to protect the CS8127. The thermal shutdown circuit does not monitor the temperature of the pass transistor, which will probably be much hotter. To optimize thermal shutdown, board design should minimize the difference in temperature of the CS8127 and the pass device. ***bQ1 = Pass transistor minimum b @ maximum output current. Typical start-up current and current limit can be calculated as follows: 4V + 5mA ISTART Å ROUT External Component Selection ILimit Å External Pass Device - Select a pass device that will deliver the desired output current, withstand the maximum expected input voltage, and dissipate the resulting power. The CS8127 is compatible with a wide variety of Bipolar and FET pass transistors. VIN Ð 1V x §Q1 @ Current Limit ROUT For example, if the minimum input voltage is 6V, maximum output current is 1Amp, and minimum transistor b @ 1Amp is 60, then ROUT can be calculated as follows: Output Capacitor - An output capacitor is required for stability in most applications. Though a 10µF capacitor should be sufficient, regulator stability is dependent on the characteristics of the pass transistor. Capacitor effective series resistance (ESR) also factors in system stability. Some bench work may be required to determine the capacitor characteristics required for use in a particular application. ROUT Å IStart Å 6V Ð 1V x 60 = 300½ 1Amp 4V 300½ + 5mA = 18.3mA With VIN = 14V, and a pass transistor b of 40 @ current limit: 14V Ð 1V x 40 = 1.7Amps ILimit Å 300½ BIAS Resistor - This resistor provides bias current for the CS8127 output stage, and prevents the pass device from ÒleakingÓ. It also speeds the turn-off of the pass device during an overvoltage transient. For proper operation over temperature, the recommended value is 560½, although it 5 CS8127 Package Specification PACKAGE THERMAL DATA PACKAGE DIMENSIONS IN mm (INCHES) Thermal Data D Lead Count Metric Max Min 10.16 9.02 5.00 4.80 8L PDIP 8L SO Narrow English Max Min .400 .355 .197 .189 RQJC RQJA 8 Lead PDIP 52 100 typ typ 8 Lead SO Narrow 45 165 ûC/W ûC/W Plastic DIP (N); 300 mil wide 7.11 (.280) 6.10 (.240) 8.26 (.325) 7.62 (.300) 1.77 (.070) 1.14 (.045) 2.54 (.100) BSC 3.68 (.145) 2.92 (.115) 0.39 (.015) MIN. .356 (.014) .203 (.008) .558 (.022) .356 (.014) REF: JEDEC MS-001 Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. D Surface Mount Narrow Body (D); 150 mil wide 4.00 (.157) 3.80 (.150) 6.20 (.244) 5.80 (.228) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 1.75 (.069) MAX 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.25 (.010) 0.19 (.008) D 0.25 (0.10) 0.10 (.004) REF: JEDEC MS-012 Ordering Information Part Number CS8127YN8 CS8127YD8 CS8127YDR8 Rev. 2/12/99 Description 8 Lead PDIP 8 Lead SO Narrow 8 Lead SO Narrow (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 6 © 1999 Cherry Semiconductor Corporation