CHERRY CS8122YTHA5

CS8122
CS8122
2% 5V, 750mA Low Dropout Linear
Regulator with Delayed RESET
Description
The CS8122 is a precision 5V linear regulator capable of sourcing in excess of
750mA. The RESET Õs delay time is
externally programmed using a discrete
RC network. During power up, or when
the output goes out of regulation, the
RESET lead remains in the low state
for the duration of the delay. This function is independent of the input voltage
and will function correctly as long as
the output voltage remains at or above
1V. Hysteresis is included in the Delay
and the RESET comparators to
improve noise immunity. A latching
discharge circuit is used to discharge
the delay capacitor when it is triggered
by a brief fault condition.
Features
The regulator is protected against a
variety of fault conditions: i.e. reverse
battery, overvoltage, short circuit and
thermal runaway conditions. The regulator is protected against voltage transients ranging from -50V to +40V. Short
circuit current is limited to 1.2A (typ).
The CS8122 is an improved replacement
for the CS8126 and features a tighter tolerance on its output voltage (2% vs 4%).
The CS8122 is packaged in a 5 lead
TOÐ220 with copper tab. The copper tab
can be connected to a heat sink if
necessary.
■ 5V +/- 2% Regulated
Output
■ Low Dropout Voltage
(0.6V @ 0.5A)
■ 750mA Output Current
Capability
■ Externally Programmed
RESET Delay
■ Fault Protection
Reverse Battery
60V Load Dump
-50V Reverse Transient
Short Circuit
Thermal Shutdown
Block Diagram
VIN
Package Options
Over Voltage
Shutdown
VOUT
5 Lead TO-220
Regulated Supply
for Circuit Bias
PreRegulator
Error Amplifier
Bandgap
Reference
Anti-Saturation
and
Current Limit
+
VOUTSENSE
Thermal
Shutdown
Charge
Current
Generator
1
2
3
4
5
Latching Discharge
Delay
Q
S
+
R
1
+
VDISC
VIN
VOUT
Gnd
Delay
RESET
Delay Comparator
+
RESET
-
Gnd
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 2/5/99
1
A
¨
Company
CS8122
Absolute Maximum Ratings
Input Operating Range..................................................................................................................................................-0.5 to 26V
Power Dissipation.............................................................................................................................................Internally Limited
Transient Input Voltage .................................................................................................................................................-50V, 60V
Output Current .................................................................................................................................................Internally Limited
ESD Susceptibility (Human Body Model)..............................................................................................................................4kV
Junction Temperature .............................................................................................................................................-55¡C to 150¡C
Storage Temperature...............................................................................................................................................-55¡C to 150¡C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Electrical Characteristics: -40ûC ² TA ² +125ûC, -40ûC ² TJ ² +150ûC, 6V ² VIN ² 26V, 5mA ² IOUT ² 500mA,
R RESET = 4.7k½ to VCC unless otherwise noted*
PARAMETER
■
TEST CONDITIONS
MIN
TYP
MAX
4.9
5.0
5.1
UNIT
Output Stage (VOUT)
Output Voltage
V
Dropout Voltage
IOUT = 500mA
0.35
0.60
V
Supply Current
IOUT ² 10mA
IOUT ² 100mA
IOUT ² 500mA
2
6
55
7
12
100
mA
Line Regulation
6V ² VIN ² 26V, IOUT = 50mA
5
50
mV
Load Regulation
50mA ² IOUT ² 500mA, VIN = 14V
10
50
mV
Ripple Rejection
f = 120Hz, VIN = 7 to 17V,
IOUT = 250mA
Current Limit
Overvoltage Shutdown
54
75
dB
0.75
1.20
A
32
40
V
Maximum Line Transient
VOUT ² 5.5V
60
95
V
Reverse Polarity Input
Voltage DC
VOUT ³ -0.6V, 10½ Load
-15
-30
V
Reverse Polarity Input
Voltage Transient
1% Duty Cycle, T < 100ms,
10½ Load
-50
-80
V
Thermal Shutdown
Guaranteed by Design
150
180
210
¡C
■ RESET and Delay Functions
Delay Charge Current
VDELAY = 2V
5
10
15
µA
RESET Threshold
VOUT Increasing, VRT(ON)
VOUT Decreasing, VRT(OFF)
4.65
4.50
4.90
4.70
VOUT-0.01
VOUT-0.16
V
V
RESET Hysteresis
VRH = VRT(ON) - VRT(OFF)
150
200
250
mV
Delay Threshold
Charge, VDC(HI)
Discharge, VDC(L)
3.25
2.85
3.50
3.10
3.75
3.35
V
V
200
400
800
mV
0.1
0.4
V
10
µA
0.2
0.5
V
32
48
ms
Delay Hysteresis
RESET Output Voltage Low
1V < VOUT < VRT(L), 3k½ to VOUT
RESET Output Leakage
VOUT > VRT(H)
Current
Delay Capacitor
Discharge Voltage
Discharge Latched ÒONÓ,
VOUT > VRT
Delay Time
CDELAY = 0.1µF
0
16
* To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
CDelay x VDelay Threshold Charge
= CDelay x 3.5 x 105 (typ)
Delay Time =
ICharge
2
CS8122
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
5Lead TO-220
1
VIN
Unregulated supply voltage to IC.
2
VOUT
Regulated 5V output.
3
Gnd
Ground connection.
4
Delay
Timing capacitor for RESET function.
5
RESET
CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6% of it's regulated value.
Typical Performance Characteristics
Quiescent Current vs Input Voltage over Temperature
55.0
50.0
Quiescent Current vs Input Voltage over Load Resistance
120.0
Rload = 25W
Rload = 6.67W
100.0
40.0
Quiescent Current (mA)
Quiescent Current (mA)
45.0
Room Temp.
35.0
30.0
125ûC
25.0
20.0
15.0
25ûC
10.0
60.0
Rload = 10W
40.0
20.0
-40ûC
5.0
80.0
Rload = 25W
Rload = NO LOAD
0.0
0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V)
VIN (V)
VOUT vs. VIN over RLOAD
Output Voltage vs Input Voltage over Temperature
Rload = 25W
5.5
5.5
5.0
5.0
Rload=25½
4.5
4.5
4.0
4.0
VOUT (V)
VOUT (V)
2.5
125ûC
1.0
3.0
2.5
2.0
2.0
1.5
Rload = 6.67W
3.5
3.5
3.0
Room Temp.
1.5
25ûC
Rload =
NO LOAD
1.0
-40ûC
0.5
0.5
Rload = 10W
0.0
0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V)
VIN (V)
3
CS8122
Typical Performance Characteristics: continued
Load Regulation vs. Output Current
100
6
80
4
60
VIN 6-26V
40
TEMP = 25ûC
20
TEMP = - 40ûC
0
-20
-40
TEMP = 125ûC
-60
TEMP = -40ûC
2
LOAD REGULATION (mV)
LINE REGULATION (mV)
Line Regulation vs. Output Current
0
-2
TEMP = 25ûC
-4
VIN = 14V
-6
TEMP = 125ûC
-8
-10
-80
-12
-100
-14
0
100
200
300
400
500
600
700
800
0
100
200
OUTPUT CURRENT (mA)
900
100
800
90
700
25ûC
500
125ûC
400
300
-40ûC
200
100
500
VIN = 14V
80
600
700
800
125ûC
70
25ûC
60
50
-40ûC
40
30
20
10
0
0
0
100
200
300
400
500
600
700
0
800
100
200
300
400
500
600
700
800
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Output Capacitor ESR
Ripple Rejection
103
IOUT= 250mA
90
102
80
COUT= 10mF, ESR = 1 & 0.1mF,
ESR = 0
60
50
40
COUT= 10mF, ESR = 1W
30
CO= 47/68mF
101
ESR (ohms)
70
REJECTION (dB)
400
Quiescent Current vs. Output Current
QUIESCENT CURRENT (mA)
DROPOUT VOLTAGE (mV)
Dropout Voltage vs. Output Current
600
300
OUTPUT CURRENT (mA)
Stable Region
100
10-1
CO= 47mF
-2
10
20
COUT= 10mF, ESR = 10W
10
10
0
100
101
102
103
104
105
106
CO= 68mF
-3
107
10-4
100
108
FREQUENCY (Hz)
101
102
Output Current (mA)
4
103
CS8122
RESET Circuit Waveform
VOUT
VRH
VRT(ON)
VRT(OFF)
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0V)
(1)
RESET
(2)
(3)
VRL
tDelay
Delay
VDH
VDC(HI)
VDC(LO)
VDIS
(2)
Circuit Description
The CS8122 RESET function, has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
Reset Delay Circuit
The Reset Delay Circuit provides a programmable (by
external capacitor) delay on the RESET output lead. The
Delay lead provides source current to the external delay
capacitor only when the Low Voltage Inhibit circuit indicates that output voltage is above VRT(ON). Otherwise, the
Delay lead sinks current to ground (used to discharge the
delay capacitor). The discharge current is latched ON
when the output voltage is below VRT(OFF). The Delay
capacitor is fully discharged anytime the output voltage
falls out of regulation, even for a short period of time. This
feature ensures that a controlled RESET pulse is generated
following detection of an error condition. The circuit
allows the RESET output transistor to go to the OFF (open)
state only when the voltage on the Delay lead is higher
than VDC(HI).
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
Low Voltage Inhibit Circuit
The Low Voltage Inhibit Circuit monitors output voltage,
and when output voltage is below the specified minimum,
causes the RESET output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the RESET output transistor
to go into the OFF state if allowed by the RESET Delay circuit.
Test Circuit
VOUT
VIN
CIN*
100nF
CS8122
Delay
Gnd
CDelay
0.1mF
*CIN required if regulator is far from power source filter.
**COUT required for stability.
5
RESET
RRST
4.7kW
COUT**
10mF
CS8122
Application Notes
for this tolerance plus the variation which will occur at
low temperatures. The ESR of the capacitor should be less
than 50% of the maximum allowable ESR found in step 3
above.
Stability Considerations
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start-up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information.
The value for the output capacitor COUT shown in the test
and applications circuit should work for most applications, however it is not necessarily the optimized solution.
To determine an acceptable value for COUT for a particular
application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.
Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by
the longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If
the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger
standard capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ± 20% so the minimum
value found should be increased by at least 50% to allow
Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output regulator (Figure 1) is:
(1)
PD(max)={VIN(max)ÐVOUT(min)}IOUT(max)+VIN(max)IQ
where
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum permissible value of RQJA can be calculated:
RQJA =
150¡C - TA
PD
(2)
The value of RQJA can then be compared with those in
the package section of the data sheet. Those packages
with RQJA's less than the calculated value in equation 2
will keep the die temperature below 150¡C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
IIN
VIN
Smart
Regulator
}
IOUT
VOUT
Control
Features
IQ
Figure 1: Single output regulator with key performance parameters
labeled.
6
where:
RQJC = the junctionÐtoÐcase thermal resistance,
RQCS = the caseÐtoÐheatsink thermal resistance, and
RQSA = the heatsinkÐtoÐambient thermal resistance.
RQJC appears in the package section of the data sheet. Like
RQJA, it too is a function of package type. RQCS and RQSA
are functions of the package type, heatsink and the interface between them. These values appear in heat sink data
sheets of heat sink manufacturers.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed
to determine the value of RQJA:
RQJA = RQJC + RQCS + RQSA
(3)
7
CS8122
Application Notes: continued
CS8122
Package Specification
PACKAGE DIMENSIONS IN mm(INCHES)
PACKAGE THERMAL DATA
Thermal Data
RQJC
typ
RQJA
typ
5 Lead TO-220 (T) Straight
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
10.54 (.415)
9.78 (.385)
5 Lead TO-220
2.1
50
5 Lead TO-220 (TVA) Vertical
4.83 (.190)
4.06 (.160)
3.96 (.156)
3.71 (.146)
2.87 (.113)
6.55 (.258) 2.62 (.103)
5.94 (.234)
ûC/W
ûC/W
10.54 (.415)
9.78 (.385)
14.99 (.590)
14.22 (.560)
3.96 (.156)
3.71 (.146)
1.40 (.055)
1.14 (.045)
6.55 (.258)
5.94 (.234)
2.87 (.113)
2.62 (.103)
14.99 (.590)
14.22 (.560)
14.22 (.560)
13.72 (.540)
1.78 (.070)
2.92 (.115)
2.29 (.090)
1.02 (.040)
0.76 (.030)
8.64 (.340)
7.87 (.310)
0.56 (.022)
0.36 (.014)
1.83(.072)
1.57(.062)
1.02(.040)
0.63(.025)
6.93(.273)
6.68(.263)
4.34 (.171)
1.68
(.066) typ
1.70 (.067)
0.56 (.022)
0.36 (.014)
7.51 (.296)
6.80 (.268)
2.92 (.115)
2.29 (.090)
.94 (.037)
.69 (.027)
5 Lead TO-220 (THA) Horizontal
4.83 (.190)
10.54 (.415)
9.78 (.385)
2.87 (.113)
2.62 (.103)
1.40 (.055)
4.06 (.160)
1.14 (.045)
3.96 (.156)
3.71 (.146)
14.99 (.590)
14.22 (.560)
6.55 (.258)
5.94 (.234)
2.77 (.109)
6.83 (.269)
1.68
(.066)
TYP
1.70 (.067)
0.81(.032)
2.92 (.115)
2.29 (.090)
0.56 (.022)
0.36 (.014)
6.60 (.260)
5.84 (.230)
6.81(.268)
Ordering Information
Part Number
CS8122YT5
CS8122YTHA5
CS8122YTVA5
Rev. 2/5/99
Description
5 Lead TO-220 Straight
5 Lead TO-220 Horizontal
5 Lead TO-220 Vertical
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
8
© 1999 Cherry Semiconductor Corporation