EL2072C EL2072C 730 MHz Closed Loop Buffer Features General Description # 730 MHz b 3 dB bandwidth (0.5 VPP) # 5 ns settling to 0.2% # VS e g 5V @ 15 mA # Low distortion: HD2, HD3 of b 65 dBc at 20 MHz # Overload/short-circuit protected # Closed-loop, unity gain # Low cost # Direct replacement for CLC110 The EL2072 is a wide bandwidth, fast settling monolithic buffer built using an advanced complementary bipolar process. This buffer is closed loop to achieve lower output impedance and higher gain accuracy. Designed for closed-loop unity gain, the EL2072 has a 730 MHz b 3 dB bandwidth and 5 ns settling to 0.2% while consuming only 15 mA of supply current. Applications # # # # # # # Video buffer Video distribution HDTV buffer High-speed A/D buffer Photodiode, CCD preamps IF processors High-speed communications Ordering Information Part No. Temp. Range Package EL2072CN b 40§ C to a 85§ C 8-Pin P-DIP EL2072CS b 40§ C to a 85§ C 8-Pin SO Outline Ý The EL2072 is an obvious high-performance solution for video distribution and line-driving applications. With low 15 mA supply current and a 70 mA output drive, performance in these areas is assured. The EL2072’s settling to 0.2% in 5 ns, low distortion, and ability to drive capacitive loads make it an ideal flash A/D driver. The wide 730 MHz bandwidth and extremely linear phase allow unmatched signal fidelity. The EL2072 can be used inside an amplifier loop or PLL as its wide bandwidth and fast rise time have minimal effect on loop dynamics. Elantec products and facilities comply with MIL-I-45028A, and other applicable quality specifications. For information on Elantec’s processing, see Elantec document QRA-1: Elantec’s Processing, Monolithic Integrated Circuits. MDP0031 MDP0027 Connection Diagram DIP and SO Package 2072 – 1 Manufactured under U.S. Patent No. 4,893,091 Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. © 1991 Elantec, Inc. December 1995 Rev E Top View EL2072C 730 MHz Closed Loop Buffer Absolute Maximum Ratings (TA e 25§ C) Supply Voltage (VS) Output Current Input Voltage g 7V Output is short-circuit protected to ground, however, maximum reliability is obtained if IOUT does not exceed 70 mA. g VS b 40§ C to a 85§ C Operating Temperature Junction Temperature Storage Temperature Thermal Resistance 175§ C b 60§ C to a 150§ C iJA e 95§ C/W P-DIP iJA e 175§ C/W SO Note: See EL2071/EL2171 for Thermal Impedance curves. Important Note: All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore TJ e TC e TA. Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002. 100% production tested at TA e 25§ C and QA sample tested at TA e 25§ C , TMAX and TMIN per QA test plan QCX0002. QA sample tested per QA test plan QCX0002. Parameter is guaranteed (but not tested) by Design and Characterization Data. Parameter is typical value at TA e 25§ C for information purposes only. DC Electrical Characteristics Parameter VOS TCVOS IB Description Test Conditions Typ Max Test Level Units 2.0 8.0 I mV TMIN 16.0 V mV TMAX 13.0 V mV IV mV/§ C Temp Min 25§ C Output Offset Voltage Average Offset Voltage Drift Input Bias Current 25§ C b TMAX 20.0 50.0 25§ C b TMIN 20.0 100.0 25§ C, TMAX 10.0 TMIN TCIB AV ILIN Average Input Bias Current Drift Small Signal Gain Integral End Point linearity PSRR Power Supply Rejection Ratio IS Supply CurrentÐQuiescent RL e 100X mA IV nA/§ C I V/V 200.0 300.0 200.0 700.0 25§ C 0.96 TMIN, TMAX 0.95 0.98 V V/V 0.4 IV %F.S. TMIN 0.8 IV %F.S. TMAX 0.3 IV %F.S. II dB II mA All 2 mA V 25§ C b TMIN All No Load II 25§ C b TMAX 25§ C g 2V F.S. 50.0 100.0 0.2 45.0 65.0 15.0 20.0 TD is 3.3in VS e g 5V, RL e 100X, RS e 50X unless otherwise specified EL2072C 730 MHz Closed Loop Buffer DC Electrical Characteristics Parameter RIN CIN Description Test Conditions Input Resistance Temp Min Typ 25§ C 100.0 160.0 Output Impedance (DC) IOUT Output Current Output Voltage Swing kX 50.0 V kX V kX 1.6 2.0 TMIN, TMAX VOUT I 200.0 25§ C RL e 100X Units TMIN TMIN, TMAX ROUT Test Level TMAX 25§ C Input Capacitance Max 25§ C, TMAX 50.0 TMIN 45.0 25§ C, TMAX g 3.2 TMIN g 3.0 2.2 IV pF 2.5 IV pF 3.0 IV X 3.5 IV X II mA V mA II V V V 70.0 g 4.0 TD is 2.4in VS e g 5V, RL e 100X, RS e 50X unless otherwise specified Ð Contd. AC Electrical Characteristics VS e g 5V, RL e 100X, RS e 50X unless otherwise specified Parameter Description Test Conditions Test Level Units V MHz 400.0 IV MHz 300.0 IV MHz Temp Min Typ 25§ C 400.0 730.0 TMIN TMAX Max FREQUENCY RESPONSE SSBW LSBW b 3 dB Bandwidth (VOUT k 0.5 VPP) b 3 dB Bandwidth (VOUT e 5.0 VPP) 25§ C 55.0 TMIN, TMAX 50.0 90.0 IV MHz IV MHz GFPL GFR GDL Peaking VOUT k 0.5 VPP k 200 MHz Rolloff VOUT k 0.5 VPP k 200 MHz Group Delay k 200 MHz 25§ C 0.5 V dB TMAX 0.6 IV dB TMIN 0.8 IV dB 25§ C 0.0 0.8 V dB TMIN 1.0 IV dB TMAX 1.2 IV dB 25§ C, TMIN 0.0 0.75 TMAX LPD Linear Phase Deviation VOUT k 0.5 VPP k 200 MHz 25§ C, TMIN TMAX 3 0.7 1.0 IV ns 1.2 IV ns 1.5 IV § 2.0 IV § TD is 3.5in GAIN FLATNESS EL2072C 730 MHz Closed Loop Buffer AC Electrical Characteristics Ð Contd. VS e g 5V, RL e 100X, RS e 50X unless otherwise specified Parameter Description Test Conditions Temp Min Typ Max Test Level Units TIME-DOMAIN RESPONSE TR1, TF1 TR2, TF2 Rise Time, Fall Time Input Signal Rise/Fall e 300 ps 0.5V Step Rise Time, Fall Time 5.0V Step 0.4 TMAX Input Signal Rise/Fall s 1 ns 25§ C 4.5 TMIN, TMAX TS1 Settling Time to 0.2% Input Signal Rise/Fall s 1 ns 2.0V Step OS Overshoot Input Signal Rise/Fall e 300 ps 0.5V Step SR 25§ C, TMIN All 5.0 25§ C 0.0 TMIN, TMAX 25§ C 500.0 TMIN, TMAX 450.0 Slew Rate 1.0 IV ns 1.4 IV ns 7.5 IV ns 8.5 IV ns 10.0 IV ns 10.0 IV % 15.0 IV % IV V/ms IV V/ms 800.0 DISTORTION HD2 HD2A HD3 HD3A 2nd Harmonic Distortion at 20 MHz 2nd Harmonic Distortion at 50 MHz 25§ C 2 VPP 2 VPP b 50.0 V dBc TMIN b 48.0 IV dBc TMAX b 55.0 IV dBc b 45.0 IV dBc b 40.0 IV dBc b 55.0 V dBc b 55.0 IV dBc b 50.0 IV dBc b 45.0 IV dBc b 155.0 IV dBm (1 Hz) b 154.0 IV dBm (1 Hz) 57.0 IV mV 63.0 IV mV 25§ C , TMAX b 55.0 b 50.0 TMIN 3rd Harmonic Distortion at 20 MHz 2 VPP 3rd Harmonic Distortion at 50 MHz 2 VPP 25§ C b 65.0 TMIN, TMAX 25§ C , TMIN b 60.0 TMAX NF Noise Floor l 100 kHz 25§ C, TMIN INV Integrated Noise 100 kHz to 200 MHz 25§ C, TMIN b 158.0 TMAX TMAX 4 40.0 TD is 5.1in EQUIVALENT INPUT NOISE EL2072C 730 MHz Closed Loop Buffer Typical Performance Curves (VS e g 5V, RL e 100X, RS e 50X) Forward Gain and Phase Gain Flatness & Deviation from Linear Phase Reverse Gain and phase Input Impedance Output Impedance Recommended RS vs Load Capacitance Integral Linearity Error Frequency Response vs Rload lS21l vs Cload with Recommended Rs 2072 – 2 5 EL2072C 730 MHz Closed Loop Buffer Typical Performance Curves (VS e g 5V, RL e 100X, RS e 50X) Ð Contd. Small Signal Pulse Response Large Signal Pulse Response Long-Term Settling Time 2nd Harmonic Distortion 3rd Harmonic Distortion 2-Tone, 3rd Order Intermodulation Intercept 2072 – 3 6 EL2072C 730 MHz Closed Loop Buffer Burn-In Circuit 2072 – 4 Increasing capacitance on the output of the EL2072 will add phase shift, decreasing phase margin and increasing frequency-response peaking. A small series resistor before the capacitance decouples this effect, and should be used for large capacitance values. Please refer to the graphs for the appropriate resistor value to be used. Printed Circuit Layout As with any high-frequency device, good PCB layout is necessary for optimum performance. This is especially important for the EL2072, which has a typical bandwidth of 730 MHz. Ground plane construction is a requirement, as is good power-supply bypassing close to the package. A closely-placed 0.01 mF ceramic capacitor between each supply pin and the ground plane is usually sufficient decoupling. Pins 2, 3, 6, and 7 should be connected to the ground-plane to minimize capacitive feedthrough, and all input and output traces should be laid out as transmission lines and terminated as close to the EL2072 package as possible. 7 EL2072C EL2072C 730 MHz Closed Loop Buffer General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. December 1995 Rev E WARNING Ð Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. Elantec, Inc. 1996 Tarob Court Milpitas, CA 95035 Telephone: (408) 945-1323 (800) 333-6314 Fax: (408) 945-9305 European Office: 44-71-482-4596 8 Printed in U.S.A.