EPSON S1D13706

S1D13706 Embedded Memory LCD Controller
Hardware Functional Specification
Document Number: X31B-A-001-09
Copyright © 1999, 2004 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Features . . . . . . . . . .
2.1 Integrated Frame Buffer
2.2 CPU Interface . . . .
2.3 Display Support . . . .
2.4 Display Modes . . . .
2.5 Display Features . . .
2.6 Clock Source . . . . .
2.7 Miscellaneous . . . .
3
Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 14
4
Pins . . . . . . . . . . . . . . . . .
4.1 Pinout Diagram - TQFP15 - 100pin
4.2 Pinout Diagram - Die Form . . .
4.3 Pin Descriptions . . . . . . .
4.3.1 Host Interface . . . . . . . .
4.3.2 LCD Interface . . . . . . . .
4.3.3 Clock Input . . . . . . . . .
4.3.4 Miscellaneous . . . . . . . .
4.3.5 Power And Ground . . . . .
4.4 Summary of Configuration Options
4.5 Host Bus Interface Pin Mapping .
4.6 LCD Interface Pin Mapping . . .
5
D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 CPU Interface Timing . . . . . . . . . . . . . . . . . . . .
6.2.1 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . .
6.2.2 Generic #2 Interface Timing (e.g. ISA) . . . . . . . . . . . . . . .
6.2.3 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . .
6.2.4 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . .
6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000) . . . . . .
6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030) . . . . . .
Hardware Functional Specification
Issue Date: 2004/02/09
.
.
.
.
.
.
.
.
. .
.
.
.
.
.
.
.
. .
. .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. .
.
.
.
.
.
.
.
. . .
. .
. .
. .
. . .
. . .
. . .
. . .
. . .
. .
. .
. .
. .
. .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . .
. . . .
. . . .
. . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . .
. . . .
. . . .
. . .
. .
. .
. .
. .
. .
. .
. .
. . .
. .
. .
. .
. . .
. . .
. . .
. . .
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . .
. . . . .
. . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . .
. . . . . .
. . . . . .
. . .
. .
. . .
. . .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . . .
. . . .
. . . . .
. . . . .
. . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . .
12
12
12
12
13
13
13
13
18
18
19
21
21
25
27
27
27
28
29
30
32
32
32
34
35
35
37
39
41
43
45
S1D13706
X31B-A-001-09
Page 4
Epson Research and Development
Vancouver Design Center
6.2.7 Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328) 49
6.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328) 51
6.3 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.3.1 Passive/TFT Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.2 Passive/TFT Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.4 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6.4.1 Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.4.2 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 60
6.4.3 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 62
6.4.4 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.5 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 66
6.4.6 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 68
6.4.7 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4.8 Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.9 9/12/18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx) . . . . . . . 76
6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) . . . . . . . . 80
6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) . . . . . . . . . . . . . . . . 82
6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) . . . . . . . . . . . . . . . . 86
7
Clocks . . . . . . . . . . .
7.1 Clock Descriptions . .
7.1.1 BCLK . . . . . .
7.1.2 MCLK . . . . . .
7.1.3 PCLK . . . . . .
7.1.4 PWMCLK . . . .
7.2 Clock Selection . . .
7.3 Clocks versus Functions
. . .
. .
. . .
. . .
. . .
. . .
. .
. .
. . . .
. . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . .
. . . .
. . .
. .
. . .
. . .
. . .
. . .
. .
. .
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . .
. . . . .
.
.
.
.
.
.
.
.
. . . . . .90
. . . . .90
. . . . . . 90
. . . . . . 90
. . . . . . 91
. . . . . . 92
. . . . .93
. . . . .94
8
Registers . . . . . . . . . . . . . . . . . . . .
8.1 Register Mapping . . . . . . . . . . .
8.2 Register Set . . . . . . . . . . . . . .
8.3 Register Descriptions . . . . . . . . . .
8.3.1 Read-Only Configuration Registers . . .
8.3.2 Clock Configuration Registers . . . . .
8.3.3 Look-Up Table Registers . . . . . . . .
8.3.4 Panel Configuration Registers . . . . . .
8.3.5 Display Mode Registers . . . . . . . . .
8.3.6 Picture-in-Picture Plus (PIP+) Registers
8.3.7 Miscellaneous Registers . . . . . . . . .
. . . .
. . . .
. . . .
. . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . .
. .
. .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
S1D13706
X31B-A-001-09
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . .
. . . . .
.
.
.
.
.
.
.
.
. . .95
. . .95
. . .95
. . .96
. . . 96
. . . 97
. . . 99
. . .101
. . .109
. . .115
. . .120
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
8.3.8
8.3.9
9
Page 5
General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration
Registers 126
Frame Rate Calculation
10 Display Data Formats
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12 SwivelView™ . . . . . . . . . . . .
12.1 Concept . . . . . . . . . . .
12.2 90° SwivelView™ . . . . . .
12.2.1 Register Programming . . .
12.3 180° SwivelView™ . . . . . .
12.3.1 Register Programming . . .
12.4 270° SwivelView™ . . . . . .
12.4.1 Register Programming . . .
.
.
.
.
.
.
.
.
. . .
. .
. .
. . .
. .
. . .
. .
. . .
. . . .
. . . .
. . . .
. . . . .
. . . .
. . . . .
. . . .
. . . . .
. . .
. .
. .
. . .
. .
. . .
. .
. . .
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . . . .
. . . . .
. . . . . . .
. . . . .
. . . . . . .
.
.
.
.
.
.
.
.
. . .
. .
. .
. . .
. .
. . .
. .
. . .
. . . . 138
. . . . 138
. . . . 138
. . . . . 139
. . . . 140
. . . . . 140
. . . . 141
. . . . . 142
13 Picture-in-Picture Plus (PIP+)
13.1 Concept . . . . . . . .
13.2 With SwivelView Enabled
13.2.1 SwivelView 90° . . .
13.2.2 SwivelView 180° . .
13.2.3 SwivelView 270° . .
. . .
. . .
. . .
. . . .
. . . .
. . . .
.
.
.
.
.
.
. . .
. .
. .
. . .
. . .
. . .
. . . .
. . . .
. . . .
. . . . .
. . . . .
. . . . .
. . .
. .
. .
. . .
. . .
. . .
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
.
.
.
.
.
.
. . . . . . . 143
. . . . . . 143
. . . . . . 144
. . . . . . . . 144
. . . . . . . . 144
. . . . . . . . 145
14 Big-Endian Bus Interface . . . . .
14.1 Byte Swapping Bus Data . . . .
14.1.1 16 Bpp Color Depth . . . . .
14.1.2 1/2/4/8 Bpp Color Depth . .
.
.
.
.
. . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . .
. .
. . .
. . .
.
.
.
.
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
.
.
.
.
. . . . . . . 146
. . . . . . 146
. . . . . . . . 147
. . . . . . . . 148
15 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
16 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
18 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 7
List of Tables
Table 4-1: Pinout Assignments - Die Form (S1D13706D00A) . . . . . . . . . .
Table 4-2: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . .
Table 4-3: LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . .
Table 4-4: Clock Input Pin Descriptions. . . . . . . . . . . . . . . . . . . . . .
Table 4-5: Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . .
Table 4-6: Power And Ground Pin Descriptions . . . . . . . . . . . . . . . . .
Table 4-7: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . .
Table 4-8: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . .
Table 4-9: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . .
Table 5-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .
Table 5-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . .
Table 5-3: Electrical Characteristics for VDD = 3.3V typical . . . . . . . . . . .
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1
Table 6-3: Clock Input Requirements for CLKI2 . . . . . . . . . . . . . . . . .
Table 6-4: Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . .
Table 6-5: Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . .
Table 6-6: Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . .
Table 6-7: Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . .
Table 6-8: Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . .
Table 6-9: Motorola MC68K #1 Interface Timing . . . . . . . . . . . . . . . .
Table 6-10: Motorola MC68K #2 Interface Timing . . . . . . . . . . . . . . . .
Table 6-11: Motorola REDCAP2 Interface Timing. . . . . . . . . . . . . . . . .
Table 6-12: Motorola DragonBall Interface with DTACK Timing . . . . . . . . .
Table 6-13: Motorola DragonBall Interface without DTACK Timing . . . . . . .
Table 6-14: Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . .
Table 6-15: Passive/TFT Power-Off Sequence Timing . . . . . . . . . . . . . . .
Table 6-16: Panel Timing Parameter Definition and Register Summary . . . . . .
Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . .
Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . .
Table 6-19: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . .
Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . .
Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . .
Table 6-22: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . .
Table 6-23: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-24: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing . . . . . . . . .
Table 6-25: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing . . . . . . .
Hardware Functional Specification
Issue Date: 2004/02/09
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
20
21
25
27
27
27
28
29
30
31
31
31
32
33
33
34
36
38
40
42
44
46
48
50
52
54
55
57
61
63
65
67
69
71
75
77
79
S1D13706
X31B-A-001-09
Page 8
Table 6-26: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing
Table 6-27: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing .
Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing . . . . .
Table 6-29: 160x240 Epson D-TFD Panel GCP Horizontal Timing . .
Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing . . . . . .
Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing . . . . .
Table 6-32: 320x240 Epson D-TFD Panel GCP Horizontal Timing . .
Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing . . . . . .
Table 7-1: BCLK Clock Selection . . . . . . . . . . . . . . . . . . .
Table 7-2: MCLK Clock Selection. . . . . . . . . . . . . . . . . . .
Table 7-3: PCLK Clock Selection . . . . . . . . . . . . . . . . . . .
Table 7-4: Relationship between MCLK and PCLK. . . . . . . . . .
Table 7-5: PWMCLK Clock Selection. . . . . . . . . . . . . . . . .
Table 7-6: S1D13706 Internal Clock Requirements . . . . . . . . . .
Table 8-1: S1D13706 Register Set . . . . . . . . . . . . . . . . . . .
Table 8-2: MCLK Divide Selection . . . . . . . . . . . . . . . . . .
Table 8-3: PCLK Divide Selection. . . . . . . . . . . . . . . . . . .
Table 8-4: PCLK Source Selection. . . . . . . . . . . . . . . . . . .
Table 8-5: Panel Data Width Selection . . . . . . . . . . . . . . . .
Table 8-6: Active Panel Resolution Selection . . . . . . . . . . . . .
Table 8-7: LCD Panel Type Selection . . . . . . . . . . . . . . . . .
Table 8-8: Inverse Video Mode Select Options . . . . . . . . . . . .
Table 8-9: LCD Bit-per-pixel Selection . . . . . . . . . . . . . . . .
Table 8-10: SwivelViewTM Mode Select Options . . . . . . . . . . .
Table 8-11: 32-bit Address Increments for Color Depth . . . . . . . .
Table 8-12: 32-bit Address Increments for Color Depth . . . . . . . .
Table 8-13: 32-bit Address Increments for Color Depth . . . . . . . .
Table 8-14: 32-bit Address Increments for Color Depth . . . . . . . .
Table 8-15: PWM Clock Control . . . . . . . . . . . . . . . . . . . .
Table 8-16: CV Pulse Control . . . . . . . . . . . . . . . . . . . . . .
Table 8-17: PWM Clock Divide Select Options . . . . . . . . . . . .
Table 8-18: CV Pulse Divide Select Options . . . . . . . . . . . . . .
Table 8-19: PWMOUT Duty Cycle Select Options . . . . . . . . . . .
Table 15-1: Power Save Mode Function Summary . . . . . . . . . . .
S1D13706
X31B-A-001-09
Epson Research and Development
Vancouver Design Center
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 81
. 81
. 83
. 84
. 85
. 87
. 88
. 89
. 90
. 90
. 91
. 92
. 92
. 94
. 95
. 97
. 98
. 98
.102
.102
.102
.110
.111
.112
.116
.117
.118
.119
.126
.127
.128
.128
.129
.149
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 9
List of Figures
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 3-5:
Figure 3-6:
Figure 3-7:
Figure 3-8:
Figure 4-1:
Figure 4-2:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 6-7:
Figure 6-8:
Figure 6-9:
Figure 6-10:
Figure 6-11:
Figure 6-12:
Figure 6-13:
Figure 6-14:
Figure 6-15:
Figure 6-16:
Figure 6-17:
Figure 6-18:
Figure 6-19:
Figure 6-20:
Figure 6-21:
Figure 6-22:
Figure 6-23:
Figure 6-24:
Figure 6-25:
Figure 6-26:
Figure 6-27:
Typical System Diagram (Generic #1 Bus) . . . . . . . . . . . . . . . . . . . . . .
Typical System Diagram (Generic #2 Bus) . . . . . . . . . . . . . . . . . . . . . .
Typical System Diagram (Hitachi SH-4 Bus) . . . . . . . . . . . . . . . . . . . . .
Typical System Diagram (Hitachi SH-3 Bus) . . . . . . . . . . . . . . . . . . . . .
Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000) . . . . . . . . . . .
Typical System Diagram (MC68K #2, Motorola 32-Bit 68030) . . . . . . . . . . . .
Typical System Diagram (Motorola REDCAP2 Bus) . . . . . . . . . . . . . . . . .
Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus) .
Pinout Diagram - TQFP15 - 100pin (S1D13706F00A) . . . . . . . . . . . . . . . .
Pinout Diagram - Die Form (S1D13706D00A) . . . . . . . . . . . . . . . . . . . .
Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Motorola MC68K #1 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . .
Motorola MC68K #2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . .
Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Motorola DragonBall Interface with DTACK Timing . . . . . . . . . . . . . . . . .
Motorola DragonBall Interface without DTACK# Timing . . . . . . . . . . . . . .
Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . .
Passive/TFT Power-Off Sequence Timing . . . . . . . . . . . . . . . . . . . . . . .
Panel Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . .
Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . .
Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . .
Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . .
Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . .
Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . .
Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . .
Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . .
Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . .
Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Functional Specification
Issue Date: 2004/02/09
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 14
. 14
. 15
. 15
. 16
. 16
. 17
. 17
. 18
. 19
. 32
. 35
. 37
. 39
. 41
. 43
. 45
. 47
. 49
. 51
. 54
. 55
. 56
. 58
. 60
. 61
. 62
. 63
. 64
. 65
. 66
. 67
. 68
. 69
. 70
. 71
. 72
S1D13706
X31B-A-001-09
Page 10
Figure 6-28:
Figure 6-29:
Figure 6-30:
Figure 6-31:
Figure 6-32:
Figure 6-33:
Figure 6-34:
Figure 6-35:
Figure 6-36:
Figure 6-37:
Figure 6-38:
Figure 6-39:
Figure 7-1:
Figure 8-1:
Figure 8-2:
Figure 10-1:
Figure 11-1:
Figure 11-2:
Figure 11-3:
Figure 11-4:
Figure 11-5:
Figure 11-6:
Figure 11-7:
Figure 11-8:
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 13-1:
Figure 13-2:
Figure 13-3:
Figure 13-4:
Figure 14-1:
Figure 14-2:
Figure 16-1:
S1D13706
X31B-A-001-09
Epson Research and Development
Vancouver Design Center
18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .76
160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .78
320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .80
320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .81
160x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .82
160x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .84
160x240 Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . .85
320x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .86
320x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .88
320x240 Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . .89
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Display Data Byte/Word Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
PWM Clock/CV Pulse Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4/8/16 Bit-Per-Pixel Display Data Memory Organization . . . . . . . . . . . . . . . . 131
1 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 132
2 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 132
4 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 133
8 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 133
1 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 134
2 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 135
4 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 136
8 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 137
Relationship Between The Screen Image and the Image Refreshed in 90× SwivelView. 138
Relationship Between The Screen Image and the Image Refreshed in 180× SwivelView.140
Relationship Between The Screen Image and the Image Refreshed in 270× SwivelView.141
Picture-in-Picture Plus with SwivelView disabled . . . . . . . . . . . . . . . . . . . . 143
Picture-in-Picture Plus with SwivelView 90° enabled . . . . . . . . . . . . . . . . . . 144
Picture-in-Picture Plus with SwivelView 180° enabled . . . . . . . . . . . . . . . . . 144
Picture-in-Picture Plus with SwivelView 270° enabled . . . . . . . . . . . . . . . . . 145
Byte-swapping for 16 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Byte-swapping for 1/2/4/8 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Mechanical Data 100pin TQFP15 (S1D13706F00A) . . . . . . . . . . . . . . . . . . 150
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 11
1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13706 Embedded Memory LCD
Controller. Included in this document are timing diagrams, AC and DC characteristics,
register descriptions, and power management descriptions. This document is intended for
two audiences: Video Subsystem Designers and Software Developers.
For additional documentation related to the S1D13706 see Section 17, “References” on
page 151.
This document is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before
beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
1.2 Overview Description
The S1D13706 is a color/monochrome LCD graphics controller with an embedded 80K
byte SRAM display buffer. While supporting all other panel types, the S1D13706 is the
only LCD controller to directly interface to both the Epson D-TFD and the Sharp HR-TFT
family of products thus removing the requirement of an external Timing Control IC. This
high level of integration provides a low cost, low power, single chip solution to meet the
demands of embedded markets such as Mobile Communications devices and Palm-size
PCs, where board size and battery life are major concerns.
The S1D13706 utilizes a guaranteed low-latency CPU architecture providing support for
microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data
path provides high performance bandwidth into display memory allowing for fast screen
updates.
Products requiring a rotated display image can take advantage of the SwivelView TM feature
which provides hardware rotation of the display memory transparent to the software application. The S1D13706 also provides support for “Picture-in-Picture Plus” (a variable size
Overlay window).
The S1D13706 provides impressive support for Palm OS handhelds, however its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety
of applications.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 12
Epson Research and Development
Vancouver Design Center
2 Features
2.1 Integrated Frame Buffer
• Embedded 80K byte SRAM display buffer.
2.2 CPU Interface
• Direct support of the following interfaces:
Generic MPU bus interface using WAIT# signal.
Hitachi SH-3.
Hitachi SH-4.
Motorola M68K.
Motorola MC68EZ328/MC68VZ328 DragonBall.
Motorola “REDCAP2” - no WAIT# signal.
• 8-bit processor support with “glue logic”.
• “Fixed” low-latency CPU access times.
• Registers are memory-mapped - M/R# input selects between memory and register
address space.
• The complete 80K byte display buffer is directly and contiguously available through the
17-bit address bus.
• Single level CPU write buffer.
2.3 Display Support
• Single-panel, single-drive passive displays.
• 4/8-bit monochrome LCD interface.
• 4/8/16-bit color LCD interface.
• Active Matrix TFT interface.
• 9/12/18-bit interface.
• ‘Direct’ support for 18-bit Epson D-TFD interface.
• ‘Direct’ support for 18-bit Sharp HR-TFT interface.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 13
2.4 Display Modes
• 1/2/4/8/16 bit-per-pixel (bpp) color depths.
• Up to 64 gray shades using Frame Rate Modulation (FRM) and dithering on monochrome passive LCD panels.
• Up to 64K colors on passive STN panels.
• Up to 64K colors on active matrix LCD panels.
• Example resolutions:
320x240 at a color depth of 8 bpp
160x160 at a color depth of 16 bpp
160x240 at a color depth of 16 bpp
2.5 Display Features
• SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image.
• “Picture-in-Picture Plus”: displays a variable size window overlaid over background
image.
• Double Buffering/Multi-pages: provides smooth animation and instantaneous screen
updates.
2.6 Clock Source
• Two clock inputs: CLKI and CLKI2. It is possible to use one clock input only.
• Bus clock is derived from CLKI and can be internally divided by 2, 3, or 4.
• Memory clock is derived from bus clock. It can be internally divided by 2, 3, or 4.
• Pixel clock can be derived from CLKI, CLKI2, bus clock, or memory clock. It can be
internally divided by 2, 3, 4, or 8.
2.7 Miscellaneous
• Hardware/Software Video Invert.
• Software Power Save mode.
• General Purpose Input/Output pins are available.
• 100-pin TQFP15 package.
• 104-pin CFLGA package.
• Die form available.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 14
Epson Research and Development
Vancouver Design Center
3 Typical System Implementation Diagrams
.
Oscillator
BS#
A[27:17]
FPDAT[15:0]
M/R#
Decoder
FPFRAME
CSn#
CS#
FPLINE
A[16:1]
AB[16:1]
FPSHIFT
D[15:0]
DB[15:0]
DRDY
WE0#
WE0#
WE1#
WE1#
RD0#
RD#
RD1#
RD/WR#
WAIT#
S1D13706
16-bit
Single
FPFRAME LCD
Display
D[15:0]
FPLINE
FPSHIFT
MOD
Bias Power
HIOVDD
CLKI2
Generic #1
BUS
GPO
WAIT#
BUSCLK
CLKI
RESET#
RESET#
AB0
VSS
Figure 3-1: Typical System Diagram (Generic #1 Bus)
.
VDD
BS#
RD/WR#
A[27:17]
CSn#
Decoder
FPDAT[8:0]
M/R#
FPFRAME
CS#
FPLINE
A[16:0]
AB[16:0]
FPSHIFT
D[15:0]
DB[15:0]
DRDY
WE#
WE0#
BHE#
WE1#
RD#
WAIT#
S1D13706
D[8:0]
FPFRAME
FPLINE
FPSHIFT
DRDY
9-bit
TFT
Display
Bias Power
Generic #2
BUS
CLKI2
Oscillator
GPO
RD#
WAIT#
BUSCLK
CLKI
RESET#
RESET#
Figure 3-2: Typical System Diagram (Generic #2 Bus)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 15
.
Oscillator
M/R#
Decoder
FPDAT15
FPDAT12
CSn#
FPDAT[9:0]
CS#
A[16:1]
FPFRAME
AB[16:1]
D[15:0]
FPLINE
DB[15:0]
WE0#
FPSHIFT
WE0#
WE1#
WE1#
BS#
BS#
RD/WR#
DRDY
D[9:0]
FPFRAME
FPLINE
FPSHIFT
DRDY
S1D13706
GPO
RD/WR#
RD#
12-bit
TFT
Display
D11
D10
Bias Power
A[25:17]
CLKI2
SH-4
BUS
RD#
RDY#
WAIT#
CKIO
CLKI
RESET#
RESET#
AB0
VSS
Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus)
.
Oscillator
M/R#
Decoder
FPDAT[17:0]
CSn#
FPFRAME
CS#
A[16:1]
AB[16:1]
D[15:0]
DB[15:0]
WE0#
FPLINE
FPSHIFT
WE0#
WE1#
WE1#
BS#
BS#
RD/WR#
RD/WR#
RD#
DRDY
S1D13706
D[17:0]
FPFRAME
FPLINE
FPSHIFT
DRDY
18-bit
TFT
Display
Bias Power
A[25:17]
CLKI2
SH-3
BUS
GPO
RD#
WAIT#
WAIT#
CKIO
CLKI
RESET#
RESET#
AB0
VSS
Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus)
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 16
Epson Research and Development
Vancouver Design Center
.
Oscillator
RD#
WE0#
A[23:17]
FC0, FC1
Decoder
FPDAT[17:0]
D[17:0]
SPS
FPFRAME
FPLINE
M/R#
LP
FPSHIFT
Decoder
CS#
A[16:1]
AB[16:1]
D[15:0]
DB[15:0]
LDS#
AB0
UDS#
WE1#
AS#
S1D13706
18-bit
HR-TFT
Display
CLK
GPIO0
PS
GPIO1
CLS
GPIO2
REV
GPIO3
SPL
Bias Power
HIOVDD
CLKI2
MC68K #1
BUS
GPO
BS#
R/W#
RD/WR#
DTACK#
WAIT#
CLK
CLKI
RESET#
RESET#
Figure 3-5: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)
.
Oscillator
Decoder
Decoder
M/R#
FPDAT[17:0]
D[17:0]
DY
LP
FPFRAME
FPLINE
CS#
FPSHIFT
A[16:0]
AB[16:0]
D[31:16]
DB[15:0]
XSCL
DRDY
GCP
GPIO0
XINH
GPIO1
YSCL
DS#
WE1#
GPIO2
FR
AS#
BS#
GPIO3
FRS
GPIO4
RES
RD#
GPIO5
DD_P1
SIZ0
WE0#
GPIO6
YSCLD
DSACK1#
WAIT#
R/W#
SIZ1
CLK
RESET#
RD/WR#
CLKI
S1D13706
18-bit
D-TFD
Display
XSET (Bias Power)
A[31:17]
FC0, FC1
CLKI2
MC68K #2
BUS
GPO
RESET#
Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 17
.
Oscillator
CLKI2
HIOVDD
BS#
A[21:17]
M/R#
Decoder
CSn
FPDAT[7:4]
CS#
A[16:1]
AB[16:1]
D[15:0]
DB[15:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
R/W
RD/WR#
OE
S1D13706
D[3:0]
FPSHIFT
4-bit
Single
LCD
Display
FPFRAME
FPLINE
MOD
Bias Power
REDCAP2
BUS
GPO
RD#
EB1
WE0#
EB0
WE1#
CLK
CLKI
RESET_OUT
RESET#
AB0
VSS
*Note: CSn# can be any of CS0-CS4
Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus)
.
HIOVDD
BS#
FPDAT[7:0]
RD/WR#
A[25:17]
FPSHIFT
M/R#
Decoder
CSX
FPFRAME
CS#
A[16:1]
FPLINE
AB[16:1]
D[15:0]
DB[15:0]
LWE
WE0#
UWE
WE1#
OE
DRDY
S1D13706
D[7:0]
FPSHIFT
FPFRAME
FPLINE
MOD
8-bit
Single
LCD
Display
Bias Power
MC68EZ328/
MC68VZ328
DragonBall
BUS
CLKI2
Oscillator
GPO
RD#
WAIT#
DTACK
CLKO
CLKI
RESET
RESET#
AB0
VSS
Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus)
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 18
Epson Research and Development
Vancouver Design Center
4 Pins
4.1 Pinout Diagram - TQFP15 - 100pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
COREVDD
FPFRAME
FPLINE
FPSHIFT
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
VSS
NIOVDD
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
FPDAT16
FPDAT17
VSS
NIOVDD
73
74
75
76
VSS
77
CLKI2
78
CNF7
DRDY
79
CNF6
GPO
80
CNF5
CVOUT
81
CNF4
GPIO0
82
CNF3
GPIO1
83
CNF2
GPIO2
84
CNF1
GPIO3
85
CNF0
GPIO4
86
TESTEN
GPIO5
87
AB16
GPIO6
88
AB15
89
AB14
NIOVDD
90
AB13
VSS
91
AB12
DB0
92
AB11
DB1
93
AB10
DB2
94
AB9
DB3
95
AB8
DB4
NIOVDD
S1D13706
PWMOUT
96
AB7
DB5
97
AB6
DB6
AB5
DB7
98
DB8
HIOVDD
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DB9
DB10
DB11
DB12
DB13
DB14
DB15
WAIT#
HIOVDD
CLKI
VSS
RESET#
WE1#
RD#
BS#
M/R#
CS#
AB0
AB1
AB2
AB3
RD/WR#
VSS
WE0#
AB4
COREVDD
99
100
50
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
9
10
8
7
6
5
4
3
2
1
Figure 4-1: Pinout Diagram - TQFP15 - 100pin (S1D13706F00A)
Note
Package type: 100 pin surface mount TQFP15
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 19
4.2 Pinout Diagram - Die Form
170
165
160
155
150
145
140
135
130
125
120
175
DIE No. X5534D
Unusable Pad
180
115
185
110
190
105
Y
195
100
200
95
205
90
X
85
210
(0,0)
215
80
220
75
225
70
230
65
235
60
Unusable Pad
1
5
10
15
20
25
30
35
40
45
50
55
Figure 4-2: Pinout Diagram - Die Form (S1D13706D00A)
Chip Size: 5.88 x 6.55 mm
PAD size: 68 x 68 µm
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 20
Epson Research and Development
Vancouver Design Center
Table 4-1: Pinout Assignments - Die Form (S1D13706D00A)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
S1D13706
X31B-A-001-09
Pad No.
1
3
5
8
10
12
15
17
20
22
24
27
29
31
34
36
39
41
43
46
48
50
53
55
58
60
62
65
67
70
72
74
77
79
81
84
86
89
91
93
96
98
100
103
105
108
110
112
115
117
Pin Name
LVDD
AB3
AB2
AB1
AB0
CS#
M/R#
BS#
RD#
WE0#
WE1#
RD/WR#
RESET#
VSS
CLKI
HVDD
WAIT#
DB15
DB14
DB13
DB12
DB11
DB10
DB9
VSS
HVDD
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VSS
HVDD
PWMOUT
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
CVOUT
GPO
DRDY
HVDD
VSS
X (µm)
-2331
-2100
-1932
-1680
-1512
-1344
-1092
-924
-672
-504
-336
-84
84
252
504
672
924
1092
1260
1512
1680
1848
2100
2331
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
2813
Y (µm)
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-3149
-2478
-2310
-2142
-1890
-1722
-1470
-1302
-1134
-882
-714
-546
-294
-126
126
294
462
714
882
1050
1302
1470
1722
1890
2058
2310
2478
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pad No.
119
122
124
127
129
131
134
136
139
141
143
146
148
150
153
155
158
160
162
165
167
169
172
174
177
179
181
184
186
189
191
193
196
198
200
203
205
208
210
212
215
217
219
222
224
227
229
231
234
236
Pin Name
LVDD
FPFRAME
FPLINE
FPSHIFT
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
VSS
HVDD
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
FPDAT16
FPDAT17
VSS
HVDD
CLKI2
CNF7
CNF6
CNF5
CNF4
CNF3
CNF2
CNF1
CNF0
TESTEN
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
VSS
X (µm)
2813
2100
1932
1680
1512
1344
1092
924
672
504
336
84
-84
-252
-504
-672
-924
-1092
-1260
-1512
-1680
-1848
-2100
-2331
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
-2813
Y (µm)
2667
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
3149
2478
2310
2142
1890
1722
1470
1302
1134
882
714
546
294
126
-126
-294
-462
-714
-882
-1050
-1302
-1470
-1722
-1890
-2058
-2310
-2478
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 21
4.3 Pin Descriptions
Key:
I
O
IO
P
LIS
LI
LB2A
LB3P
LO3
LB3M
T1
Hi-Z
=
=
=
=
=
=
=
=
=
=
=
=
Input
Output
Bi-Directional (Input/Output)
Power pin
LVTTLa Schmitt input
LVTTL input
LVTTL IO buffer ([email protected])
Low noise LVTTL IO buffer ([email protected])
Low noise LVTTL Output buffer ([email protected])
Low noise LVTTL IO buffer with input mask ([email protected])
Test mode control input with pull-down resistor (typical value of 50Ω at 3.3V)
High Impedance
a
LVTTL is Low Voltage TTL (see Section 5, “D.C. Characteristics” on page 31).
4.3.1 Host Interface
Table 4-2: Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
RESET#
Voltage State
Description
This input pin has multiple functions.
AB0
I
5
LIS
HIOVDD
0
• For Generic #1, this pin is not used and should be connected
to VSS.
• For Generic #2, this pin inputs system address bit 0 (A0).
• For SH-3/SH-4, this pin is not used and should be connected
to VSS.
• For MC68K #1, this pin inputs the lower data strobe (LDS#).
• For MC68K #2, this pin inputs system address bit 0 (A0).
• For REDCAP2, this pin is not used and should be connected
to VSS.
• For DragonBall, this pin is not used and should be connected
to VSS.
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
AB[16:1]
I
87-99,
2-4
Hardware Functional Specification
Issue Date: 2004/02/09
LI
HIOVDD
0
System address bus bits 16-1.
S1D13706
X31B-A-001-09
Page 22
Epson Research and Development
Vancouver Design Center
Table 4-2: Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
RESET#
Voltage State
Description
Input data from the system data bus.
DB[15:0]
IO
18-24,
27-35
LB2A
HIOVDD
Hi-Z
•
•
•
•
•
For Generic #1, these pins are connected to D[15:0].
For Generic #2, these pins are connected to D[15:0].
For SH-3/SH-4, these pins are connected to D[15:0].
For MC68K #1, these pins are connected to D[15:0].
For MC68K #2, these pins are connected to D[31:16] for a 32bit device (e.g. MC68030) or D[15:0] for a 16-bit device (e.g.
MC68340).
• For REDCAP2, these pins are connected to D[15:0].
• For DragonBall, these pins are connected to D[15:0].
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
This input pin has multiple functions.
WE0#
I
10
LIS
HIOVDD
1
• For Generic #1, this pin inputs the write enable signal for the
lower data byte (WE0#).
• For Generic #2, this pin inputs the write enable signal (WE#)
• For SH-3/SH-4, this pin inputs the write enable signal for data
byte 0 (WE0#).
• For MC68K #1, this pin must be tied to HIO VDD
• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
• For REDCAP2, this pin inputs the byte enable signal for the
D[7:0] data byte (EB1).
• For DragonBall, this pin inputs the byte enable signal for the
D[7:0] data byte (LWE).
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
This input pin has multiple functions.
WE1#
I
11
LIS
HIOVDD
1
• For Generic #1, this pin inputs the write enable signal for the
upper data byte (WE1#).
• For Generic #2, this pin inputs the byte enable signal for the
high data byte (BHE#).
• For SH-3/SH-4, this pin inputs the write enable signal for data
byte 1 (WE1#).
• For MC68K #1, this pin inputs the upper data strobe (UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For REDCAP2, this pin inputs the byte enable signal for the
D[15:8] data byte (EB0).
• For DragonBall, this pin inputs the byte enable signal for the
D[15:8] data byte (UWE).
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
CS#
M/R#
S1D13706
X31B-A-001-09
I
I
6
7
LI
LIS
HIOVDD
HIOVDD
1
Chip select input. See Table 4-8: “Host Bus Interface Pin Mapping,”
on page 29 for summary.
0
This input pin is used to select between the display buffer and
register address spaces of the S1D13706. M/R# is set high to
access the display buffer and low to access the registers. See
Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 23
Table 4-2: Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
RESET#
Voltage State
Description
This input pin has multiple functions.
BS#
I
8
LIS
HIOVDD
1
•
•
•
•
•
•
•
For Generic #1, this pin must be tied to HIO VDD.
For Generic #2, this pin must be tied to HIO VDD.
For SH-3/SH-4, this pin inputs the bus start signal (BS#).
For MC68K #1, this pin inputs the address strobe (AS#).
For MC68K #2, this pin inputs the address strobe (AS#).
For REDCAP2, this pin must be tied to HIO VDD.
For DragonBall, this pin must be tied to HIO VDD.
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
This input pin has multiple functions.
RD/WR#
I
12
LIS
HIOVDD
1
• For Generic #1, this pin inputs the read command for the
upper data byte (RD1#).
• For Generic #2, this pin must be tied to HIO VDD.
• For SH-3/SH-4, this pin inputs the RD/WR# signal. The
S1D13706 needs this signal for early decode of the bus cycle.
• For MC68K #1, this pin inputs the R/W# signal.
• For MC68K #2, this pin inputs the R/W# signal.
• For REDCAP2, this pin inputs the R/W signal.
• For DragonBall, this pin must be tied to HIO VDD.
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
This input pin has multiple functions.
RD#
I
9
LIS
HIOVDD
1
• For Generic #1, this pin inputs the read command for the
lower data byte (RD0#).
• For Generic #2, this pin inputs the read command (RD#).
• For SH-3/SH-4, this pin inputs the read signal (RD#).
• For MC68K #1, this pin must be tied to HIO VDD.
• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
• For REDCAP2, this pin inputs the output enable (OE).
• For DragonBall, this pin inputs the output enable (OE).
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 24
Epson Research and Development
Vancouver Design Center
Table 4-2: Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
RESET#
Voltage State
Description
During a data transfer, this output pin is driven active to force the
system to insert wait states. It is driven inactive to indicate the
completion of a data transfer. WAIT# is released to the high
impedance state after the data transfer is complete. Its active
polarity is configurable. See Table 4-7: “Summary of PowerOn/Reset Options,” on page 28.
WAIT#
O
17
LB2A
HIOVDD
Hi-Z
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
• For SH-3 mode, this pin outputs the wait request signal
(WAIT#).
• For SH-4 mode, this pin outputs the device ready signal
(RDY#).
• For MC68K #1, this pin outputs the data transfer acknowledge
signal (DTACK#).
• For MC68K #2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#).
• For REDCAP2, this pin is unused (Hi-Z).
• For DragonBall, this pin outputs the data transfer
acknowledge signal (DTACK).
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
RESET#
S1D13706
X31B-A-001-09
I
13
LIS
HIOVDD
0
Active low input to set all internal registers to the default state and
to force all signals to their inactive states.
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 25
4.3.2 LCD Interface
Table 4-3: LCD Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
RESET#
Voltage State
FPDAT[17:0]
O
74-64,
61-55
LB3P
NIOVDD
0
Description
Panel Data bits 17-0.
This output pin has multiple functions.
FPFRAME
O
52
LB3P
NIOVDD
0
• Frame Pulse
• SPS for Sharp HR-TFT
• DY for Epson D-TFD
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This output pin has multiple functions.
FPLINE
O
53
LB3P
NIOVDD
0
• Line Pulse
• LP for Sharp HR-TFT
• LP for Epson D-TFD
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This output pin has multiple functions.
FPSHIFT
O
54
LB3P
NIOVDD
0
• Shift Clock
• CLK for Sharp HR-TFT
• XSCL for Epson D-TFD
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This output pin has multiple functions.
DRDY
O
48
LO3
NIOVDD
0
• Display enable (DRDY) for TFT panels
• 2nd shift clock (FPSHIFT2) for passive LCD with Format 1
interface
• GCP for Epson D-TFD
• LCD backplane bias signal (MOD) for all other LCD panels
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This pin has multiple functions.
GPIO0
IO
45
LB3M
NIOVDD
0
•
•
•
•
PS for Sharp HR-TFT
XINH for Epson D-TFD
General purpose IO pin 0 (GPIO0)
Hardware Video Invert
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This pin has multiple functions.
GPIO1
IO
44
LB3M
NIOVDD
0
• CLS for Sharp HR-TFT
• YSCL for Epson D-TFD
• General purpose IO pin 1 (GPIO1)
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 26
Epson Research and Development
Vancouver Design Center
Table 4-3: LCD Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
RESET#
Voltage State
Description
This pin has multiple functions.
GPIO2
IO
43
LB3M
NIOVDD
0
• REV for Sharp HR-TFT
• FR for Epson D-TFD
• General purpose IO pin 2 (GPIO2)
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This pin has multiple functions.
GPIO3
IO
42
LB3M
NIOVDD
0
• SPL for Sharp HR-TFT
• FRS for Epson D-TFD
• General purpose IO pin 3 (GPIO3)
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This pin has multiple functions.
GPIO4
IO
41
LB3M
NIOVDD
0
• RES for Epson D-TFD
• General purpose IO pin 4 (GPIO4)
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This pin has multiple functions.
GPIO5
IO
40
LB3M
NIOVDD
0
• DD_P1 for Epson D-TFD
• General purpose IO pin 5 (GPIO5)
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This pin has multiple functions.
GPIO6
IO
39
LB3M
NIOVDD
0
• YSCLD for Epson D-TFD
• General purpose IO pin 6 (GPIO6)
See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
summary.
This output pin has multiple functions.
PWMOUT
O
38
LB3P
NIOVDD
0
• PWM Clock output
• General purpose output
This output pin has multiple functions.
CVOUT
S1D13706
X31B-A-001-09
O
46
LB3P
NIOVDD
0
• CV Pulse Output
• General purpose output
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 27
4.3.3 Clock Input
Table 4-4: Clock Input Pin Descriptions
IO
RESET#
Voltage State
Description
Pin Name
Type
Pin #
Cell
CLKI
I
15
LI
NIOVDD
—
Typically used as input clock source for bus clock and memory
clock
CLKI2
I
77
LI
NIOVDD
—
Typically used as input clock source for pixel clock
4.3.4 Miscellaneous
Table 4-5: Miscellaneous Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
RESET#
Voltage State
Description
These inputs are used to configure the S1D13706 - see Table 4-7:
“Summary of Power-On/Reset Options,” on page 28.
CNF[7:0]
I
78-85
LI
NIOVDD
—
GPO
O
47
LO3
NIOVDD
0
General Purpose Output (possibly used for controlling the LCD
power). It may also be used for the MOD control signal of the Sharp
HR-TFT panel.
TESTEN
I
86
T1
NIOVDD
0
Test Enable input used for production test only (has type 1 pulldown resistor with a typical value of 50Ω at 3.3V).
Note: These pins are used for configuration of the S1D13706
and must be connected directly to IO VDD or VSS.
4.3.5 Power And Ground
Table 4-6: Power And Ground Pin Descriptions
Pin Name
Type
Pin #
Cell
HIOVDD
P
16, 26
P
NIOVDD
P
37, 49,
63, 76
P
COREVDD
P
1, 51
P
14, 25,
36, 50,
62, 75,
100
VSS
Hardware Functional Specification
Issue Date: 2004/02/09
IO
RESET#
Voltage State
Description
—
IO VDD pins associated with the host interface pins as described in
Section 4.3.1, “Host Interface” on page 21.
—
—
IO VDD pins associated with the non-host interface pins as
described in Section 4.3.2, “LCD Interface” on page 25, Section
4.3.3, “Clock Input” on page 27, and Section 4.3.4, “Miscellaneous”
on page 27.
P
—
—
2 Core VDD. pins.
P
—
—
7 VSS pins.
—
S1D13706
X31B-A-001-09
Page 28
Epson Research and Development
Vancouver Design Center
4.4 Summary of Configuration Options
These pins are used for configuration of the S1D13706 and must be connected directly to
NIOVDD or VSS. The state of CNF[6:0] is latched on the rising edge of RESET#. Changing
state at any other time has no effect.
Table 4-7: Summary of Power-On/Reset Options
S1D13706
Configuration
Input
Power-On/Reset State
1 (connected to NIOVDD)
0 (Connected to VSS)
Select host bus interface as follows:
CNF4,CNF[2:0]
CNF4
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
CNF2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
CNF1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
CNF0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Host Bus
SH-4/SH-3 interface, Big Endian
SH-4/SH-3 interface, Little Endian
MC68K #1, Big Endian
Reserved
MC68K #2, Big Endian
Reserved
Generic #1, Big Endian
Generic #1, Little Endian
Reserved
Generic #2, Little Endian
REDCAP2, Big Endian
Reserved
DragonBall (MC68EZ328/MC68VZ328), Big Endian
Reserved
Reserved
Note: The host bus interface is 16-bit only.
CNF3
Configure GPIO pins as inputs at power-on
Configure GPIO pins as outputs at power-on (for use
by HR-TFT/D-TFD when selected)
CNF5
WAIT# is active high
WAIT# is active low
CLKI to BCLK divide select:
CNF[7:6]
S1D13706
X31B-A-001-09
CNF7
0
0
1
1
CNF6
0
1
0
1
CLKI to BCLK Divide Ratio
1:1
2:1
3:1
4:1
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 29
4.5 Host Bus Interface Pin Mapping
Table 4-8: Host Bus Interface Pin Mapping
Generic #2
Hitachi
SH-3 /SH-4
Motorola
MC68K #1
Motorola
MC68K #2
Motorola
REDCAP2
Motorola
MC68EZ328/
MC68VZ328
DragonBall
A[16:1]
A[16:1]
A[16:1]
A[16:1]
A[16:1]
A[16:1]
S1D13706
Pin Name
Generic #1
AB[16:1]
A[16:1]
AB0
A01
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
CS#
External Decode
1
CSn#
M/R#
CLKI
BS#
LDS#
A0
A0
A01
D[15:0]
D[15:0]2
D[15:0]
D[15:0]
CSn
CSX
CLK
CLKO
External Decode
1
External Decode
BUSCLK
BUSCLK
Connected to VDD
CKIO
CLK
CLK
BS#
AS#
AS#
Connected to VDD
RD/WR#
R/W#
R/W#
R/W
Connected to
VDD
RD/WR#
RD1#
Connected to
VDD
RD#
RD0#
RD#
RD#
Connected to
VDD
SIZ1
OE
OE
WE0#
WE0#
WE#
WE0#
Connected to
VDD
SIZ0
EB1
LWE
WE1#
WE1#
BHE#
WE1#
UDS#
DS#
EB0
UWE
WAIT#
WAIT#
WAIT#
WAIT#/
RDY#
DTACK#
DSACK1#
N/A
DTACK
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET_OUT
RESET
Note
1 A0 for these busses is not used internally by the S1D13706 and should be connected to V .
SS
2 If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 30
Epson Research and Development
Vancouver Design Center
4.6 LCD Interface Pin Mapping
Table 4-9: LCD Interface Pin Mapping
Monochrome Passive
Panel
Pin Name
Color Passive Panel
Single
Single
4-bit
Color TFT Panel
4-bit
Others
Format 2
8-bit
16-Bit
18-bit
18-bit
SPS
DY
FPLINE
FPLINE
LP
LP
FPSHIFT
FPSHIFT
DCLK
XSCL
FPSHIFT2
MOD
12-bit
18-bit
Epson
D-TFD1
FPFRAME
MOD
9-bit
Sharp HRTFT1
FPFRAME
DRDY
8-bit
Format 1
8-bit
DRDY
no connect
GCP
FPDAT0
driven 0
D0
driven 0
D0 (B5)2
D0 (G3)2
D0 (R6)2
R2
R3
R5
R5
R5
FPDAT1
driven 0
D1
driven 0
D1 (R5)2
D1 (R3)2
D1 (G5)2
R1
R2
R4
R4
R4
FPDAT2
driven 0
D2
driven 0
D2 (G4)2
D2 (B2)2
D2 (B4)2
R0
R1
R3
R3
R3
FPDAT3
driven 0
D3
driven 0
D3 (B3)2
D3 (G2)2
D3 (R4)2
G2
G3
G5
G5
G5
FPDAT4
D0
D4
D0 (R2)2
D4 (R3)2
D4 (R2)2
D8 (B5)2
G1
G2
G4
G4
G4
FPDAT5
D1
D5
D1 (B1)2
D5 (G2)2
D5 (B1)2
D9 (R5)2
G0
G1
G3
G3
G3
FPDAT6
D2
D6
D2 (G1)2
D6 (B1)2
D6 (G1)2
D10 (G4)2
B2
B3
B5
B5
B5
FPDAT7
D3
D7
D3 (R1)2
D7 (R1)2
D7 (R1)2
D11 (B3)2
B1
B2
B4
B4
B4
FPDAT8
driven 0
driven 0
driven 0
driven 0
driven 0
D4 (G3)2
B0
B1
B3
B3
B3
FPDAT9
driven 0
driven 0
driven 0
driven 0
driven 0
D5 (B2)2
driven 0
R0
R2
R2
R2
FPDAT10
driven 0
driven 0
driven 0
driven 0
driven 0
D6 (R2)2
driven 0
driven 0
R1
R1
R1
FPDAT11
driven 0
driven 0
driven 0
driven 0
driven 0
D7 (G1)2
driven 0
driven 0
R0
R0
R0
FPDAT12
driven 0
driven 0
driven 0
driven 0
driven 0
D12 (R3)2
driven 0
G0
G2
G2
G2
FPDAT13
driven 0
driven 0
driven 0
driven 0
driven 0
D13 (G2)2
driven 0
driven 0
G1
G1
G1
FPDAT14
driven 0
driven 0
driven 0
driven 0
driven 0
D14 (B1)2
driven 0
driven 0
G0
G0
G0
FPDAT15
driven 0
driven 0
driven 0
driven 0
driven 0
D15 (R1)2
driven 0
B0
B2
B2
B2
FPDAT16
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
B1
B1
B1
FPDAT17
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
B0
B0
B0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
PS
XINH
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
CLS
YSCL
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
REV
FR
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
SPL
FRS
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
(output only)
RES
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
(output only)
DD_P1
GPIO6
GPIO6
(output only)
YSCLD
GPIO6
GPIO6
GPIO6
GPO
GPIO6
GPIO6
GPIO6
GPIO6
GPO (General Purpose Output)
CVOUT
CVOUT
PWMOUT
PWMOUT
GPIO6
GPIO6
MOD
3
GPO
Note
1
GPIO pins must be configured as outputs (CNF3 = 0 at RESET#) when the HR-TFT or
D-TFD interface is selected.
2
These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
Section 6.4, “Display Interface” on page 56.
3 When the HR-TFT interface is selected (REG[10h] bits 1-0 = 10), this GPO can be
used to control the HR-TFT MOD signal. Note this is not the same signal as the
S1D13706 DRDY(MOD) signal used for passive panels.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 31
5 D.C. Characteristics
Table 5-1: Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
Core VDD
Supply Voltage
VSS - 0.3 to 4.0
V
IO VDD
Supply Voltage
VSS - 0.3 to 4.0
V
VIN
Input Voltage
VSS - 0.3 to IO VDD + 0.5
V
VOUT
Output Voltage
VSS - 0.3 to IO VDD + 0.5
V
TSTG
Storage Temperature
-65 to 150
°C
TSOL
Solder Temperature/Time
260 for 10 sec. max at lead
°C
Table 5-2: Recommended Operating Conditions
Symbol
Parameter
Condition
Min
Typ
Max
Units
1.8
2.0
2.2
V
3.0
3.3
3.6
V
1.8
2.0
2.2
V
3.0
3.3
3.6
V
3.0
3.3
3.6
V
IO VDD
V
Core VDD
Supply Voltage
VSS = 0 V
HIO VDD
Supply Voltage
VSS = 0 V
NIO VDD
Supply Voltage
VSS = 0 V
VIN
Input Voltage
VSS
TOPR
Operating Temperature
-40
25
°C
85
Note
The S1D13706 requires that Core VDD ≤ HIO VDD and Core VDD ≤ NIO VDD.
Table 5-3: Electrical Characteristics for VDD = 3.3V typical
Symbol
IDDS
IIZ
IOZ
Parameter
Quiescent Current
Input Leakage Current
Output Leakage Current
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VIH
VIL
VT+
VTVH1
RPD
CI
CO
CIO
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
Pull Down Resistance
Input Pin Capacitance
Output Pin Capacitance
Bi-Directional Pin Capacitance
Hardware Functional Specification
Issue Date: 2004/02/09
Condition
Quiescent Conditions
Min
Typ
-1
-1
VDD = min
IOH =
-6mA (Type 2)
-12mA (Type 3)
VDD = min
IOL =
6mA (Type 2)
12mA (Type 3)
LVTTL Level, VDD = max
LVTTL Level, VDD = min
LVTTL Schmitt
LVTTL Schmitt
LVTTL Schmitt
VI = VDD
Max
170
1
1
VDD - 0.4
V
0.4
2.0
1.1
0.6
0.1
20
Units
µA
µA
µA
0.8
2.4
1.8
50
120
10
10
10
V
V
V
V
V
V
kΩ
pF
pF
pF
S1D13706
X31B-A-001-09
Page 32
Epson Research and Development
Vancouver Design Center
6 A.C. Characteristics
Conditions:
HIO VDD = 2.0V ± 10% and HIO VDD = 3.3V ± 10%
NIO VDD = 3.3V ± 10%
TA = -40° C to 85° C
Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%)
CL = 50pF (Bus/MPU Interface)
CL = 0pF (LCD Panel Interface)
6.1 Clock Timing
6.1.1 Input Clocks
Clock Input Waveform
t
t
PWH
PWL
90%
V
IH
VIL
10%
t
tr
f
TOSC
Figure 6-1: Clock Input Requirements
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
Symbol
Parameter
fOSC
Input Clock Frequency (CLKI)
TOSC
Input Clock period (CLKI)
tPWH
tPWL
2.0V
Min
3.3V
Max
Min
40
Max
100
Units
MHz
1/fOSC
1/fOSC
ns
Input Clock Pulse Width High (CLKI)
4.5
4.5
ns
Input Clock Pulse Width Low (CLKI)
4.5
4.5
ns
tf
Input Clock Fall Time (10% - 90%)
5
5
ns
tr
Input Clock Rise Time (10% - 90%)
5
5
ns
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
34 for internal clock requirements.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 33
Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1
Symbol
Parameter
fOSC
Input Clock Frequency (CLKI)
TOSC
Input Clock period (CLKI)
tPWH
tPWL
2.0V
Min
3.3V
Max
Min
Max
20
66
Units
MHz
1/fOSC
1/fOSC
ns
Input Clock Pulse Width High (CLKI)
3
3
ns
Input Clock Pulse Width Low (CLKI)
3
3
ns
tf
Input Clock Fall Time (10% - 90%)
5
5
ns
tr
Input Clock Rise Time (10% - 90%)
5
5
ns
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
34 for internal clock requirements.
Table 6-3: Clock Input Requirements for CLKI2
Symbol
Parameter
fOSC
Input Clock Frequency (CLKI2)
TOSC
Input Clock period (CLKI2)
tPWH
tPWL
2.0V
Min
3.3V
Max
Min
20
Max
66
Units
MHz
1/fOSC
1/fOSC
ns
Input Clock Pulse Width High (CLKI2)
3
3
ns
Input Clock Pulse Width Low (CLKI2)
3
3
ns
tf
Input Clock Fall Time (10% - 90%)
5
5
ns
tr
Input Clock Rise Time (10% - 90%)
5
5
ns
Note
Maximum internal requirements for clocks derived from CLKI2 must be considered
when determining the frequency of CLKI2. See Section 6.1.2, “Internal Clocks” on page
34 for internal clock requirements.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 34
Epson Research and Development
Vancouver Design Center
6.1.2 Internal Clocks
Table 6-4: Internal Clock Requirements
Symbol
Parameter
2.0V
Min
3.3V
Max
Min
Max
Units
fBCLK
Bus Clock frequency
20
66
MHz
fMCLK
Memory Clock frequency
20
50
MHz
fPCLK
Pixel Clock frequency
20
50
MHz
fPWMCLK PWM Clock frequency
20
66
MHz
Note
For further information on internal clocks, refer to Section 7, “Clocks” on page 90.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 35
6.2 CPU Interface Timing
The following section includes CPU interface AC Timing for both 2.0V and 3.3V. The
2.0V timings are based on HIO VDD = Core VDD = 2.0V. The 3.3V timings are based on
HIO VDD = Core VDD = 3.3V.
6.2.1 Generic #1 Interface Timing
TCLK
t1
t2
CLK
t4
t3
A[16:1]
M/R#
t6
t5
CS#
t7
RD0#,RD1#
WE0#,WE1#
t8
t10
t9
WAIT#
t12
t11
D[15:0](write)
t13
t14
D[15:0](read)
t15
VALID
Figure 6-2: Generic #1 Interface Timing
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 36
Epson Research and Development
Vancouver Design Center
Table 6-5: Generic #1 Interface Timing
Symbol
Parameter
fCLK
TCLK
t1
t2
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[16:1], M/R# setup to first CLK rising edge where CS# = 0 and
either RD0#, RD1# = 0 or WE0#, WE1# = 0
A[16:1], M/R# hold from either RD0#, RD1# or WE0#, WE1#
rising edge
CS# setup to CLK rising edge
CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷ 2
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷ 3
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷ 4
RD0#, RD1#, WE0#, WE1# setup to CLK rising edge
Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
driven low
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
high impedance
D[15:0] setup to third CLK rising edge where CS# = 0 and
WE0#, WE1# = 0 (write cycle) (see note 1)
D[15:0] hold from WAIT# rising edge (write cycle)
RD0#, RD1# falling edge to D[15:0] driven (read cycle)
WAIT# rising edge to D[15:0] valid (read cycle)
RD0#, RD1# rising edge to D[15:0] high impedance (read cycle)
t3
t4
t5
t6
t7a
t7b
t7c
t7d
t8
t9
t10
t11
t12
t13
t14
t15
2.0V
Min
3.3V
Max
20
Min
Max
50
Unit
1/fCLK
22.5
22.5
1/fCLK
9
9
MHz
ns
ns
ns
1
1
ns
0
0
ns
0
0
1
0
ns
ns
TCLK
TCLK
TCLK
TCLK
ns
8.5
11.5
13.5
17.5
2
8.5
11.5
13.5
17.5
1
5
31
3
15
ns
5
34
3
13
ns
1
1
4
3
0
27
0
29
0
3
3
ns
14
2
11
ns
ns
ns
ns
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 37
6.2.2 Generic #2 Interface Timing (e.g. ISA)
TBUSCLK
t1
t2
BUSCLK
t4
t3
SA[16:0]
M/R#, SBHE#
t6
t5
CS#
t7
MEMR#
MEMW#
t8
t10
t9
IOCHRDY
t12
t11
SD[15:0] (write)
t13
SD[15:0] (read)
t15
t14
VALID
Figure 6-3: Generic #2 Interface Timing
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 38
Epson Research and Development
Vancouver Design Center
Table 6-6: Generic #2 Interface Timing
Symbol
fBUSCLK
TBUSCLK
t1
t2
t3
t4
t5
t6
t7a
t7b
t7c
t7d
t8
t9
t10
t11
t12
t13
t14
t15
Parameter
2.0V
Min
Bus Clock frequency
Bus Clock period
1/fBUSCLK
Clock pulse width high
22.5
Clock pulse width low
22.5
SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge
1
where CS# = 0 and either MEMR# = 0 or MEMW# = 0
SA[16:0], M/R#, SBHE# hold from either MEMR# or MEMW#
0
rising edge
CS# setup to BUSCLK rising edge
0
CS# hold from either MEMR# or MEMW# rising edge
0
MEMR#/MEMW# asserted for MCLK = BCLK
MEMR#/MEMW# asserted for MCLK = BCLK ÷ 2
MEMR#/MEMW# asserted for MCLK = BCLK ÷ 3
MEMR#/MEMW# asserted for MCLK = BCLK ÷ 4
MEMR# or MEMW# setup to BUSCLK rising edge
2
Falling edge of either MEMR# or MEMW# to IOCHRDY driven
5
low
Rising edge of either MEMR# or MEMW# to IOCHRDY high
5
impedance
SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and
1
MEMW# = 0 (write cycle) (see note 1)
SD[15:0] hold from IOCHRDY rising edge (write cycle)
1
MEMR# falling edge to SD[15:0] driven (read cycle)
4
IOCHRDY rising edge to SD[15:0] valid (read cycle)
Rising edge of MEMR# to SD[15:0] high impedance (read
5
cycle)
3.3V
Max
20
Min
Max
50
1/fBUSCLK
9
9
MHz
ns
ns
ns
1
ns
0
ns
1
0
ns
ns
8.5
11.5
13.5
17.5
8
11
13
17
TBUSCLK
TBUSCLK
TBUSCLK
TBUSCLK
ns
3
15
ns
3
13
ns
1
0
26
0
33
Unit
0
3
3
ns
13
2
ns
ns
ns
12
ns
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 39
6.2.3 Hitachi SH-4 Interface Timing
TCKIO
t1
t2
CKIO
t3
t4
A[16:1], M/R#
RD/WR#
t5
t6
BS#
t7
t8
CSn#
t9
t10
WEn#
RD#
t12
t11
RDY#
t13
Hi-Z
Hi-Z
t15
D[15:0]
(write)
t16
Hi-Z
Hi-Z
t17
D[15:0]
(read)
t14
Hi-Z
t18
VALID
Hi-Z
Figure 6-4: Hitachi SH-4 Interface Timing
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 40
Epson Research and Development
Vancouver Design Center
Table 6-7: Hitachi SH-4 Interface Timing
Symbol
Parameter
fCKIO
Clock frequency
TCKIO
Clock period
2.0V
Min
3.3V
Max
Min
20
Max
66
Unit
MHz
1/fCKIO
1/fCKIO
ns
Clock pulse width low
22.5
6.8
ns
t2
Clock pulse width high
22.5
6.8
ns
t3
A[16:1], M/R#, RD/WR# setup to CKIO
0
1
ns
t4
t1
A[16:1], M/R#, RD/WR# hold from CSn#
0
0
ns
t5
BS# setup
3
1
ns
t6
BS# hold
7
2
ns
t7
CSn# setup
0
1
ns
t8
CSn# high setup to CKIO
0
t9a
t9b
2
ns
RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz)
8.5
8.5
TCKIO
RD# or WEn# asserted for MCLK = BCLK ÷ 2
11.5
11.5
TCKIO
t9c
RD# or WEn# asserted for MCLK = BCLK ÷ 3
13.5
13.5
TCKIO
t9d
RD# or WEn# asserted for MCLK = BCLK ÷ 4
18.5
TCKIO
Falling edge RD# to D[15:0] driven (read cycle)
5
24
3
12
ns
t11
Falling edge CSn# to RDY# driven high
3
19
3
12
ns
t12
CKIO to RDY# low
5
42
4
18
ns
t13
t10
18.5
CSn# high to RDY# high
5
35
4
14
ns
t14
Falling edge CKIO to RDY# high impedance
5
38
4
14
ns
t15
D[15:0] setup to 2nd CKIO after BS# (write cycle) (see note 1)
1
0
ns
t16
D[15:0] hold (write cycle)
0
0
ns
t17
RDY# falling edge to D[15:0] valid (read cycle)
t18
Rising edge RD# to D[15:0] high impedance (read cycle)
0
5
31
3
2
ns
12
ns
1. t15 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Minimum one software WAIT state is required.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 41
6.2.4 Hitachi SH-3 Interface Timing
TCKIO
t1
t2
CKIO
t3
t4
A[16:1], M/R#
RD/WR#
t5
t6
BS#
t7
t8
CSn#
t9
t11
t10
WEn#
RD#
t13
t12
WAIT#
Hi-Z
Hi-Z
t15
t14
D[15:0]
(write)
Hi-Z
Hi-Z
t16
D[15:0]
(read)
Hi-Z
t17
VALID
Hi-Z
Figure 6-5: Hitachi SH-3 Interface Timing
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 42
Epson Research and Development
Vancouver Design Center
Table 6-8: Hitachi SH-3 Interface Timing
Symbol
Parameter
fCKIO
Bus Clock frequency
TCKIO
Bus Clock period
2.0V
Min
3.3V
Max
Min
20
Max
66
Unit
MHz
1/fCKIO
1/fCKIO
ns
Bus Clock pulse width low
22.5
6.8
ns
t2
Bus Clock pulse width high
22.5
6.8
ns
t3
A[16:1], M/R#, RD/WR# setup to CKIO
0
1
ns
t4
t1
CSn# high setup to CKIO
0
1
ns
t5
BS# setup
3
1
ns
t6
BS# hold
7
2
ns
t7
CSn# setup
0
1
ns
t8
A[16:1], M/R#, RD/WR# hold from CS#
0
t9a
t9b
0
ns
RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz)
8.5
8.5
TCKIO
RD# or WEn# asserted for MCLK = BCLK ÷ 2
11.5
11.5
TCKIO
t9c
RD# or WEn# asserted for MCLK = BCLK ÷ 3
13.5
13.5
TCKIO
t9d
RD# or WEn# asserted for MCLK = BCLK ÷ 4
18.5
TCKIO
Falling edge RD# to D[15:0] driven (read cycle)
5
24
3
12
ns
t11
Rising edge CSn# to WAIT# high impedance
4
24
2
10
ns
t12
Falling edge CSn# to WAIT# driven low
3
24
2
12
ns
t13
CKIO to WAIT# delay
6
45
4
18
ns
t10
nd
t14
D[15:0] setup to 2
t15
D[15:0] hold (write cycle)
t16
WAIT# rising edge to D[15:0] valid (read cycle)
t17
Rising edge RD# to D[15:0] high impedance (read cycle)
CKIO after BS# (write cycle) (see note 1)
18.5
1
0
ns
0
0
ns
0
5
31
3
2
ns
12
ns
1. t14 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Minimum one software WAIT state is required.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 43
6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000)
TCLK
t1
t2
CLK
t3
t4
A[16:1]
M/R#
t6
t5
CS#
t7
t9
t8
AS#
t11
t12
t10
UDS#
LDS#
t13
t14
R/W#
t15
t16
DTACK#
t17
t18
D[15:0](write)
t19
D[15:0](read)
t20
t21
VALID
Figure 6-6: Motorola MC68K #1 Interface Timing
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 44
Epson Research and Development
Vancouver Design Center
Table 6-9: Motorola MC68K #1 Interface Timing
Symbol
Parameter
fCLK
Bus Clock Frequency
TCLK
Bus Clock period
2.0V
Min
3.3V
Max
Min
20
Max
50
Unit
MHz
1/fCLK
1/fCLK
ns
t1
Clock pulse width high
22.5
9
ns
t2
Clock pulse width low
22.5
9
ns
t3
A[16:1], M/R# setup to first CLK rising edge where CS# = 0,
AS# = 0, UDS# = 0, and LDS# = 0
1
1
ns
t4
A[16:1], M/R# hold from AS# rising edge
0
0
ns
t5
CS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0
0
1
ns
t6
CS# hold from AS# rising edge
0
0
ns
t7a
AS# asserted for MCLK = BCLK
8
8
TCLK
t7b
AS# asserted for MCLK = BCLK ÷ 2
11
11
TCLK
t7c
AS# asserted for MCLK = BCLK ÷ 3
13
13
TCLK
t7d
AS# asserted for MCLK = BCLK ÷ 4
18
18
TCLK
t8
AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0
1
1
ns
t9
AS# setup to CLK rising edge
1
2
ns
t10
UDS#/LDS# setup to CLK rising edge while CS#, AS#,
UDS#/LDS# = 0
3
1
ns
t11
UDS#/LDS# high setup to CLK rising edge
3
2
ns
t12
First CLK rising edge where AS# = 1 to DTACK# high impedance
5
t13
R/W# setup to CLK rising edge before all CS#, AS#, UDS# and/or
LDS# = 0
0
1
ns
t14
R/W# hold from AS# rising edge
0
0
ns
t15
AS# = 0 and CS# = 0 to DTACK# driven high
4
23
3
13
ns
t16
AS# rising edge to DTACK# rising edge
6
39
4
16
ns
t17
D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0 and
either UDS# = 0 or LDS# = 0 (write cycle) (see note 1)
1
0
ns
t18
D[15:0] hold from DTACK# falling edge (write cycle)
0
0
ns
t19
UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle)
4
t20
DTACK# falling edge to D[15:0] valid (read cycle)
t21
UDS#, LDS# rising edge to D[15:0] high impedance (read cycle)
40
27
3
3
0
5
33
3
14
ns
13
ns
2
ns
13
ns
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 45
6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030)
TCLK
t1
t2
CLK
t4
t3
A[16:0]
M/R#, SIZ[1:0]
t6
t5
CS#
t7
t9
t8
AS#
t11
t12
t10
DS#
t13
t14
R/W#
t16
t15
DSACK1#
t17
t18
D[31:16](write)
t19
t21
t20
D[31:16](read)
VALID
Figure 6-7: Motorola MC68K #2 Interface Timing
Note
For information on the implementation of the Motorola 68K #2 Host Bus Interface, see
Interfacing To The Motorola MC68030 Microprocessor, document number
X31B-G-013-xx.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 46
Epson Research and Development
Vancouver Design Center
Table 6-10: Motorola MC68K #2 Interface Timing
Symbol
Parameter
fCLK
Bus Clock frequency
TCLK
Bus Clock period
2.0V
Min
3.3V
Max
Min
20
Max
50
Unit
MHz
1/fCLK
1/fCLK
ns
t1
Clock pulse width high
22.5
9
ns
t2
Clock pulse width low
22.5
9
ns
t3
A[16:0], SIZ[1:0], M/R# setup to first CLK rising edge where
CS# = 0, AS# = 0, DS# = 0
1
1
ns
t4
A[16:0], SIZ[1:0], M/R# hold from AS# rising edge
0
0
ns
t5
CS# setup to CLK rising edge
0
1
ns
t6
CS# hold from AS# rising edge
0
0
ns
t7a
AS# asserted for MCLK = BCLK
8
8
TCLK
t7b
AS# asserted for MCLK = BCLK ÷ 2
11
11
TCLK
t7c
AS# asserted for MCLK = BCLK ÷ 3
13
13
TCLK
t7d
AS# asserted for MCLK = BCLK ÷ 4
18
18
TCLK
t8
AS# falling edge to CLK rising edge
1
1
ns
t9
AS# rising edge to CLK rising edge
1
3
ns
t10
DS# falling edge to CLK rising edge
1
1
ns
t11
DS# setup to CLK rising edge
1
3
ns
t12
First CLK where AS# = 1 to DSACK1# high impedance
5
t13
R/W# setup to CLK rising edge before all CS# = 0, AS# = 0, and
DS# = 0
1
40
3
14
1
ns
ns
t14
R/W# hold from AS# rising edge
0
t15
AS# = 0 and CS# = 0 to DSACK1# rising edge
4
23
3
0
14
ns
t16
AS# rising edge to DSACK1# rising edge
6
39
4
17
ns
t17
D[31:16] valid to third CLK rising edge where CS# = 0, AS# = 0,
and DS# = 0 (write cycle) (see note 1)
1
0
ns
t18
D[31:16] hold from falling edge of DSACK1# (write cycle)
0
0
ns
t19
DS# falling edge to D[31:16] driven (read cycle)
4
t20
DSACK1# falling edge to D[31:16] valid (read cycle)
t21
DS# rising edge to D[31:16] invalid/high impedance (read cycle)
32
3
0
5
36
3
ns
14
ns
2
ns
13
ns
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 47
6.2.7 Motorola REDCAP2 Interface Timing
TCKO
t1
t2
CKO
t5
M/R#
A[16:1]
R/W
CSn
t3
t4
t7
t6
EB0
EB1
(write)
t8
D[15:0]
(write)
Hi-Z
t9
Hi-Z
VALID
t11
t10
OE
EB0
EB1
(read)
t13
t14
t12
D[15:0]
(read)
Hi-Z
VALID
Hi-Z
Note: CSn may be any of CS0 - CS4.
Figure 6-8: Motorola REDCAP2 Interface Timing
Note
For further information on implementing the REDCAP2 microprocessor, see Interfacing to the Motorola REDCAP2 DSP with Integrated MCU, document number
X31B-G-013-xx.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 48
Epson Research and Development
Vancouver Design Center
Table 6-11: Motorola REDCAP2 Interface Timing
Symbol
Parameter
fCKO
Bus Clock frequency
TCKO
Bus Clock period
2.0V
Min
3.3V
Max
Min
Max
17
17
Units
MHz
1/fCKO
1/fCKO
ns
Bus Clock pulse width low
26
26
ns
t2
Bus Clock pulse width high
26
26
ns
t3
A[16:1], M/R#, R/W, CSn setup to CKO rising edge
1
1
ns
t4
t1
A[16:1], M/R#, R/W, CSn hold from CKO rising edge
0
0
ns
t5a
CSn asserted for MCLK = BCLK
8
8
TCKO
t5b
CSn asserted for MCLK = BCLK ÷ 2
10
10
TCKO
t5c
CSn asserted for MCLK = BCLK ÷ 3
13
13
TCKO
t5d
CSn asserted for MCLK = BCLK ÷ 4
15
15
TCKO
t6
EB0, EB1 asserted to CKO rising edge (write cycle)
1
1
ns
t7
EB0, EB1 de-asserted to CKO rising edge (write cycle)
1
4
ns
t8
D[15:0] input setup to 3rd CKO rising edge after EB0 or EB1
asserted low (write cycle) (see note 1)
1
0
ns
t9
D[15:0] input hold from 3rd CKO rising edge after EB0 or EB1
asserted low (write cycle)
23
8
ns
t10
OE, EB0, EB1 setup to CKO rising edge (read cycle)
1
0
ns
t11
OE, EB0, EB1 hold to CKO rising edge (read cycle)
1
0
ns
t12
D[15:0] output delay from OE, EB0, EB1 falling edge
(read cycle)
4
t13a
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK (read cycle)
t13b
10
ns
4.5CKO
+7
4.5CKO +
20
ns
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK ÷ 2 (read cycle)
7CKO +
10
6.5CKO +
20
ns
t13c
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK ÷ 3 (read cycle)
8.5CKO
+8
9.5CKO +
20
ns
t13d
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK ÷ 4 (read cycle)
9CKO +
11
11.5CKO
+ 20
ns
t14
CKO rising edge to D[15:0] output in Hi-Z (read cycle)
11
ns
4
29
31
3
1
1. t8 is the delay from when data is placed on the bus until the data is latched into the write buffer.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 49
6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328)
TCLKO
t1
t2
CLKO
t3
t4
A[16:1]
t5
t7
t6
CSX
t8
t9
UWE/LWE
(write)
t11
t10
OE
(read)
t13
t12
D[15:0]
(write)
Hi-Z
Hi-Z
t15
t14
D[15:0]
(read)
Hi-Z
Hi-Z
VALID
t19
t16
t17
t18
DTACK
Figure 6-9: Motorola DragonBall Interface with DTACK Timing
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 50
Epson Research and Development
Vancouver Design Center
Table 6-12: Motorola DragonBall Interface with DTACK Timing
MC68EZ328
Symbol
Parameter
2.0V
Min
fCLKO
Bus Clock frequency
TCLKO
Bus Clock period
MC68VZ328
3.3V
Max
Min
16
2.0V
Max
Min
16
3.3V
Max
Min
20
Unit
Max
33
MHz
1/fCLKO
1/fCLKO
1/fCLKO
1/fCLKO
ns
t1
Clock pulse width high
28.1
28.1
22.5
13.5
ns
t2
Clock pulse width low
28.1
28.1
22.5
13.5
ns
t3
A[16:1] setup 1st CLKO when CSX = 0 and either
UWE/LWE or OE = 0
0
0
0
0
ns
t4
A[16:1] hold from CSX rising edge
0
0
0
0
ns
t5a
CSX asserted for MCLK = BCLK
8
8
8
8
TCLKO
t5b
CSX asserted for MCLK = BCLK ÷ 2
11
11
11
11
TCLKO
t5c
CSX asserted for MCLK = BCLK ÷ 3
13
13
13
13
TCLKO
t5d
CSX asserted for MCLK = BCLK ÷ 4
17
TCLKO
t6
CSX setup to CLKO rising edge
0
0
0
0
ns
t7
CSX rising edge to CLKO rising edge
0
0
0
0
ns
t8
UWE/LWE falling edge to CLKO rising edge
1
0
1
0
ns
t9
UWE/LWE rising edge to CSX rising edge
0
0
0
0
ns
t10
OE falling edge to CLKO rising edge
1
1
1
1
ns
t11
OE hold from CSX rising edge
0
0
0
0
ns
t12
D[15:0] setup to 3rd CLKO when CSX,
UWE/LWE asserted (write cycle) (see note 1)
1
0
1
0
ns
t13
D[15:0] in hold from CSX rising edge (write cycle)
0
t14
Falling edge of OE to D[15:0] driven (read cycle)
4
30
3
15
4
30
3
15
ns
t15
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
4
21
2
12
4
21
2
12
ns
3
20
3
13
3
20
3
13
ns
2
ns
17
17
0
17
0
0
ns
t16
CSX falling edge to DTACK driven high
t17
DTACK falling edge to D[15:0] valid (read cycle)
t18
CSX high to DTACK high
5
34
3
16
5
34
3
16
ns
t19
CLKO rising edge to DTACK Hi-Z
5
40
1
6
5
40
1
6
ns
0
2
0
1. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 51
6.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328)
TCLKO
t1
t2
CLKO
t3
t4
A[16:1]
t5
t7
t6
CSX
t8
t9
UWE/LWE
(write)
t11
t10
OE
(read)
t13
t12
D[15:0]
(write)
Hi-Z
Hi-Z
t15
t16
t14
D[15:0]
(read)
Hi-Z
VALID
Hi-Z
Figure 6-10: Motorola DragonBall Interface without DTACK# Timing
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 52
Epson Research and Development
Vancouver Design Center
Table 6-13: Motorola DragonBall Interface without DTACK Timing
MC68EZ328
Symbol
Parameter
2.0V
Min
fCLKO
Bus Clock frequency
TCLKO Bus Clock period
MC68VZ328
3.3V
Max
Min
16
2.0V
Max
Min
16
3.3V
Max
Min
20
Unit
Max
33
MHz
1/fCLKO
1/fCLKO
1/fCLKO
1/fCLKO
ns
t1
Clock pulse width high
28.1
28.1
22.5
13.6
ns
t2
Clock pulse width low
28.1
28.1
22.5
13.6
ns
t3
A[16:1] setup 1st CLKO when CSX = 0 and
either UWE/LWE or OE = 0
0
0
0
0
ns
t4
A[16:1] hold from CSX rising edge
0
0
0
0
ns
t5a
CSX asserted for MCLK = BCLK
(CPU wait state register should be programmed
to 4 wait states)
8
8
8
8
TCLKO
t5b
CSX asserted for MCLK = BCLK ÷ 2
(CPU wait state register should be programmed
to 6 wait states)
11
11
11
11
TCLKO
t5c
CSX asserted for MCLK = BCLK ÷ 3
(CPU wait state register should be programmed
to 10 wait states)
—
Note 1
—
Note 1
13
13
TCLKO
t5d
CSX asserted for MCLK = BCLK ÷ 4
(CPU wait state register should be programmed
to 12 wait states)
—
Note 1
—
Note 1
17
17
TCLKO
t6
CSX setup to CLKO rising edge
0
0
0
0
t7
CSX rising edge setup to CLKO rising edge
0
0
0
0
ns
ns
t8
UWE/LWE setup to CLKO rising edge
1
0
1
0
ns
t9
UWE/LWE rising edge to CSX rising edge
0
0
0
0
ns
t10
OE setup to CLKO rising edge
1
1
1
1
ns
t11
OE hold from CSX rising edge
0
0
0
0
ns
t12
D[15:0] setup to 3rd CLKO after CSX, UWE/LWE
asserted (write cycle) (see note 2)
1
0
1
0
ns
t13
CSX rising edge to D[15:0] output Hi-Z (write
cycle)
0
0
0
0
ns
t14
Falling edge of OE to D[15:0] driven (read cycle)
4
t15a
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK
(read cycle)
5.5TCLKO
+4
5.5TCLKO
+ 20
t15b
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
2 (read cycle)
8TCLKO +
19
t15c
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
3 (read cycle)
t15d
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
4 (read cycle)
t16
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
S1D13706
X31B-A-001-09
4
30
15
ns
5.5TCLKO
+4
5.5TCLKO
+ 20
ns
8.5TCLKO
+ 20
8TCLKO +
19
8.5TCLKO
+ 20
ns
9.5TCLKO
+ 17
10.5TCLKO
+ 20
9.5TCLKO
+ 17
10.5TCLKO
+ 20
ns
13TCLKO
+9
14.5TCLKO
+ 20
13TCLKO
+9
14.5TCLKO
+ 20
ns
12
ns
21
3
2
15
12
4
4
30
21
3
2
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 53
1. The MC68EZ328 cannot support the MCLK = BCLK ÷ 3 and MCLK = BCLK ÷ 4 settings without DTACK.
2. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 54
Epson Research and Development
Vancouver Design Center
6.3 LCD Power Sequencing
6.3.1 Passive/TFT Power-On Sequence
GPO*
Power Save
Mode Enable**
(REG[A0h] bit 0)
t1
t2
LCD Signals***
*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-on sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 0.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Figure 6-11: Passive/TFT Power-On Sequence Timing
Table 6-14: Passive/TFT Power-On Sequence Timing
Symbol
Parameter
t1
LCD signals active to LCD bias active
t2
Power Save Mode disabled to LCD signals active
Min
Max
Note 1
Note 1
0
20
Units
ns
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
Note
For HR-TFT Power-On/Off sequence information, see Connecting to the Sharp
HR-TFT Panels, document number X31B-G-011-xx.
For D-TFD Power-On/Off sequence information, see Connecting to the Epson D-TFD
Panels, document number X31B-G-012-xx.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 55
6.3.2 Passive/TFT Power-Off Sequence
t1
GPO*
Power Save
Mode Enable**
(REG[A0h] bit 0)
t2
LCD Signals***
*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Figure 6-12: Passive/TFT Power-Off Sequence Timing
Table 6-15: Passive/TFT Power-Off Sequence Timing
Symbol
Parameter
t1
LCD bias deactivated to LCD signals inactive
t2
Power Save Mode enabled to LCD signals low
Min
Max
Note 1
Note 1
0
20
Units
ns
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 56
Epson Research and Development
Vancouver Design Center
6.4 Display Interface
The timing parameters required to drive a flat panel display are shown below. Timing
details for each supported panel type are provided in the remainder of this section.
HT
HDPS
HPS
HPW
VPS
VDPS
VPW
HDP
VT
VDP
Figure 6-13: Panel Timing Parameters
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 57
Table 6-16: Panel Timing Parameter Definition and Register Summary
Symbol
HT
HDP1
HDPS
HPS
HPW
VT
VDP
VDPS
VPS
VPW
Description
Horizontal Total
Horizontal Display Period1
Derived From
Units
((REG[12h] bits 6-0) + 1) x 8
((REG[14h] bits 6-0) + 1) x 8
For STN panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 22)
Ts
Horizontal Display Period Start Position
For TFT panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 5)
FPLINE Pulse Start Position
(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
FPLINE Pulse Width
(REG[20h] bits 6-0) + 1
Vertical Total
(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1
Vertical Display Period
(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1
Vertical Display Period Start Position
REG[1Fh] bits 1-0, REG[1Eh] bits 7-0
Lines (HT)
FPFRAME Pulse Start Position
REG[27h] bits 1-0, REG[26h] bits 7-0
FPFRAME Pulse Width
(REG[24h] bits 6-0) + 1
1. For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
2. The following formulas must be valid for all panel timings:
HDPS + HDP < HT
VDPS + VDP < VT
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 58
Epson Research and Development
Vancouver Design Center
6.4.1 Generic STN Panel Timing
VT (= 1 Frame)
VPW
FPFRAME
VDP
FPLINE
MOD1(DRDY)
FPDAT[17:0]
HT (= 1 Line)
HPS
HPW
FPLINE
FPSHIFT
1PCLK
MOD2(DRDY)
HDPS
HDP
FPDAT[17:0]
Figure 6-14: Generic STN Panel Timing
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
VT
VPS
VPW
VDPS
VDP
HT
HPS
HPW
HDPS
HDP
Page 59
= Vertical Total
= [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines
= FPFRAME Pulse Start Position
= 0 lines, because (REG[27h] bits 1-0, REG[26h] bits 7-0) = 0
= FPFRAME Pulse Width
= [(REG[24h] bits 2-0) + 1] lines
= Vertical Display Period Start Position
= 0 lines, because (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) = 0
= Vertical Display Period
= [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines
= Horizontal Total
= [((REG[12h] bits 6-0) + 1) x 8] pixels
= FPLINE Pulse Start Position
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
= FPLINE Pulse Width
= [(REG[20h] bits 6-0) + 1] pixels
= Horizontal Display Period Start Position
= 22 pixels, because (REG[17h] bits 1-0, REG[16h] bits 7-0) = 0
= Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
*For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
*HPS must comply with the following formula:
HPS > HDP + 22
HPS + HPW < HT
*Panel Type Bits (REG[10h] bits 1-0) = 00b (STN)
*FPFRAME Pulse Polarity Bit (REG[24h] bit 7) = 1 (active high)
*FPLINE Polarity Bit (REG[20h] bit 7) = 1 (active high)
*MOD1 is the MOD signal when (REG[11h] bits 5-0) = 0 (MOD toggles every FPFRAME)
*MOD2 is the MOD signal when (REG[11h] bits 5-0) = n (MOD toggles every n FPLINE)
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 60
Epson Research and Development
Vancouver Design Center
6.4.2 Single Monochrome 4-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
Invalid
1-1
1-5
1-317
Invalid
FPDAT6
FPDAT5
Invalid
1-2
1-6
1-318
Invalid
Invalid
1-3
1-7
1-319
Invalid
FPDAT4
Invalid
1-4
1-8
1-320
Invalid
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
Figure 6-15: Single Monochrome 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 61
t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
FPDAT[7:4]
t13
1
2
Figure 6-16: Single Monochrome 4-Bit Panel A.C. Timing
Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:4] setup to FPSHIFT falling edge
FPDAT[7:4] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 2
4
2
2
1
2
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 2, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 62
Epson Research and Development
Vancouver Design Center
6.4.3 Single Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
LINE1
Invalid
LINE2
LINE3
LINE4
LINE479 LINE480
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
Invalid
1-1
1-9
1-633
Invalid
FPDAT6
Invalid
1-2
1-10
1-634
Invalid
FPDAT5
FPDAT4
FPDAT3
Invalid
1-3
1-11
1-635
Invalid
Invalid
1-4
1-12
1-636
Invalid
Invalid
1-5
1-13
1-637
Invalid
FPDAT2
Invalid
1-6
1-14
1-638
Invalid
FPDAT1
FPDAT0
Invalid
1-7
1-15
1-639
Invalid
Invalid
1-8
1-16
1-640
Invalid
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 6-17: Single Monochrome 8-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 63
t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
FPDAT[7:0]
t13
1
2
Figure 6-18: Single Monochrome 8-Bit Panel A.C. Timing
Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 4
8
4
4
4
4
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 4, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 64
Epson Research and Development
Vancouver Design Center
6.4.4 Single Color 4-Bit Panel Timing
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
LINE1
Invalid
LINE2
LINE3
LINE4
LINE239 LINE240
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
.5Ts
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
Notes:
FPDAT4
.5Ts
.5Ts
Invalid
1-R1
.5Ts
1-G2
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
HNDP
2.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
1-B3
1-B319
Invalid
Invalid
1-G1
1-B2
1-R4
1-R320
Invalid
Invalid
1-B1
1-R3
1-G4
1-G320
Invalid
Invalid
1-R2
1-G3
1-B4
1-B320
Invalid
- FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-19: Single Color 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 65
t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
FPDAT[7:4]
t13
1
2
Figure 6-20: Single Color 4-Bit Panel A.C. Timing
Table 6-19: Single Color 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:4] setup to FPSHIFT falling edge
FPDAT[7:4] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 0.5
1
0.5
0.5
0.5
0.5
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 1.5), if negative add t3min
= HDPS - (HPS + t4min) + 1, if negative add t3min
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 66
Epson Research and Development
Vancouver Design Center
6.4.5 Single Color 8-Bit Panel Timing (Format 1)
VNDP
VDP
FPFRAME
FPLINE
FPDAT[7:0]
LINE1
Invalid
LINE2
LINE3
LINE4
LINE239
LINE240
Invalid
2Ts
2Ts
LINE1
LINE2
FPLINE
HDP
2Ts
FPSHIFT
2Ts
2Ts
4Ts
2Ts
2Ts
2Ts
4Ts
2Ts
2Ts
4Ts
2Ts
4Ts
2Ts
2Ts
4Ts
2Ts
HNDP
2Ts
2Ts
2Ts
4Ts
2Ts
2Ts
4Ts
2Ts
FPSHIFT2
2Ts
2Ts
4Ts
2Ts
2Ts
2Ts
2Ts
2Ts
FPDAT7
Invalid
1-R1
1-G1
1-G6
1-B6
1-B11
1-R12
1R316
Invalid
FPDAT6
Invalid
1-B1
1-R2
1-R7
1-G7
1-G12
1-B12
1B316
Invalid
FPDAT5
FPDAT4
FPDAT3
Invalid
1-G2
1-B2
1-B7
1-R8
1-R13
1-G13
1G317
Invalid
Invalid
1-R3
1-G3
1-G8
1-B8
1-B13
1-R14
1R318
Invalid
Invalid
1-B3
1-R4
1-R9
1-G9
1-G14
1-B14
1B318
Invalid
FPDAT2
Invalid
1-G4
1-B4
1-B9
1-R10
1-R15
1-G15
1G319
Invalid
FPDAT1
Invalid
1-R5
1-G5
1-G10
1-B10
1-B15
1-R16
1R320
Invalid
FPDAT0
Invalid
1-B5
1-R6
1-R11
1-G11
1-G16
1-B16
1B320
Invalid
Notes:
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FPSHIFT/FPSHIFT2 rising edges
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-21: Single Color 8-Bit Panel Timing (Format 1)
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 67
t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
Data Timing
FPLINE
t6a
t6b
t7a
t8
t9
t14
t11
t10
FPSHIFT
t7b
FPSHIFT2
t12 t13 t12 t13
FPDAT[7:0]
1
2
Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1)
Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol
t1
t2
t3
t4
t6a
t6b
t7a
t7b
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t6amin
t6bmin
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT2 falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPSHIFT2 falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT rising, FPSHIFT2 falling edge
FPSHIFT2, FPSHIFT period
FPSHIFT2, FPSHIFT pulse width low
FPSHIFT2, FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT2, FPSHIFT falling edge
FPDAT[7:0] hold from FPSHIFT2, FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6a + t4
t6b + t4
t14 + 2
4
2
2
1
1
note 8
Typ
Max
6
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - (HDP + HDPS), if negative add t3min
= HPS - (HDP + HDPS) + 2, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 68
Epson Research and Development
Vancouver Design Center
6.4.6 Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
2Ts
FPSHIFT
Ts
Ts
2Ts
2Ts
Ts
Ts
2Ts
HNDP
2Ts
Ts
Ts
Ts
2Ts
Ts
Ts
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
Invalid
1-R1
1-B3
1-G6
Ts
1-G318
Invalid
Invalid
1-G1
1-R4
1-B6
1-B318
Invalid
Invalid
Invalid
1-B1
1-G4
1-R7
1-R319
Invalid
1-R2
1-B4
1-G7
1-G319
Invalid
Invalid
1-G2
1-R5
1-B7
1-B319
Invalid
FPDAT2
Invalid
1-B2
1-G5
1-R8
1-R320
Invalid
FPDAT1
Invalid
1-R3
1-B5
1-G8
1-G320
Invalid
FPDAT0
Invalid
1-G3
1-R6
1-B8
1-B320
Invalid
Notes:
- The duty cycle of FPSHIFT changes in order to process 8 pixels in 3 FPSHIFT rising clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-23: Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 69
t1
Sync Timing
t2
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
FPDAT[7:0]
t13
1
2
Figure 6-24: Single Color 8-Bit Panel A.C. Timing (Format 2)
Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2)
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 2
2
1
1
1
1
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 1, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 70
Epson Research and Development
Vancouver Design Center
6.4.7 Single Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[15:0]
LINE1
Invalid
LINE2
LINE3
LINE4
LINE479
LINE480
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
3Ts
FPSHIFT
2Ts
3Ts
3Ts
2Ts
3Ts
3Ts
3Ts
HNDP
3Ts
3Ts
2Ts
3Ts
3Ts
1-G635
Invalid
1-G12
1-G636
Invalid
1-B7
1-R13
1-R637
Invalid
1-R3
1-G8
1-B13
1-B637
Invalid
1-B3
1-R9
1-G14
1-G638
Invalid
1-G4
1-B9
1-R15
1-R639
Invalid
Invalid
1-R5
1-G10
1-B15
1-B639
Invalid
Invalid
1-B5
1-R11
1-G16
1-G640
Invalid
FPDAT11
FPDAT10
FPDAT9
FPDAT8
Invalid
1-G1
1-B6
1-R12
1-R636
Invalid
Invalid
1-R2
1-G7
1-B12
1-B636
Invalid
Invalid
1-B2
1-R8
1-G13
1-G637
Invalid
Invalid
1-G3
1-B8
1-R14
1-R638
Invalid
FPDAT3
Invalid
1-R4
1-G9
1-B14
1-B638
Invalid
FPDAT2
Invalid
1-B4
1-R10
1-G15
1-G639
Invalid
FPDAT1
Invalid
1-G5
1-B10
1-R16
1-R640
Invalid
FPDAT0
Invalid
1-R6
1-G11
1-B16
1-B640
Invalid
FPDAT15
FPDAT14
FPDAT13
FPDAT12
FPDAT7
FPDAT6
Invalid
1-R1
3Ts
3Ts
2Ts
1-G6
1-B11
Invalid
1-B1
1-R7
Invalid
1-G2
Invalid
Invalid
Invalid
FPDAT5
FPDAT4
3Ts
2Ts
2Ts
3Ts
Notes:
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 3 FPSHIFT rising clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 640x480 panel
Figure 6-25: Single Color 16-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 71
t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t7
t9
t14
t11
t10
FPSHIFT
t12
FPDAT[15:0]
t13
1
2
Figure 6-26: Single Color 16-Bit Panel A.C. Timing
Table 6-22: Single Color 16-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
8.
Ts
t1min
t2min
t3min
t4min
t5min
t6min
t14min
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[15:0] setup to FPSHIFT rising edge
FPDAT[15:0] hold to FPSHIFT rising edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 3
5
2
2
2
2
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= HPS + t4min
= t3min - (HPS + t4min)
= HT
= HPW
= HPS - 1
= HPS - (HDP + HDPS) + 2, if negative add t3min
= HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 72
Epson Research and Development
Vancouver Design Center
6.4.8 Generic TFT Panel Timing
VT (= 1 Frame)
VPS
VPW
FPFRAME
VDP
VDPS
FPLINE
DRDY
FPDAT[17:0]
HT (= 1 Line)
HPS
HPW
FPLINE
FPSHIFT
DRDY
HDPS
FPDAT[17:0]
HDP
invalid
invalid
Figure 6-27: Generic TFT Panel Timing
VT
VPS
VPW
VDPS
VDP
HT
HPS
HPW
HDPS
HDP
= Vertical Total
= FPFRAME Pulse Start Position
= FPFRAME Pulse Width
= Vertical Display Period Start Position
= Vertical Display Period
= Horizontal Total
= FPLINE Pulse Start Position
= FPLINE Pulse Width
= Horizontal Display Period Start Position
= Horizontal Display Period
= [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines
= (REG[27h] bits 1-0, REG[26h] bits 7-0) lines
= [(REG[24h] bits 2-0) + 1] lines
= (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) lines
= [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines
= [((REG[12h] bits 6-0) + 1) x 8] pixels
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
= [(REG[20h] bits 6-0) + 1] pixels
= [(REG[17h] bits 1-0, REG[16h] bits 7-0) + 5] pixels
= [((REG[14h] bits 6-0) + 1) x 8] pixels
*For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
*Panel Type Bits (REG[10h] bits 1-0) = 01 (TFT)
*FPLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)
*FPFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 73
6.4.9 9/12/18-Bit TFT Panel Timing
VNDP2
VDP
VNDP1
FPFRAME
FPLINE
FPDAT[17:0]
LINE240
LINE1
LINE480
DRDY
FPLINE
HDP
HNDP1
HNDP2
FPSHIFT
DRDY
FPDAT[17:0]
invalid
1-1
1-2
1-320
invalid
Note: DRDY is used to indicate the first pixel
Example Timing for 18-bit 320x240 panel
Figure 6-28: 18-Bit TFT Panel Timing
VDP
VNDP
VNDP1
VNDP2
HDP
HNDP
HNDP1
HNDP2
= Vertical Display Period
= VDP Lines
= Vertical Non-Display Period
= VNDP1 + VNDP2
= VT - VDP Lines
= Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
= Vertical Non-Display Period 2
= VDPS - VPS Lines
= Horizontal Display Period
= HDP Ts
= Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
= Horizontal Non-Display Period 1
= HDPS - HPS Ts
= Horizontal Non-Display Period 2
= HPS - (HDP + HDPS) Ts
Hardware Functional Specification
Issue Date: 2004/02/09
if negative add VT
if negative add HT
if negative add HT
S1D13706
X31B-A-001-09
Page 74
Epson Research and Development
Vancouver Design Center
t1
t2
FPFRAME
t3
FPLINE
t4
FPLINE
t5
t8
t7
t6
DRDY
t9
t12
t13
t10 t11
t14
FPSHIFT
t15 t16
FPDAT[17:0]
invalid
1
2
319
320
invalid
Note: DRDY is used to indicate the first pixel
Figure 6-29: TFT A.C. Timing
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 75
Table 6-23: TFT A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
1. Ts
2. t6min
3. t8min
Parameter
FPFRAME cycle time
FPFRAME pulse width low
FPFRAME falling edge to FPLINE falling edge phase difference
FPLINE cycle time
FPLINE pulse width low
FPLINE Falling edge to DRDY active
DRDY pulse width
DRDY falling edge to FPLINE falling edge
FPSHIFT period
FPSHIFT pulse width high
FPSHIFT pulse width low
FPLINE setup to FPSHIFT falling edge
DRDY to FPSHIFT falling edge setup time
DRDY hold from FPSHIFT falling edge
Data setup to FPSHIFT falling edge
Data hold from FPSHIFT falling edge
= pixel clock period
= HDPS - HPS
= HPS - (HDP + HDPS)
Hardware Functional Specification
Issue Date: 2004/02/09
Min
VT
VPW
HPS
HT
HPW
note 2
HDP
note 3
1
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Typ
Max
250
Units
Lines
Lines
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
if negative add HT
if negative add HT
S1D13706
X31B-A-001-09
Page 76
Epson Research and Development
Vancouver Design Center
6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx)
FPFRAME
(SPS)
t1
FPLINE
(LP)
t2
t3
FPLINE
(LP)
t4
FPSHIFT
(CLK)
t5 t6
D1
FPDAT[17:0]
t7
t9
D2
D160
D3
t8
t10
GPIO3
(SPL)
t11
GPIO1
(CLS)
t12
GPIO0
(PS)
t13
GPIO2
(REV)
Figure 6-30: 160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 77
Table 6-24: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
1.
2.
3.
4.
5.
6.
Ts
t1typ
t2typ
t3typ
t7typ
t8typ
Parameter
FPLINE start position
Horizontal total period
FPLINE width
FPSHIFT period
Data setup to FPSHIFT rising edge
Data hold from FPSHIFT rising edge
Horizontal display start position
Horizontal display period
FPLINE rising edge to GPIO3 rising edge
GPIO3 pulse width
GPIO1(GPIO0) pulse width
GPIO1 rising edge (GPIO0 falling edge) to FPLINE rise edge
GPIO2 toggle edge to FPLINE rise edge
Min
Typ
13
180
Max
220
2
1
0.5
0.5
5
160
4
1
136
4
10
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= (REG[22h] bits 7-0) + 1
= ((REG[12h] bits 6-0) + 1) x 8
= (REG[20h] bits 6-0) + 1
= ((REG[16h] bits 7-0) + 5) - ((REG[22h] bits 7-0) + 1)
= ((REG[14h] bits 6-0) + 1) x 8
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 78
Epson Research and Development
Vancouver Design Center
t1
t2
t3
FPDAT[17:0]
LINE1
LINE2
LINE160
t4
FPFRAME
(SPS)
t5
t6
GPIO1
(CLS)
t8
t7
GPIO0
(PS)
t9
FPLINE
(LP)
FPSHIFT
(CLK)
t10
GPIO1
(CLS)
t11
t12
t13
t14
GPIO0
(PS)
Figure 6-31: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 79
Table 6-25: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1. Ts
Parameter
Vertical total period
Vertical display start position
Vertical display period
Vertical sync pulse width
FPFRAME falling edge to GPIO1 alternate timing start
GPIO1 alternate timing period
FPFRAME falling edge to GPIO0 alternate timing start
GPIO0 alternate timing period
GPIO1 first pulse rising edge to FPLINE rising edge
GPIO1 first pulse width
GPIO1 first pulse falling edge to second pulse rising edge
GPIO1 second pulse width
GPIO0 falling edge to FPLINE rising edge
GPIO0 low pulse width
Min
203
Typ
40
160
2
5
4
40
162
4
48
40
48
4
24
Max
264
Units
Lines
Lines
Lines
Lines
Lines
Lines
Lines
Lines
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
= pixel clock period
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 80
Epson Research and Development
Vancouver Design Center
6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01)
FPFRAME
(SPS)
t1
FPLINE
(LP)
t2
t3
FPLINE
(LP)
t4
FPSHIFT
(CLK)
t5 t6
D1
FPDAT[17:0]
D320
D3
t8
t7
t9
D2
t10
GPIO3
(SPL)
t11
GPIO1
(CLS)
t12
GPIO0
(PS)
t13
GPIO2
(REV)
Figure 6-32: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 81
Table 6-26: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing
Symbol
Parameter
FPLINE start position
Horizontal total period
FPLINE width
FPSHIFT period
Data setup to FPSHIFT rising edge
Data hold from FPSHIFT rising edge
Horizontal display start position
Horizontal display period
FPLINE rising edge to GPIO3 rising edge
GPIO3 pulse width
GPIO1(GPIO0) pulse width
GPIO1 rising edge (GPIO0 falling edge) to FPLINE rise edge
GPIO2 toggle edge to FPLINE rise edge
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
1.
2.
3.
4.
5.
6.
Ts
t1typ
t2typ
t3typ
t7typ
t8typ
Min
Typ
14
400
Max
440
1
1
0.5
0.5
60
320
59
1
353
5
11
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= (REG[22h] bits 7-0) + 1
= ((REG[12h] bits 6-0) + 1) x 8
= (REG[20h] bits 6-0) + 1
= ((REG[16h] bits 7-0) + 5) - ((REG[22h] bits 7-0) + 1)
= ((REG[14h] bits 6-0) + 1) x 8
t1
t2
FPDAT[17:0]
t3
LINE1
LINE2
LINE240
t4
FPFRAME
(SPS)
Figure 6-33: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
Table 6-27: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
Symbol
t1
t2
t3
t4
Parameter
Vertical total period
Vertical display start position
Vertical display period
Vertical sync pulse width
Hardware Functional Specification
Issue Date: 2004/02/09
Min
245
Typ
4
240
2
Max
330
Units
Lines
Lines
Lines
Lines
S1D13706
X31B-A-001-09
Page 82
Epson Research and Development
Vancouver Design Center
6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR)
t1
FPLINE
(LP)
t3
t2
FPSHIFT
(XSCL)
t4
t6
t5
FPDAT[17:0]
1
2
3
4
160
(R,G,B)
t7
t8
t9
t9
t10
t10
GPIO4
(RES)
t11
t12
t11
t12
GPIO1
(YSCL)
t13
GPIO0
(XINH)
t14
t15
GPIO6
(YSCLD)
GPIO2
(FR)
t16
GPIO3
(FRS)
t17
t17
GPIO5
(DD_P1)
Figure 6-34: 160x240 Epson D-TFD Panel Horizontal Timing
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 83
Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
1. Ts
Parameter
FPLINE pulse width
FPLINE falling edge to FPSHIFT start position
FPSHIFT active period
FPSHIFT start to first data
Horizontal display period
Last data to FPSHIFT inactive
FPLINE falling edge to GPIO4 first pulse falling edge
Horizontal total period
GPIO4 first pulse falling edge to second pulse falling edge
GPIO4 pulse width
GPIO1 pulse width
GPIO1 low period
GPIO0 pulse width
GPIO6 low pulse width
GPIO6 rising edge to GPIO0 falling edge
GPIO2 toggle to GPIO3 toggle
GPIO5 low pulse width
Min
Typ
9
8.5
167
4
160
3
1
400
200
11
100
100)
200
90
10
1
7
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 84
Epson Research and Development
Vancouver Design Center
t1
GPIO4
(RES)
t2
DRDY
(GCP)
GCP Data Register
(REG[2Ch])
1
1
0
1
0
0
1
bit0
bit7
Index 00h
1
0
1
bit7
bit7
Index 01h
Index 00h
Figure 6-35: 160x240 Epson D-TFD Panel GCP Horizontal Timing
Table 6-29: 160x240 Epson D-TFD Panel GCP Horizontal Timing
Symbol
Parameter
Half of the horizontal total period
GCP clock period
t1
t2
1. Ts
Min
Typ
200
1
Max
Units
Ts (note 1)
Ts
= pixel clock period
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 85
Vertical Total = 250HT
t1
FPFRAME
(DY)
t2
GPIO1
(YSCL)
GPIO0
(XINH)
t3
FPDAT[17:0]
(R,G,B)
line1
line2
GPIO2 (FR)
(odd frame)
GPIO2 (FR)
(even frame)
Figure 6-36: 160x240 Epson D-TFD Panel Vertical Timing
Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing
Symbol
t1
t2
t3
1. Ts
Parameter
FPFRAME pulse width
Horizontal total period
Vertical display start
Min
Typ
200
400
400
Max
Units
Ts (note 1)
Ts
Ts
= pixel clock period
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 86
Epson Research and Development
Vancouver Design Center
6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR)
t1
FPLINE
(LP)
t3
t2
FPSHIFT
(XSCL)
FPDAT[17:0]
(R,G,B)
t6
t5
t4
1
2
3
4
320
t8
t7
t9
t9
t10
t10
GPIO4
(RES)
t11
t12
t11
t12
GPIO1
(YSCL)
t13
GPIO0
(XINH)
t14
t15
GPIO6
(YSCLD)
GPIO2
(FR)
t16
GPIO3
(FRS)
t17
t17
GPIO5
(DD_P1)
Figure 6-37: 320x240 Epson D-TFD Panel Horizontal Timing
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 87
Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
1. Ts
Parameter
FPLINE pulse width
FPLINE falling edge to FPSHIFT start position
FPSHIFT active period
FPSHIFT start to first data
Horizontal display period
Last data to FPSHIFT inactive
FPLINE falling edge to GPIO4 first pulse falling edge
Horizontal total period
GPIO4 first pulse falling edge to second pulse falling edge
GPIO4 pulse width
GPIO1 pulse width
GPIO1 low period
GPIO0 pulse width
GPIO6 low pulse width
GPIO6 rising edge to GPIO0 falling edge
GPIO2 toggle to GPIO3 toggle
GPIO5 low pulse width
Min
Typ
9
8.5
331
6
320
5
1
400
200
11
100
100
200
90
10
1
7
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 88
Epson Research and Development
Vancouver Design Center
t1
GPIO4
(RES)
t2
DRDY
(GCP)
GCP Data Register
(REG[2Ch])
1
1
0
1
0
0
1
bit0
bit7
Index 00h
1
0
1
bit7
bit7
Index 00h
Index 01h
Figure 6-38: 320x240 Epson D-TFD Panel GCP Horizontal Timing
Table 6-32: 320x240 Epson D-TFD Panel GCP Horizontal Timing
Symbol
Parameter
Half of the horizontal total period
GCP clock period
t1
t2
1. Ts
Min
Typ
200
1
Max
Units
Ts (note 1)
Ts
= pixel clock period
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 89
Vertical Total = 250HT
t1
FPFRAME
(DY)
t2
GPIO1
(YSCL)
GPIO0
(XINH)
t3
FPDAT[17:0]
(R,G,B)
line1
line2
GPIO2 (FR)
(odd frame)
GPIO2 (FR)
(even frame)
Figure 6-39: 320x240 Epson D-TFD Panel Vertical Timing
Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing
Symbol
t1
t2
t3
1. Ts
Parameter
FPFRAME pulse width
Horizontal total period
Vertical display start
Min
Typ
200
400
400
Max
Units
Ts (note 1)
Ts
Ts
= pixel clock period
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 90
Epson Research and Development
Vancouver Design Center
7 Clocks
7.1 Clock Descriptions
7.1.1 BCLK
BCLK is an internal clock derived from CLKI. BCLK can be a divided version (÷1, ÷2, ÷3,
÷4) of CLKI. CLKI is typically derived from the host CPU bus clock.
The source clock options for BCLK may be selected as in the following table.
Table 7-1: BCLK Clock Selection
Source Clock Options
BCLK Selection
CLKI
CNF[7:6] = 00
CLKI ÷2
CNF[7:6] = 01
CLKI ÷3
CNF[7:6] = 10
CLKI ÷4
CNF[7:6] = 11
Note
For synchronous bus interfaces, it is recommended that BCLK be set the same as the
CPU bus clock (not a divided version of CLKI) e.g. SH-3, SH-4.
Note
The CLKI ÷ 3 and CLKI ÷ 4 options may not work properly with bus interfaces with
short back-to-back cycle timing.
7.1.2 MCLK
MCLK provides the internal clock required to access the embedded SRAM. The S1D13706
is designed with efficient power saving control for clocks (clocks are turned off when not
used); reducing the frequency of MCLK does not necessarily save more power.
Furthermore, reducing the MCLK frequency relative to the BCLK frequency increases the
CPU cycle latency and so reduces screen update performance. For a balance of power
saving and performance, the MCLK should be configured to have a high enough frequency
setting to provide sufficient screen refresh as well as acceptable CPU cycle latency.
The source clock options for MCLK may be selected as in the following table.
Table 7-2: MCLK Clock Selection
S1D13706
X31B-A-001-09
Source Clock Options
MCLK Selection
BCLK
REG[04h] bit 5,4 = 00
BCLK ÷2
REG[04h] bit 5,4 = 01
BCLK ÷3
REG[04h] bit 5,4 = 10
BCLK ÷4
REG[04h] bit 5,4 = 11
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 91
7.1.3 PCLK
PCLK is the internal clock used to control the LCD panel. PCLK should be chosen to match
the optimum frame rate of the LCD panel. See Section 9, “Frame Rate Calculation” on page
130 for details on the relationship between PCLK and frame rate.
Some flexibility is possible in the selection of PCLK. Firstly, LCD panels typically have a
range of permissible frame rates. Secondly, it may be possible to choose a higher PCLK
frequency and tailor the horizontal and vertical non-display periods to lower the frame-rate
to its optimal value.
The source clock options for PCLK may be selected as in the following table.
Table 7-3: PCLK Clock Selection
Hardware Functional Specification
Issue Date: 2004/02/09
Source Clock Options
PCLK Selection
MCLK
REG[05h] = 00h
MCLK ÷2
REG[05h] = 10h
MCLK ÷3
REG[05h] = 20h
MCLK ÷4
REG[05h] = 30h
MCLK ÷8
REG[05h] = 40h
BCLK
REG[05h] = 01h
BCLK ÷2
REG[05h] = 11h
BCLK ÷3
REG[05h] = 21h
BCLK ÷4
REG[05h] = 31h
BCLK ÷8
REG[05h] = 41h
CLKI
REG[05h] = 02h
CLKI ÷2
REG[05h] = 12h
CLKI ÷3
REG[05h] = 22h
CLKI ÷4
REG[05h] = 32h
CLKI ÷8
REG[05h] = 42h
CLKI2
REG[05h] = 03h
CLKI2 ÷2
REG[05h] = 13h
CLKI2 ÷3
REG[05h] = 23h
CLKI2 ÷4
REG[05h] = 33h
CLKI2 ÷8
REG[05h] = 43h
S1D13706
X31B-A-001-09
Page 92
Epson Research and Development
Vancouver Design Center
There is a relationship between the frequency of MCLK and PCLK that must be
maintained.
Table 7-4: Relationship between MCLK and PCLK
SwivelView Orientation
Color Depth (bpp)
MCLK to PCLK Relationship
16
fMCLK ≥ fPCLK
8
fMCLK ≥ fPCLK ÷ 2
4
fMCLK ≥ fPCLK ÷ 4
2
fMCLK ≥ fPCLK ÷ 8
1
fMCLK ≥ fPCLK ÷16
16/8/4/2/1
fMCLK ≥ 1.25fPCLK
SwivelView 0° and 180°
SwivelView 90° and 270°
7.1.4 PWMCLK
PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel.
The source clock options for PWMCLK may be selected as in the following table.
Table 7-5: PWMCLK Clock Selection
Source Clock Options
PWMCLK Selection
CLKI
REG[B1h] bit 0 = 0
CLKI2
REG[B1h] bit 0 = 1
For further information on controlling PWMCLK, see Section 8.3.9, “Pulse Width
Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers” on
page 126.
Note
The S1D13706 provides Pulse Width Modulation output on the pin PWMOUT.
PWMOUT can be used to control LCD panels which support PWM control of the backlight inverter.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 93
7.2 Clock Selection
The following diagram provides a logical representation of the S1D13706 internal clocks.
CLKI
00
÷2
01
÷3
10
÷4
11
BCLK
CNF[7:6]1
REG[04h] bits 5,4
00
÷2
01
÷3
10
÷4
11
MCLK
00
01
000
10
CLKI2
11
REG[05h] bits 1,0
0
÷2
001
÷3
010
÷4
011
÷8
1xx
PCLK
REG[05h] bits 6-4
PWMCLK
1
REG[B1h] bit 0
Figure 7-1: Clock Selection
Note
1
Hardware Functional Specification
Issue Date: 2004/02/09
CNF[7:6] must be set at RESET#.
S1D13706
X31B-A-001-09
Page 94
Epson Research and Development
Vancouver Design Center
7.3 Clocks versus Functions
Table 7-6: “S1D13706 Internal Clock Requirements”, lists the internal clocks required for
the following S1D13706 functions.
Table 7-6: S1D13706 Internal Clock Requirements
Function
Bus Clock
(BCLK)
Memory Clock
(MCLK)
Pixel Clock
(PCLK)
PWM Clock
(PWMCLK)
Register Read/Write
Required
Not Required
Not Required
Not Required1
Memory Read/Write
Required
Required
Not Required
Not Required1
Look-Up Table Register
Read/Write
Required
Required
Not Required
Not Required1
Software Power Save
Required
Not Required
Not Required
Not Required1
LCD Output
Required
Required
Required
Not Required1
Note
1
S1D13706
X31B-A-001-09
PWMCLK is an optional clock (see Section 7.1.4, “PWMCLK” on page 92).
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 95
8 Registers
This section discusses how and where to access the S1D13706 registers. It also provides
detailed information about the layout and usage of each register.
8.1 Register Mapping
The S1D13706 registers are memory-mapped. When the system decodes the input pins as
CS# = 0 and M/R# = 0, the registers may be accessed. The register space is decoded by
A[16:0].
8.2 Register Set
The S1D13706 register set is as follows.
Table 8-1: S1D13706 Register Set
Register
Pg
Register
Pg
REG[01h] Display Buffer Size Register
97
Read-Only Configuration Registers
REG[00h] Revision Code Register
96
REG[02h] Configuration Readback Register
97
Clock Configuration Registers
REG[04h] Memory Clock Configuration Register
97
REG[05h] Pixel Clock Configuration Register
98
Look-Up Table Registers
REG[08h] Look-Up Table Blue Write Data Register
99
REG[09h] Look-Up Table Green Write Data Register
REG[0Ah] Look-Up Table Red Write Data Register
99
REG[0Bh] Look-Up Table Write Address Register
99
100
REG[0Ch] Look-Up Table Blue Read Data Register
100
REG[0Dh] Look-Up Table Green Read Data Register
100
REG[0Eh] Look-Up Table Red Read Data Register
101
REG[0Fh] Look-Up Table Read Address Register
101
Panel Configuration Registers
REG[10h] Panel Type Register
101
REG[11h] MOD Rate Register
103
REG[12h] Horizontal Total Register
103
REG[14h] Horizontal Display Period Register
103
REG[16h] Horizontal Display Period Start Position Register 0
104
REG[17h] Horizontal Display Period Start Position Register 1
104
REG[18h] Vertical Total Register 0
105
REG[19h] Vertical Total Register 1
105
REG[1Ch] Vertical Display Period Register 0
105
REG[1Dh] Vertical Display Period Register 1
105
REG[1Eh] Vertical Display Period Start Position Register 0
106
REG[1Fh] Vertical Display Period Start Position Register 1
106
REG[20h] FPLINE Pulse Width Register
106
REG[22h] FPLINE Pulse Start Position Register 0
107
REG[23h] FPLINE Pulse Start Position Register 1
107
REG[24h] FPFRAME Pulse Width Register
107
REG[26h] FPFRAME Pulse Start Position Register 0
108
REG[27h] FPFRAME Pulse Start Position Register 1
108
108
REG[2Ch] D-TFD GCP Data Register
108
REG[28h] D-TFD GCP Index Register
Display Mode Registers
REG[70h] Display Mode Register
109
REG[71h] Special Effects Register
111
REG[74h] Main Window Display Start Address Register 0
113
REG[75h] Main Window Display Start Address Register 1
113
REG[76h] Main Window Display Start Address Register 2
113
REG[78h] Main Window Line Address Offset Register 0
114
REG[79h] Main Window Line Address Offset Register 1
114
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 96
Epson Research and Development
Vancouver Design Center
Table 8-1: S1D13706 Register Set
Register
Pg
Register
Pg
+
Picture-in-Picture Plus (PIP ) Registers
Window Display Start Address Register 0
115
REG[7Dh] PIP+ Window Display Start Address Register 1
115
REG[7Eh] PIP Window Display Start Address Register 2
115
REG[80h] PIP+ Window Line Address Offset Register 0
115
REG[7Ch]
PIP+
+
+
+
REG[81h] PIP Window Line Address Offset Register 1
115
REG[84h] PIP Window X Start Position Register 0
116
REG[85h] PIP+ Window X Start Position Register 1
116
REG[88h] PIP+ Window Y Start Position Register 0
117
+
+
REG[89h] PIP Window Y Start Position Register 1
117
REG[8Ch] PIP Window X End Position Register 0
118
REG[8Dh] PIP+ Window X End Position Register 1
118
REG[90h] PIP+ Window Y End Position Register 0
119
REG[91h]
PIP+
Window Y End Position Register 1
119
Miscellaneous Registers
REG[A0h] Power Save Configuration Register
120
REG[A1h] Reserved
120
REG[A2h] Reserved
121
REG[A3h] Reserved
121
REG[A4h] Scratch Pad Register 0
121
REG[A5h] Scratch Pad Register 1
121
General Purpose IO Pins Registers
REG[A8h] General Purpose IO Pins Configuration Register 0
122
REG[ACh] General Purpose IO Pins Status/Control Register 0 123
REG[A9h] General Purpose IO Pins Configuration Register 1
122
REG[ADh] General Purpose IO Pins Status/Control Register 1 125
PWM Clock and CV Pulse Configuration Registers
REG[B0h] PWM Clock / CV Pulse Control Register
126
REG[B1h] PWM Clock / CV Pulse Configuration Register
128
REG[B2h] CV Pulse Burst Length Register
129
REG[B3h] PWMOUT Duty Cycle Register
129
8.3 Register Descriptions
Unless specified otherwise, all register bits are set to 0 during power-on.
8.3.1 Read-Only Configuration Registers
Revision Code Register
REG[00h]
Read Only
Product Code Bits 5-0
7
6
5
4
Revision Code Bits 1-0
3
2
1
0
Note
The S1D13706 returns a value of 28h.
bits 7-2
Product Code
These are read-only bits that indicates the product code. The product code is 001010.
bits 1-0
Revision Code
These are read-only bits that indicates the revision code. The revision code is 00.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 97
Display Buffer Size Register
REG[01h]
Read Only
Display Buffer Size Bits 7-0
7
6
bits 7-0
5
4
3
2
1
0
Display Buffer Size Bits [7:0]
This is a read-only register that indicates the size of the SRAM display buffer measured in
4K byte increments. The S1D13706 display buffer is 80K bytes and therefore this register
returns a value of 20 (14h).
Value of this register = display buffer size ÷ 4K bytes
= 80K bytes ÷ 4K bytes
= 20 (14h)
Configuration Readback Register
REG[02h]
CNF7 Status
CNF6 Status CNF5 Status
7
6
bits 7-0
Read Only
CNF4 Status
5
4
CNF3 Status
3
CNF2 Status
CNF1 Status
2
CNF0 Status
1
0
CNF[7:0] Status
These read-only status bits return the status of the configuration pins CNF[7:0]. CNF[7:0]
are latched at the rising edge of RESET#.
8.3.2 Clock Configuration Registers
Memory Clock Configuration Register
REG[04h]
n/a
7
bits 5-4
Read/Write
MCLK Divide Select Bits 1-0
6
5
4
n/a
3
Reserved
2
1
0
MCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the
Bus Clock (BCLK).
Table 8-2: MCLK Divide Selection
bit 0
MCLK Divide Select Bits
BCLK to MCLK Frequency Ratio
00
1:1
01
2:1
10
3:1
11
4:1
Reserved.
This bit must remain at 0.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 98
Epson Research and Development
Vancouver Design Center
Pixel Clock Configuration Register
REG[05h]
n/a
7
bits 6-4
Read/Write
PCLK Divide Select Bits 2-0
6
5
n/a
4
3
PCLK Source Select Bits 1-0
2
1
0
PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel
Clock Source.
Table 8-3: PCLK Divide Selection
bits 1-0
PCLK Divide Select Bits
PCLK Source to PCLK Frequency Ratio
000
1:1
001
2:1
010
3:1
011
4:1
1XX
8:1
PCLK Source Select Bits [1:0]
These bits determine the source of the Pixel Clock (PCLK).
Table 8-4: PCLK Source Selection
S1D13706
X31B-A-001-09
PCLK Source Select Bits
PCLK Source
00
MCLK
01
BCLK
10
CLKI
11
CLKI2
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 99
8.3.3 Look-Up Table Registers
Note
The S1D13706 has three 256-position, 6-bit wide LUTs, one for each of red, green, and
blue (see Section 11, “Look-Up Table Architecture” on page 132).
Look-Up Table Blue Write Data Register
REG[08h]
Write Only
LUT Blue Write Data Bits 5-0
7
6
bits 7-2
5
4
n/a
3
2
1
0
LUT Blue Write Data Bits [5:0]
This register contains the data to be written to the blue component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written to.
Look-Up Table Green Write Data Register
REG[09h]
Write Only
LUT Green Write Data Bits 5-0
7
6
bits 7-2
5
4
n/a
3
2
1
0
LUT Green Write Data Bits [5:0]
This register contains the data to be written to the green component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written to.
Look-Up Table Red Write Data Register
REG[0Ah]
Write Only
LUT Red Write Data Bits 5-0
7
bits 7-2
6
5
4
n/a
3
2
1
0
LUT Red Write Data Bits [5:0]
This register contains the data to be written to the red component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written to.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 100
Epson Research and Development
Vancouver Design Center
Look-Up Table Write Address Register
REG[0Bh]
Write Only
LUT Write Address Bits 7-0
7
6
bits 7-0
5
4
3
2
1
0
LUT Write Address Bits [7:0]
This register forms a pointer into the Look-Up Table (LUT) which is used to write LUT
blue, green, and red data stored in REG[08h], REG[09h], and REG[0Ah]. The data is
updated to the LUT only with the completion of a write to this register. This is a writeonly register and returns 00h if read.
Note
When a value is written to the LUT Write Address register, the same value is automatically written to the LUT Read Address register (REG[0Fh].
Look-Up Table Blue Read Data Register
REG[0Ch]
Read Only
LUT Blue Read Data Bits 5-0
7
6
bits 7-2
5
4
n/a
3
2
1
0
LUT Blue Read Data Bits [5:0]
This register contains the data from the blue component of the Look-Up Table. The LUT
position is controlled by the LUT Read Address Register (REG[0Fh]). This is a read-only
register.
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written to.
Look-Up Table Green Read Data Register
REG[0Dh]
Read Only
LUT Green Read Data Bits 5-0
7
bits 7-2
6
5
4
n/a
3
2
1
0
LUT Green Read Data Bits [5:0]
This register contains the data from the green component of the Look-Up Table. The LUT
position is controlled by the LUT Read Address Register (REG[0Fh]). This is a read-only
register.
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written to.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 101
Look-Up Table Red Read Data Register
REG[0Eh]
Read Only
LUT Red Read Data Bits 5-0
7
6
bits 7-2
5
4
n/a
3
2
1
0
LUT Red Read Data Bits [5:0]
This register contains the data from the red component of the Look-Up Table. The LUT
position is controlled by the LUT Read Address Register (REG[0Fh]). This is a read-only
register.
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written to.
Look-Up Table Read Address Register
REG[0Fh]
Write Only
LUT Read Address Bits 7-0
7
6
bits 7-0
5
4
3
2
1
0
LUT Read Address Bits [7:0]
This register forms a pointer into the Look-Up Table (LUT) which is used to read LUT
blue, green, and red data. Blue data is read from REG[0Ch], green data from REG[0Dh],
and red data from REG[0Eh]. This is a write-only register and returns 00h if read.
Note
If a write to the LUT Write Address register (REG[0Bh]) is made, the LUT Read Address register is automatically updated with the same value.
8.3.4 Panel Configuration Registers
Panel Type Register
REG[10h]
Read/Write
Panel Data
Format Select
Color/Mono.
Panel Select
7
6
Panel Data Width Bits 1-0
5
4
Active Panel
Resolution
Select
n/a
3
2
Panel Type Bits 1-0
1
0
bit 7
Panel Data Format Select
When this bit = 0, 8-bit single color passive LCD panel data format 1 is selected. For AC
timing see Section 6.4.5, “Single Color 8-Bit Panel Timing (Format 1)” on page 66.
When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. For AC
timing see Section 6.4.6, “Single Color 8-Bit Panel Timing (Format 2)” on page 68.
bit 6
Color/Mono Panel Select
When this bit = 0, a monochrome LCD panel is selected.
When this bit = 1, a color LCD panel is selected.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 102
bits 5-4
Epson Research and Development
Vancouver Design Center
Panel Data Width Bits [1:0]
These bits select the data width size of the LCD panel.
Table 8-5: Panel Data Width Selection
bit 3
Panel Data Width Bits [1:0]
Passive Panel Data Width
Size
Active Panel Data Width Size
00
4-bit
9-bit
01
8-bit
12-bit
10
16-bit
18-bit
11
Reserved
Reserved
Active Panel Resolution Select
This bit selects one of two panel resolutions when an HR-TFT or D-TFD panel is selected.
This bit has no effect for other panel types.
Table 8-6: Active Panel Resolution Selection
Active Panel Resolution
Select Bit
HR-TFT Resolution
D-TFD Resolution
0
160x160
160x240
1
320x240
320x240
Note
This bit sets some internal non-configurable timing values for the selected panel. However, all panel configuration registers (REG[12h] - REG[27h]) still require programming with the appropriate values for the selected panel. For panel AC timing, see
Section 6.4, “Display Interface” on page 56.
bits 1-0
Panel Type Bits[1:0]
These bits select the panel type.
Table 8-7: LCD Panel Type Selection
S1D13706
X31B-A-001-09
REG[10h] Bits[1:0]
Panel Type
00
STN
01
TFT
10
HR-TFT
11
D-TFD
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 103
MOD Rate Register
REG[11h]
Read/Write
n/a
7
MOD Rate Bits 5-0
6
bits 5-0
5
4
3
2
1
MOD Rate Bits [5:0]
These bits are for passive LCD panels only.
When these bits are all 0, the MOD output signal (DRDY) toggles every FPFRAME.
For a non-zero value n, the MOD output signal (DRDY) toggles every n FPLINE.
Horizontal Total Register
REG[12h]
Read/Write
n/a
7
0
Horizontal Total Bits 6-0
6
bits 6-0
5
4
3
2
1
0
Horizontal Total Bits [6:0]
These bits specify the LCD panel Horizontal Total period, in 8 pixel resolution. The Horizontal Total is the sum of the Horizontal Display period and the Horizontal Non-Display
period. Since the maximum Horizontal Total is 1024 pixels, the maximum panel resolution supported is 800x600.
Horizontal Total in number of pixels = ((REG[12h] bits 6:0) + 1) × 8
Note
1
This register must be programmed such that the following formulas are valid.
HDPS + HDP < HT
2
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface” on page 56.
Horizontal Display Period Register
REG[14h]
n/a
7
bits 6-0
Read/Write
Horizontal Display Period Bits 6-0
6
5
4
3
2
1
0
Horizontal Display Period Bits [6:0]
These bits specify the LCD panel Horizontal Display Period (HDP), in 8 pixel resolution.
The Horizontal Display Period should be less than the Horizontal Total to allow for a sufficient Horizontal Non-Display Period.
Horizontal Display Period in number of pixels = ((REG[14h] bits 6:0) + 1) × 8
Note
For passive panels, HDP must be a minimum of 32 pixels and can be increased by multiples of 16. For TFT panels, HDP must be a minimum of 16 pixels and can be increased
by multiples of 8.
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface”
on page 56.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 104
Epson Research and Development
Vancouver Design Center
Horizontal Display Period Start Position Register 0
REG[16h]
Read/Write
Horizontal Display Period Start Position Bits 7-0
7
6
5
4
3
2
1
Horizontal Display Period Start Position Register 1
REG[17h]
Read/Write
Horizontal Display Period
Start Position Bits 9-8
n/a
7
bits 9-0
6
5
0
4
3
2
1
0
Horizontal Display Period Start Position Bits [9:0]
These bits specify a value used in the calculation of the Horizontal Display Period Start
Position (in 1 pixel resolution) for TFT, HR-TFT and D-TFD panels.
For passive LCD panels these bits must be set to 00h which will result in HDPS = 22.
HDPS = (REG[17h] bits 1-0, REG[16h] bits 7-0) + 22
For TFT/HR-TFT/D-TFD panels, HDPS is calculated using the following formula.
HDPS = (REG[17h] bits 1-0, REG[16h] bits 7-0) + 5
For further information on calculating the HDPS, see the specific panel AC Timing in
Section 6.4, “Display Interface” on page 56.
Note
This register must be programmed such that the following formula is valid.
HDPS + HDP < HT
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 105
Vertical Total Register 0
REG[18h]
Read/Write
Vertical Total Bits 7-0
7
6
5
4
3
2
1
Vertical Total Register 1
REG[19h]
Read/Write
n/a
7
6
bits 9-0
0
5
Vertical Total Bits 9-8
4
3
2
1
0
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The
maximum Vertical Total is 1024 lines.
Vertical Total in number of lines = (REG[18h] bits 7:0, REG[19h] bits 1:0) + 1
Note
1
This register must be programmed such that the following formula is valid.
VDPS + VDP < VT
2 For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface” on page 56.
Vertical Display Period Register 0
REG[1Ch]
Read/Write
Vertical Display Period Bits 7-0
7
6
5
4
3
2
1
Vertical Display Period Register 1
REG[1Dh]
Read/Write
Vertical Display Period
Bits 9-8
n/a
7
bits 9-0
6
5
0
4
3
2
1
0
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The Vertical
Display period should be less than the Vertical Total to allow for a sufficient Vertical
Non-Display period.
Vertical Display Period in number of lines = (REG[1Ch] bits 7:0, REG[1Dh] bits 1:0) + 1
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface” on page 56.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 106
Epson Research and Development
Vancouver Design Center
Vertical Display Period Start Position Register 0
REG[1Eh]
Read/Write
Vertical Display Period Start Position Bits 7-0
7
6
5
4
3
2
1
Vertical Display Period Start Position Register 1
REG[1Fh]
Read/Write
Vertical Display Period Start
Position Bits 9-8
n/a
7
6
bits 9-0
5
0
4
3
2
1
0
Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position for panels in 1 line resolution.
For passive LCD panels these bits must be set to 00h.
For TFT panels, VDPS is calculated using the following formula.
VDPS = (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0)
Note
1
This register must be programmed such that the following formula is valid.
VDPS + VDP < VT
2
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface” on page 56.
FPLINE Pulse Width Register
REG[20h]
Read/Write
FPLINE Pulse
Polarity
7
FPLINE Pulse Width Bits 6-0
6
5
4
3
2
1
0
bit 7
FPLINE Pulse Polarity
This bit selects the polarity of the horizontal sync signal. For passive panels, this bit must
be set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the
panel (typically FPLINE or LP).
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
bits 6-0
FPLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The
horizontal sync signal is typically FPLINE or LP, depending on the panel type.
FPLINE Pulse Width in number of pixels = (REG[20h] bits 6:0) + 1
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface” on page 56.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 107
FPLINE Pulse Start Position Register 0
REG[22h]
Read/Write
FPLINE Pulse Start Position Bits 7-0
7
6
5
4
3
2
1
FPLINE Pulse Start Position Register 1
REG[23h]
Read/Write
FPLINE Pulse Start Position
Bits 9-8
n/a
7
6
bits 9-0
5
0
4
3
2
1
0
FPLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
FPLINE Pulse Start Position in pixels = (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
Note
For passive panels, these bits must be programmed such that the following formula is
valid.
HPW + HPS < HT
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface” on page 56.
FPFRAME Pulse Width Register
REG[24h]
Read/Write
FPFRAME
Pulse Polarity
7
n/a
6
5
FPFRAME Pulse Width Bits 2-0
4
3
2
1
0
bit 7
FPFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. For passive panels, this bit must be
set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the panel
(typically FPFRAME, SPS or DY).
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
bits 2-0
FPFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The vertical sync signal is typically FPFRAME, SPS or DY, depending on the panel type.
FPFRAME Pulse Width in number of lines = (REG[24h] bits 2:0) + 1
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface” on page 56.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 108
Epson Research and Development
Vancouver Design Center
FPFRAME Pulse Start Position Register 0
REG[26h]
Read/Write
FPFRAME Pulse Start Position Bits 7-0
7
6
5
4
3
2
1
FPFRAME Pulse Start Position Register 1
REG[27h]
Read/Write
FPFRAME Pulse Start
Position Bits 9-8
n/a
7
6
bits 9-0
5
0
4
3
2
1
0
FPFRAME Pulse Start Position Bits [9:0]
These bits specify the start position of the vertical sync signal, in 1 line resolution.
For passive panels, these bits must be set to 00h.
For TFT/HR-TFT/D-TFD panels, VDPS is calculated using the following formula:
VPS = (REG[27h] bits 1-0, REG[26h] bits 7-0)
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface” on page 56.
D-TFD GCP Index Register
REG[28h]
Read/Write
n/a
7
D-TFD GCP Index Bits 4-0
6
bits 4-0
5
4
3
2
1
0
D-TFD GCP Index Bits [4:0]
For D-TFD panels only. These bits form the index that points to 32 8-bit GCP data registers.
D-TFD GCP Data Register
REG[2Ch]
Read/Write
D-TFD GCP Data Bits 7-0
7
bits 7-0
6
5
4
3
2
1
0
D-TFD GCP Data Bits [7:0]
For D-TFD panel only. This register stores the data to be written to the GCP data bits and
is controlled by the D-TFD GCP Index register (REG[28h]). For further information on
the use of this register, see Connecting to the Epson D-TFD Panels, document number
X31B-G-012-xx.
Note
The Panel Type bits (REG[10h] bits 1:0) must be set to 11 (D-TFD) for the GCP Data
bits to have any hardware effect.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 109
8.3.5 Display Mode Registers
Display Mode Register
REG[70h]
Read/Write
Display Blank
Dithering
Disable
Hardware
Video Invert
Enable
Software
Video Invert
n/a
7
6
5
4
3
Bit-per-pixel Select Bits 2-0
2
1
0
bit 7
Display Blank
When this bit = 0, the LCD display pipeline is enabled.
When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are
forced to zero (i.e., the screen is blanked).
bit 6
Dithering Disable
Dithering allows 64 intensity levels for each color component (RGB). In monochrome
modes where only the Green color component of the Look-Up-Table is used, 64 shades of
gray are available for each position used in the LUT. In color modes, 64 shades of color
are available for each color component resulting in 256K possible color combinations.
When this bit = 0, dithering is enabled for passive LCD panels.
When this bit = 1, dithering is disabled for passive LCD panels.
Note
This bit does not refer to the number of simultaneously displayed colors but rather the
maximum available colors (refer to Table 8-9: “LCD Bit-per-pixel Selection,” on page
111 for the maximum number of simultaneously displayed colors).
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 110
bit 5
Epson Research and Development
Vancouver Design Center
Hardware Video Invert Enable
This bit allows the Video Invert feature to be controlled using the General Purpose IO pin
GPIO0. This option is not available if configured for a HR-TFT or D-TFD as GPIO0
is used as an LCD control signal by both panels.
When this bit = 0, GPIO0 has no effect on the video data.
When this bit = 1, video data may be inverted via GPIO0.
Note
The S1D13706 requires some configuration before the hardware video invert feature
can be enabled.
• CNF3 must be set to 1 at RESET#
• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1
• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0
If Hardware Video Invert is not available (i.e. HR-TFT panel is used), the video invert
function can be controlled by software using REG[70h] bit 4. The following table summarizes the video invert options available.
Table 8-8: Inverse Video Mode Select Options
Hardware Video
Invert Enable
Software Video
Invert
GPIO0
Video Data
0
0
X
Normal
0
1
X
Inverse
1
X
0
Normal
1
X
1
Inverse
Note
Video data is inverted after the Look-Up Table.
bit 4
Software Video Invert
When this bit = 0, video data is normal.
When this bit = 1, video data is inverted.
See Table 8-8: “Inverse Video Mode Select Options”.
Note
Video data is inverted after the Look-Up Table
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
bits 2-0
Page 111
Bit-per-pixel Select Bits [2:0]
These bits select the color depth (bit-per-pixel) for the displayed data for both the main
window and the PIP+ window (if active).
Note
1, 2, 4 and 8 bpp color depths use the 18-bit LUT, allowing a maximum number of 256K
available colors on TFT panels. 16 bpp mode bypasses the LUT, allowing a maximum
of only 64K available colors.
Table 8-9: LCD Bit-per-pixel Selection
Bit-per-pixel
Color Depth (bpp)
Select Bits [2:0]
Maximum Number of Available
Colors/Shades
Passive Panel
(Dithering On)
TFT Panel
Max. No. Of
Simultaneously
Displayed
Colors/Shades
000
1 bpp
64K/64
256K/64
2/2
001
2 bpp
64K/64
256K/64
4/4
010
4 bpp
64K/64
256K/64
16/16
011
8 bpp
64K/64
256K/64
256/64
100
16 bpp
64K/64
64K/64
64K/64
101, 110, 111
Reserved
Special Effects Register
REG[71h]
Read/Write
+
Display Data
Word Swap
Display Data
Byte Swap
n/a
PIP Window
Enable
7
6
5
4
bit 7
SwivelView Mode Select
Bits 1-0
n/a
3
2
1
0
Display Data Word Swap
The display pipe fetches 32-bits of data from the display buffer. This bit enables the lower
16-bit word and the upper 16-bit word to be swapped before sending them to the LCD display. If the Display Data Byte Swap bit is also enabled, then the byte order of the fetched
32-bit data is reversed.
Note
For further information on byte swapping for Big Endian mode, see Section 14, “BigEndian Bus Interface” on page 146.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 112
bit 6
Epson Research and Development
Vancouver Design Center
Display Data Byte Swap
The display pipe fetches 32-bits of data from the display buffer. This bit enables byte 0
and byte 1 to be swapped, and byte 2 and byte 3 to be swapped, before sending them to the
LCD display. If the Display Data Word Swap bit is also enabled, then the byte order of the
fetched 32-bit data is reversed.
byte 0
byte 1
32-bit display data
from display buffer
Data
To LUT
Serialization
byte 2
byte 3
Byte Swap
Word Swap
Figure 8-1: Display Data Byte/Word Swap
Note
For further information on byte swapping for Big Endian mode, see Section 14, “BigEndian Bus Interface” on page 146.
bit 4
Picture-in-Picture Plus (PIP+) Window Enable
This bit enables the PIP+ window within the main window used for the Picture-in-Picture
Plus feature. The location of the PIP+ window within the landscape window is determined
by the PIP+ Window X Position registers (REG[84h], REG[85h], REG[8Ch], REG[8Dh])
and PIP+ Window Y Position registers (REG[88h], REG[89h], REG[90h], REG[91h]).
The PIP+ window has its own Display Start Address register (REG[7Ch], REG[7Dh],
REG[7Eh]) and Memory Address Offset register (REG[80h], REG[81h]). The PIP+ window shares the same color depth and SwivelViewTM orientation as the main window.
bit 1-0
SwivelView Mode Select Bits [1:0]
These bits select different SwivelViewTM orientations:
Table 8-10: SwivelViewTM Mode Select Options
S1D13706
X31B-A-001-09
SwivelView Mode Select Bits
SwivelView Orientation
00
0° (Normal)
01
90°
10
180°
11
270°
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 113
Main Window Display Start Address Register 0
REG[74h]
Read/Write
Main window Display Start Address Bits 7-0
7
6
5
4
3
2
1
Main Window Display Start Address Register 1
REG[75h]
0
Read/Write
Main window Display Start Address Bits 15-8
7
6
5
4
3
2
1
Main Window Display Start Address Register 2
REG[76h]
Read/Write
Main window
Display Start
Address
Bit 16
n/a
7
bits 16-0
6
5
4
0
3
2
1
0
Main Window Display Start Address Bits [16:0]
This register specifies the starting address, in DWORDS, for the LCD image in the display
buffer for the main window.
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the second double-word of the display memory, and so on. Calculate the Display Start Address as
follows:
Main Window Display Start Address bits 16:0
= image address ÷ 4 (valid only for SwivelView 0°)
Note
For information on setting this register for other SwivelView orientations, see Section
12, “SwivelView™” on page 138.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 114
Epson Research and Development
Vancouver Design Center
Main Window Line Address Offset Register 0
REG[78h]
Read/Write
Main window Line Address Offset Bits 7-0
7
6
5
4
3
2
1
Main Window Line Address Offset Register 1
REG[79h]
Read/Write
Main window Line Address
Offset Bits 9-8
n/a
7
bits 9-0
6
5
0
4
3
2
1
0
Main Window Line Address Offset Bits [9:0]
This register specifies the offset, in DWORDS, from the beginning of one display line to
the beginning of the next display line in the main window. Note that this is a 32-bit
address increment. Calculate the Line Address Offset as follows:
Main Window Line Address Offset bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
Note
A virtual display can be created by programming this register with a value greater than
the formula requires. When a virtual display is created the image width is larger than the
display width and the displayed image becomes a window into the larger virtual image.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 115
8.3.6 Picture-in-Picture Plus (PIP+) Registers
PIP+ Window Display Start Address Register 0
REG[7C]
Read/Write
PIP+ Window Display Start Address Bits 7-0
7
6
5
4
3
2
1
PIP+ Window Display Start Address Register 1
REG[7Dh]
0
Read/Write
PIP+ Window Display Start Address Bits 15-8
7
6
5
4
3
2
1
PIP+ Window Display Start Address Register 2
REG[7Eh]
Read/Write
PIP+ Window
Display Start
Address
Bit 16
n/a
7
6
5
4
0
3
2
1
0
PIP+ Window Display Start Address Bits [16:0]
These bits form the 17-bit address for the starting double-word of the PIP+ window.
bits 16-0
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the second double-word of the display memory, and so on.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[71h] bit
4).
PIP+ Window Line Address Offset Register 0
REG[80h]
Read/Write
PIP+ Window Line Address Offset Bits 7-0
7
6
5
4
3
2
1
PIP+ Window Line Address Offset Register 1
REG[81h]
0
Read/Write
+
PIP Window Line Address
Offset Bits 9-8
n/a
7
bits 9-0
6
5
4
3
2
1
0
PIP+ Window Line Address Offset Bits [9:0]
These bits are the LCD display’s 10-bit address offset from the starting double-word of
line “n” to the starting double-word of line “n + 1” for the PIP+ window. Note that this is
a 32-bit address increment.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[71h] bit
4).
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 116
Epson Research and Development
Vancouver Design Center
PIP+ Window X Start Position Register 0
REG[84h]
Read/Write
PIP+ Window X Start Position Bits 7-0
7
6
5
4
3
2
1
PIP+ Window X Start Position Register 1
REG[85h]
0
Read/Write
+
PIP Window X Start Position
Bits 9-8
n/a
7
bits 9-0
6
5
4
3
2
1
0
+
PIP Window X Start Position Bits [9:0]
These bits determine the X start position of the PIP+ window in relation to the origin of the
panel. Due to the S1D13706 SwivelView feature, the X start position may not be a
horizontal position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the X Start Position register, see Section 13, “Picture-in-Picture
Plus (PIP+)” on page 143.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the X start position is incremented by x pixels where x is relative to
the current color depth.
Table 8-11: 32-bit Address Increments for Color Depth
Color Depth
Pixel Increment (x)
1 bpp
32
2 bpp
16
4 bpp
8
8 bpp
4
16 bpp
2
For 90° and 270° SwivelView the X start position is incremented in 1 line increments.
Depending on the color depth, some of the higher bits in this register are unused because
the maximum horizontal display width is 1024 pixels.
Note
1
These bits have no effect unless the PIP+ Window Enable bit is set to 1
(REG[71h] bit 4).
2 The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written
and at the next vertical non-display period.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 117
PIP+ Window Y Start Position Register 0
REG[88h]
Read/Write
PIP+ Window Y Start Position Bits 7-0
7
6
5
4
3
2
1
PIP+ Window Y Start Position Register 1
REG[89h]
0
Read/Write
+
PIP Window Y Start Position
Bits 9-8
n/a
7
bits 9-0
6
5
4
3
2
1
0
+
PIP Window Y Start Position Bits [9:0]
These bits determine the Y start position of the PIP+ window in relation to the origin of the
panel. Due to the S1D13706 SwivelView feature, the Y start position may not be a vertical
position value (only true in 0° and 180° SwivelView). For further information on defining
the value of the Y Start Position register, see Section 13, “Picture-in-Picture Plus (PIP+)”
on page 143.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the Y start position is incremented in 1 line increments. For 90° and
270° SwivelView the Y start position is incremented by y pixels where y is relative to the
current color depth.
Table 8-12: 32-bit Address Increments for Color Depth
Color Depth
Pixel Increment (y)
1 bpp
32
2 bpp
16
4 bpp
8
8 bpp
4
16 bpp
2
Depending on the color depth, some of the higher bits in this register are unused because
the maximum vertical display height is 1024 pixels.
Note
1
These bits have no effect unless the PIP+ Window Enable bit is set to 1
(REG[71h] bit 4).
2
The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written
and at the next vertical non-display period.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 118
Epson Research and Development
Vancouver Design Center
PIP+ Window X End Position Register 0
REG[8Ch]
Read/Write
PIP+ Window X End Position Bits 7-0
7
6
5
4
3
2
1
PIP+ Window X End Position Register 1
REG[8Dh]
0
Read/Write
+
PIP Window X End Position
Bits 9-8
n/a
7
bits 9-0
6
5
4
3
2
1
0
+
PIP Window X End Position Bits [9:0]
These bits determine the X end position of the PIP+ window in relation to the origin of the
panel. Due to the S1D13706 SwivelView feature, the X end position may not be a
horizontal position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the X End Position register, see Section 13, “Picture-in-Picture
Plus (PIP+)” on page 143.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the X end position is incremented by x pixels where x is relative to
the current color depth.
Table 8-13: 32-bit Address Increments for Color Depth
Color Depth
Pixel Increment (x)
1 bpp
32
2 bpp
16
4 bpp
8
8 bpp
4
16 bpp
2
For 90° and 270° SwivelView the X end position is incremented in 1 line increments.
Depending on the color depth, some of the higher bits in this register are unused because
the maximum horizontal display width is 1024 pixels.
Note
1
These bits have no effect unless the PIP+ Window Enable bit is set to 1
(REG[71h] bit 4).
2 The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written
and at the next vertical non-display period.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 119
PIP+ Window Y End Position Register 0
REG[90h]
Read/Write
PIP+ Window Y End Position Bits 7-0
7
6
5
4
3
2
1
PIP+ Window Y End Position Register 1
REG[91h]
0
Read/Write
+
PIP Window Y End Position
Bits 9-8
n/a
7
bits 9-0
6
5
4
3
2
1
0
+
PIP Window Y End Position Bits [9:0]
These bits determine the Y end position of the PIP+ window in relation to the origin of the
panel. Due to the S1D13706 SwivelView feature, the Y end position may not be a vertical
position value (only true in 0° and 180° SwivelView). For further information on defining
the value of the Y End Position register, see Section 13, “Picture-in-Picture Plus (PIP+)”
on page 143.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the Y end position is incremented in 1 line increments. For 90° and
270° SwivelView the Y end position is incremented by y pixels where y is relative to the
current color depth.
Table 8-14: 32-bit Address Increments for Color Depth
Color Depth
Pixel Increment (y)
1 bpp
32
2 bpp
16
4 bpp
8
8 bpp
4
16 bpp
2
Depending on the color depth, some of the higher bits in this register are unused because
the maximum vertical display height is 1024 pixels.
Note
1
These bits have no effect unless the PIP+ Window Enable bit is set to 1
(REG[71h] bit 4).
2
The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written
and at the next vertical non-display period.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 120
Epson Research and Development
Vancouver Design Center
8.3.7 Miscellaneous Registers
Power Save Configuration Register
REG[A0h]
Vertical NonDisplay
Period Status
(RO)
7
Read/Write
Memory
Controller
Power Save
Status (RO)
n/a
6
5
4
3
Power Save
Mode Enable
n/a
2
1
0
bit 7
Vertical Non-Display Period Status
This is a read-only status bit.
When this bit = 0, the LCD panel output is in a Vertical Display Period.
When this bit = 1, the LCD panel output is in a Vertical Non-Display Period.
bit 3
Memory Controller Power Save Status
This read-only status bit indicates the power save state of the memory controller.
When this bit = 0, the memory controller is powered up.
When this bit = 1, the memory controller is powered down and the MCLK source can be
turned off.
Note
Memory writes are possible during power save mode because the S1D13706 dynamically enables the memory controller for display buffer writes.
bit 0
Power Save Mode Enable
When this bit = 1, the software initiated power save mode is enabled.
When this bit = 0, the software initiated power save mode is disabled.
At reset, this bit is set to 1. For a summary of Power Save Mode, see Section 15, “Power
Save Mode” on page 149.
Note
Memory writes are possible during power save mode because the S1D13706 dynamically enables the memory controller for display buffer writes.
Reserved
REG[A1h]
Read/Write
n/a
7
bit 0
S1D13706
X31B-A-001-09
6
5
4
Reserved
3
2
1
0
Reserved.
This bit must remain at 0.
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 121
Reserved
REG[A2h]
Read/Write
Reserved
7
n/a
6
5
4
bit 7
Reserved.
This bit must remain at 0.
bit 0
Reserved.
This bit must remain at 0.
Reserved
3
2
1
Reserved
REG[A3h]
Read/Write
Reserved
7
0
n/a
6
bit 7
5
4
3
2
1
0
Reserved.
This bit must remain at 0.
Scratch Pad Register 0
REG[A4h]
Read/Write
Scratch Pad Bits 7-0
7
6
5
4
3
2
1
Scratch Pad Register 1
REG[A5h]
0
Read/Write
Scratch Pad Bits 15-8
7
bits 15-0
6
5
4
3
2
1
0
Scratch Pad Bits [15:0]
This register contains general purpose read/write bits. These bits have no effect on
hardware.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 122
Epson Research and Development
Vancouver Design Center
8.3.8 General IO Pins Registers
General Purpose IO Pins Configuration Register 0
REG[A8h]
n/a
7
Read/Write
GPIO6 Pin IO GPIO5 Pin IO GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIO0 Pin IO
Configuration Configuration Configuration Configuration Configuration Configuration Configuration
6
5
4
3
2
1
0
Note
1
If CNF3 = 0 at RESET#, then all GPIO pins are configured as outputs only and this
register has no effect. This case allows the GPIO pins to be used by the HR-TFT/D-TFD
panel interfaces. For a summary of GPIO usage for HR-TFT/D-TFD, see Table 4-9:
“LCD Interface Pin Mapping,” on page 30.
2 The input functions of the GPIO pins are not enabled until REG[A9h] bit 7 is set to 1.
bit 6
GPIO6 Pin IO Configuration
When this bit = 0 (default), GPIO6 is configured as an input pin.
When this bit = 1, GPIO6 is configured as an output pin.
bit 5
GPIO5 Pin IO Configuration
When this bit = 0 (default), GPIO5 is configured as an input pin.
When this bit = 1, GPIO5 is configured as an output pin.
bit 4
GPIO4 Pin IO Configuration
When this bit = 0 (default), GPIO4 is configured as an input pin.
When this bit = 1, GPIO4 is configured as an output pin.
bit 3
GPIO3 Pin IO Configuration
When this bit = 0 (default), GPIO3 is configured as an input pin.
When this bit = 1, GPIO3 is configured as an output pin.
bit 2
GPIO2 Pin IO Configuration
When this bit = 0 (default), GPIO2 is configured as an input pin.
When this bit = 1, GPIO2 is configured as an output pin.
bit 1
GPIO1 Pin IO Configuration
When this bit = 0 (default), GPIO1 is configured as an input pin.
When this bit = 1, GPIO1 is configured as an output pin.
bit 0
GPIO0 Pin IO Configuration
When this bit = 0 (default), GPIO0 is configured as an input pin.
When this bit = 1, GPIO0 is configured as an output pin.
General Purpose IO Pins Configuration Register 1
REG[A9h]
GPIO Pin
Input Enable
7
bit 7
S1D13706
X31B-A-001-09
Read/Write
n/a
6
5
4
3
2
1
0
GPIO Pin Input Enable
This bit is used to enable the input function of the GPIO pins. It must be changed to a 1
after power-on reset to enable the input function of the GPIO pins (default is 0).
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 123
General Purpose IO Pins Status/Control Register 0
REG[ACh]
n/a
GPIO6 Pin IO
Status
GPIO5 Pin IO
Status
7
6
5
Read/Write
GPIO4 Pin IO GPIO3 Pin IO
Status
Status
4
3
GPIO2 Pin IO
Status
2
GPIO1 Pin IO GPIO0 Pin IO
Status
Status
1
0
Note
For information on GPIO pin mapping when HR-TFT/D-TFD panels are selected, see
Table 4-9: “LCD Interface Pin Mapping,” on page 30.
bit 6
GPIO6 Pin IO Status
When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO6 is configured as an
output, writing a 1 to this bit drives GPIO6 high and writing a 0 to this bit drives GPIO6
low.
When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO6 is configured as an
input, a read from this bit returns the status of GPIO6.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO6 outputs the YSCLD
signal automatically and writing to this bit has no effect.
bit 5
GPIO5 Pin IO Status
When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO5 is configured as an
output, writing a 1 to this bit drives GPIO5 high and writing a 0 to this bit drives GPIO5
low.
When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO5 is configured as an
input, a read from this bit returns the status of GPIO5.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11) and a 1 is written to this bit, the
D-TFD signal DD_P1 signal is enabled.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11) and a 0 is written to this bit, the
D-TFD signal DD_P1 signal is forced low.
bit 4
GPIO4 Pin IO Status
When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO4 is configured as an
output, writing a 1 to this bit drives GPIO4 high and writing a 0 to this bit drives GPIO4
low.
When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO4 is configured as an
input, a read from this bit returns the status of GPIO4.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO4 outputs the RES signal
automatically and writing to this bit has no effect.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 124
bit 3
Epson Research and Development
Vancouver Design Center
GPIO3 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is
configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit
drives GPIO3 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is
configured as an input, a read from this bit returns the status of GPIO3.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO3 outputs the FRS signal
automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO3 outputs the SPL signal automatically and writing to this bit has no effect.
bit 2
GPIO2 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO2 is
configured as an output, writing a 1 to this bit drives GPIO2 high and writing a 0 to this bit
drives GPIO2 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO2 is
configured as an input, a read from this bit returns the status of GPIO2.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO2 outputs the FR signal
automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO2 outputs the REV signal automatically and writing to this bit has no effect.
bit 1
GPIO1 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO1 is
configured as an output, writing a 1 to this bit drives GPIO1 high and writing a 0 to this bit
drives GPIO1 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO1 is
configured as an input, a read from this bit returns the status of GPIO1.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO1 outputs the YSCL signal automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO1 outputs the CLS signal automatically and writing to this bit has no effect.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
bit 0
Page 125
GPIO0 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is
configured as an output, writing a 1 to this bit drives GPIO0 high and writing a 0 to this bit
drives GPIO0 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is
configured as an input, a read from this bit returns the status of GPIO0.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO0 outputs the XINH signal automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO0 outputs the PS signal
automatically and writing to this bit has no effect.
General Purpose IO Pins Status/Control Register 1
REG[ADh]
GPO Control
7
bit 7
Read/Write
n/a
6
5
4
3
2
1
0
GPO Control
This bit controls the General Purpose Output pin.
Writing a 0 to this bit drives GPO to low.
Writing a 1 to this bit drives GPO to high.
Note
Many implementations use the GPO pin to control the LCD bias power (see Section 6.3,
“LCD Power Sequencing” on page 54).
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 126
Epson Research and Development
Vancouver Design Center
8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse
Configuration Registers
PWM Clock Enable
Divided
Clock
PWM Clock
Divider
PWMCLK
Clock Source / 2
PWM Duty Cycle
Modulation
m
to PWMOUT
Duty = n / 256
frequency =
Clock Source / (2m X 256)
n = PWM Clock Duty Cycle
m = PWM Clock Divide Select value
PWM Clock Force High
CV Pulse Enable
Divided
Clock
CV Pulse
Divider
Clock Source / 2 x
CV Pulse Burst
Generation
to CVOUT
y-pulse burst
frequency =
Clock Source / (2x X 2)
y = Burst Length value
x = CV Pulse Divide Select value
CV Pulse Force High
Figure 8-2: PWM Clock/CV Pulse Block Diagram
Note
For further information on PWMCLK, see Section 7.1.4, “PWMCLK” on page 92.
PWM Clock / CV Pulse Control Register
REG[B0h]
PWM Clock
Force High
n/a
7
6
bit 7 and bit 4
5
Read/Write
PWM Clock
Enable
CV Pulse
Force High
CV Pulse
Burst Status
(RO)
CV Pulse
Burst Start
CV Pulse
Enable
4
3
2
1
0
PWM Clock Force High (bit 7) and PWM Clock Enable (bit 4)
These bits control the PWMOUT pin and PWM Clock circuitry as follows.
Table 8-15: PWM Clock Control
Bit 7
Bit 4
Result
0
1
PWM Clock circuitry enabled
(controlled by REG[B1h] and REG[B3h])
0
0
PWMOUT forced low
1
x
PWMOUT forced high
x = don’t care
When PWMOUT is forced low or forced high it can be used as a general purpose output.
Note
The PWM Clock circuitry is disabled when Power Save Mode is enabled.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
bit 3 and bit 0
Page 127
CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0)
These bits control the CVOUT pin and CV Pulse circuitry as follows.
Table 8-16: CV Pulse Control
Bit 3
Bit 0
Result
0
1
CV Pulse circuitry enabled
(controlled by REG[B1h] and REG[B2h])
0
0
CVOUT forced low
1
x
CVOUT forced high
x = don’t care
When CVOUT is forced low or forced high it can be used as a general purpose output.
Note
1
Bit 3 must be set to 0 and bit 0 must be set to 1 before initiating a new burst using the
CV Pulse Burst Start bit.
2
The CV Pulse circuitry is disabled when Power Save Mode is enabled.
bit 2
CV Pulse Burst Status
This is a read-only bit. A “1” indicates a CV pulse burst is occurring. A “0” indicates no
CV pulse burst is occurring. Software should wait for this bit to clear before starting
another burst.
bit 1
CV Pulse Burst Start
A 1 in this bit initiates a single CVOUT pulse burst. The number of clock pulses generated
is programmable from 1 to 256. The frequency of the pulses is the divided CV Pulse
source divided by 2, with 50/50 duty cycle. This bit should be cleared to 0 by software
before initiating a new burst.
Note
This bit has effect only if the CV Pulse Enable bit is 1.
bit 0
CV Pulse Enable
See description for bit 3.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 128
Epson Research and Development
Vancouver Design Center
PWM Clock / CV Pulse Configuration Register
REG[B1h]
PWM Clock Divide Select Bits 3-0
7
bits 7-4
6
5
Read/Write
CV Pulse Divide Select Bits 2-0
4
3
2
PWMCLK
Source Select
1
0
PWM Clock Divide Select Bits [3:0]
The value of these bits represents the power of 2 by which the selected PWM clock source
is divided.
Table 8-17: PWM Clock Divide Select Options
PWM Clock Divide Select Bits [3:0]
PWM Clock Divide Amount
0h
1
1h
2
2h
4
3h
8
...
...
Ch
4096
Dh-Fh
Reserved
Note
This divided clock is further divided by 256 before it is output at PWMOUT.
bits 3-1
CV Pulse Divide Select Bits [2:0]
The value of these bits represents the power of 2 by which the selected CV Pulse source is
divided.
Table 8-18: CV Pulse Divide Select Options
CV Pulse Divide Select Bits [2:0]
CV Pulse Divide Amount
0h
1
1h
2
2h
4
3h
8
...
...
7h
128
Note
This divided clock is further divided by 2 before it is output at the CVOUT.
bit 0
PWMCLK Source Select
When this bit = 0, the clock source for PWMCLK is CLKI.
When this bit = 1, the clock source for PWMCLK is CLKI2.
Note
For further information on the PWMCLK source select, see Section 7.2, “Clock Selection” on page 93.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 129
CV Pulse Burst Length Register
REG[B2h]
Read/Write
CV Pulse Burst Length Bits 7-0
7
6
bits 7-0
5
4
3
2
1
0
CV Pulse Burst Length Bits [7:0]
The value of this register determines the number of pulses generated in a single CV Pulse
burst:
Number of pulses in a burst = (ContentsOfThisRegister) + 1
PWMOUT Duty Cycle Register
REG[B3h]
Read/Write
PWMOUT Duty Cycle Bits 7-0
7
bits 7-0
6
5
4
3
2
1
0
PWMOUT Duty Cycle Bits [7:0]
This register determines the duty cycle of the PWMOUT output.
Table 8-19: PWMOUT Duty Cycle Select Options
PWMOUT Duty Cycle [7:0]
PWMOUT Duty Cycle
00h
Always Low
01h
High for 1 out of 256 clock periods
02h
High for 2 out of 256 clock periods
...
...
FFh
High for 255 out of 256 clock periods
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 130
Epson Research and Development
Vancouver Design Center
9 Frame Rate Calculation
The following formula is used to calculate the display frame rate.
f PCLK
FrameRate = -------------------------------( HT ) × ( VT )
Where:
S1D13706
X31B-A-001-09
fPCLK
= PClk frequency (Hz)
HT
= Horizontal Total
= ((REG[12h] bits 6-0) + 1) x 8 Pixels
VT
= Vertical Total
= ((REG[19h] bits 1-0, REG[18h] bits 7-0) + 1) Lines
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 131
10 Display Data Formats
The following diagrams show the display mode data formats for a little-endian system.
1 bpp:
bit 7
bit 0
Byte 0
A0
A1
A2
A3
A4
A5
A6
Byte 1
A8
A9
A10 A11 A12 A13 A14 A15
Byte 2
A16 A17 A18 A19 A20 A21 A22 A23
P0 P1 P2 P3 P4 P5 P6 P7
A7
LUT
Pn = RGB value from LUT
Index (An)
Host Address
Panel Display
Display Memory
2 bpp:
bit 7
bit 0
Byte 0
A0
B0
A1
B1
A2
B2
A3
B3
Byte 1
A4
B4
A5
B5
A6
B6
A7
B7
Byte 2
A8
B8
A9
B9
A10 B10 A11 B11
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT
Index (An, Bn)
Host Address
Display Memory
Panel Display
4 bpp:
bit 7
bit 0
Byte 0
A0
B0
C0
D0
A1
B1
C1
D1
Byte 1
A2
B2
C2
D2
A3
B3
C3
D3
Byte 2
A4
B4
C4
D4
A5
B5
C5
D5
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT
Index (An, Bn, Cn, Dn)
Host Address
Display Memory
Panel Display
8 bpp:
bit 7
bit 0
Byte 0
A0
B0
C0
D0
E0
F0
G0
H0
Byte 1
A1
B1
C1
D1
E1
F1
G1
H1
Byte 2
A2
B2
C2
D2
E2
F2
G2
H2
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT Index
(An, Bn, Cn, Dn, En, Fn, Gn, Hn)
Host Address
Panel Display
Display Memory
16 bpp:
Byte 0
5-6-5 RGB
bit 7
bit 0
1
2
0
G0 G0 G0 B04 B03 B02 B01 B00
Byte 1
R04 R03 R02 R01 R00 G05 G04 G03
2
G1 G11
R14 R13
Byte 2
Byte 3
G1
0
B1
4
B1
3
R12 R11 R10
2
B1 B11
G15 G14
B1
P0 P1 P2 P3 P4 P5 P6 P7
Bypasses LUT
Pn = (Rn4-0, Gn 5-0, Bn4-0)
0
G 13
Panel Display
Host Address
Display Buffer
Figure 10-1: 4/8/16 Bit-Per-Pixel Display Data Memory Organization
Note
1. The Host-to-Display mapping shown here is for a little endian system.
2. For 16 bpp format, Rn, Gn, Bn represent the red, green, and blue color components.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 132
Epson Research and Development
Vancouver Design Center
11 Look-Up Table Architecture
The following figures are intended to show the display data output path only.
Note
When Video Data Invert is enabled the video data is inverted after the Look-Up Table.
11.1 Monochrome Modes
The green Look-Up Table (LUT) is used for all monochrome modes.
1 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
00
01
6-bit Gray Data
FC
FD
FE
FF
= unused Look-Up Table entries
1 bit-per-pixel data
from Display Buffer
Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path
2 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
02
03
00
01
10
11
6-bit Gray Data
FC
FD
FE
FF
2 bit-per-pixel data
from Display Buffer
= unused Look-Up Table entries
Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 133
4 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6-bit Gray Data
FC
FD
FE
FF
4 bit-per-pixel data
from Display Buffer
= unused Look-Up Table entries
Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path
8 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
6-bit Gray Data
8 bit-per-pixel data
from Display Buffer
Figure 11-4: 8 Bit-per-pixel Monochrome Mode Data Output Path
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 134
Epson Research and Development
Vancouver Design Center
16 Bit-Per-Pixel Monochrome Mode
The LUT is bypassed and the green data is directly mapped for this color depth– See
“Display Data Formats” on page 131..
11.2 Color Modes
1 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
0
1
6-bit Red Data
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
0
1
6-bit Green Data
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
0
1
6-bit Blue Data
FC
FD
FE
FF
1 bit-per-pixel data
from Image Buffer
= unused Look-Up Table entries
Figure 11-5: 1 Bit-Per-Pixel Color Mode Data Output Path
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 135
2 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
02
03
00
01
10
11
6-bit Red Data
00
01
10
11
6-bit Green Data
00
01
10
11
6-bit Blue Data
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
02
03
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
FC
FD
FE
FF
2 bit-per-pixel data
from Image Buffer
= unused Look-Up Table entries
Figure 11-6: 2 Bit-Per-Pixel Color Mode Data Output Path
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 136
Epson Research and Development
Vancouver Design Center
4 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6-bit Red Data
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6-bit Green Data
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
FC
FD
FE
FF
4 bit-per-pixel data
from Image Buffer
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6-bit Blue Data
= unused Look-Up Table entries
Figure 11-7: 4 Bit-Per-Pixel Color Mode Data Output Path
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 137
8 Bit-per-pixel Color Mode
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
6-bit Red Data
6-bit Green Data
6-bit Blue Data
8 bit-per-pixel data
from Display Buffer
Figure 11-8: 8 Bit-per-pixel Color Mode Data Output Path
16 Bit-Per-Pixel Color Mode
The LUT is bypassed and the color data is directly mapped for this color depth– See
“Display Data Formats” on page 131.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 138
Epson Research and Development
Vancouver Design Center
12 SwivelView™
12.1 Concept
Most computer displays are refreshed in landscape orientation – from left to right and top
to bottom. Computer images are stored in the same manner. SwivelView™ is designed to
rotate the displayed image on an LCD by 90°, 180°, or 270° in an counter-clockwise
direction. The rotation is done in hardware and is transparent to the user for all display
buffer reads and writes. By processing the rotation in hardware, SwivelView™ offers a
performance advantage over software rotation of the displayed image.
The image is not actually rotated in the display buffer since there is no address translation
during CPU read/write. The image is rotated during display refresh.
12.2 90° SwivelView™
90° SwivelView™ requires the Memory Clock (MCLK) to be at least 1.25 times the
frequency of the Pixel Clock (PCLK), i.e. MCLK ≥ 1.25PCLK.
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13706 in the
following sense: A–B–C–D. The display is refreshed by the S1D13706 in the following
sense: B-D-A-C.
physical memory
start address
320
display start address
(panel origin)
C
SwivelView
window
SwivelView
window
B
D
B
A
480
A
D
C
480
320
image seen by programmer
= image in display buffer
image refreshed by S1D13706
Figure 12-1: Relationship Between The Screen Image and the Image Refreshed in 90° SwivelView.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 139
12.2.1 Register Programming
Enable 90° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 01.
Display Start Address
The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start
Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the
address of pixel “B”. To calculate the value of the address of pixel “B” use the following
formula (assumes 8 bpp color depth).
Main Window Display Start Address bits 16:0
= ((image address + (panel height x bpp ÷ 8)) ÷ 4) - 1
= ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ 4) -1
= 79 (4Fh)
Line Address Offset
The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the
display width and programmed using the following formula.
Main Window Line Address Offset bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ 32 ÷ 8 bpp
= 80 (50h)
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 140
Epson Research and Development
Vancouver Design Center
12.3 180° SwivelView™
The following figure shows how the programmer sees a 480x320 landscape image and how
the image is being displayed. The application image is written to the S1D13706 in the
following sense: A–B–C–D. The display is refreshed by the S1D13706 in the following
sense: D-C-B-A.
display start address
(panel origin)
D
D
480
image seen by programmer
= image in display buffer
B
C
320
320
SwivelView
window
A
B
SwivelView
window
A
C
physical memory
start address
480
image refreshed by S1D13706
Figure 12-2: Relationship Between The Screen Image and the Image Refreshed in 180° SwivelView.
12.3.1 Register Programming
Enable 180° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 10.
Display Start Address
The display refresh circuitry starts at pixel “D”, therefore the Main Window Display Start
Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the
address of pixel “D”. To calculate the value of the address of pixel “D” use the following
formula (assumes 8 bpp color depth).
Main Window Display Start Address bits 16:0
= ((image address + (offset x (panel height - 1) + panel width) x bpp ÷ 8) ÷ 4) - 1
= ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp ÷ 8) ÷ 4) - 1
= 38399 (95FFh)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 141
Line Address Offset
The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the
display width and programmed using the following formula.
Main Window Line Address Offset bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
= 480 pixels ÷ 32 ÷ 8 bpp
= 120 (78h)
12.4 270° SwivelView™
270° SwivelView™ requires the Memory Clock (MCLK) to be at least 1.25 times the
frequency of the Pixel Clock (PCLK), i.e. MCLK ≥ 1.25PCLK.
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13706 in the
following sense: A–B–C–D. The display is refreshed by the S1D13706 in the following
sense: C-A-D-B.
physical memory
start address
B
320
display start address
(panel origin)
A
SwivelView
window
SwivelView
window
C
480
A
B
D
D
C
480
320
image seen by programmer
= image in display buffer
image refreshed by S1D13706
Figure 12-3: Relationship Between The Screen Image and the Image Refreshed in 270° SwivelView.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 142
Epson Research and Development
Vancouver Design Center
12.4.1 Register Programming
Enable 270° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 11.
The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start
Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the
address of pixel “C”. To calculate the value of the address of pixel “C” use the following
formula (assumes 8 bpp color depth).
Main Window Display Start Address bits 16:0
= (image address + ((panel width - 1) x offset x bpp ÷ 8) ÷ 4)
= (0 + ((480 pixels - 1) x 320 pixels x 8 bpp ÷ 8) ÷ 4)
= 38320 (95B0h)
Line Address Offset
The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the
display width and programmed using the following formula.
Main Window Line Address Offset bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ 32 ÷ 8 bpp
= 80 (50h)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 143
13 Picture-in-Picture Plus (PIP + )
13.1 Concept
Picture-in-Picture Plus enables a secondary window (or PIP+ window) within the main
display window. The PIP+ window may be positioned anywhere within the virtual display
and is controlled through the PIP+ window control registers (REG[7Ch] through
REG[91h]). The PIP+ window retains the same color depth and SwivelView orientation as
the main window.
The following diagram shows an example of a PIP+ window within a main window and the
registers used to position it.
0° SwivelViewTM
PIP+ window y start position
(REG[89h],REG[88h])
panel’s origin
PIP+ window y end position
(REG[91h],REG[90h])
main-window
PIP+ window
PIP+ window x start position
(REG[85h],REG[84h])
PIP+ window x end position
(REG[8Dh],REG[8Ch])
Figure 13-1: Picture-in-Picture Plus with SwivelView disabled
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 144
Epson Research and Development
Vancouver Design Center
13.2 With SwivelView Enabled
13.2.1 SwivelView 90°
90° SwivelViewTM
panel’s origin
PIP+ window x start position
(REG[85h],REG[84h])
PIP+ window x end position
(REG[8Dh],REG[8Ch])
PIP+ window
main-window
PIP+ window y start position
(REG[89h],REG[88h])
PIP+ window y end position
(REG[91h],REG[90h])
Figure 13-2: Picture-in-Picture Plus with SwivelView 90° enabled
13.2.2 SwivelView 180°
180° SwivelViewTM
PIP+ window x end position
(REG[8Dh],REG[8Ch])
PIP+ window x start position
(REG[85h],REG[84h])
PIP+ window
main-window
PIP+ window y end position
(REG[91h],REG[90h])
PIP+ window y start position
(REG[89h],REG[88h])
panel’s origin
Figure 13-3: Picture-in-Picture Plus with SwivelView 180° enabled
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 145
13.2.3 SwivelView 270°
270° SwivelViewTM
PIP+ window y end position
(REG[91h],REG[90h])
PIP+ window y start position
(REG[89h],REG[88h])
PIP+ window x start position
(REG[85h],REG[84h])
main-window
PIP+ window
PIP+ window x end position
(REG[8Dh],REG[8Ch])
panel’s origin
Figure 13-4: Picture-in-Picture Plus with SwivelView 270° enabled
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 146
Epson Research and Development
Vancouver Design Center
14 Big-Endian Bus Interface
14.1 Byte Swapping Bus Data
The display buffer and register architecture of the S1D13706 is inherently little-endian. If
a host bus interface is configured as big-endian (CNF4 = 1 at reset), bus accesses are
automatically handled by byte swapping all read/write data to/from the internal display
buffer and registers.
Bus data byte swapping translates all byte accesses correctly to the S1D13706 register and
display buffer locations. To maintain the correct translation for 16-bit word access, even
address bytes must be mapped to the MSB of the 16-bit word, and odd address bytes to the
LSB of the 16-bit word. For example:
Byte write 11h to register address 1Eh
Byte write 22h to register address 1Fh
->
->
Word write 1122h to register address 1Eh->
S1D13706
X31B-A-001-09
REG[1Eh] <= 11h
REG[1Fh] <= 22h
REG[1Eh] <= 11h
REG[1Fh] <= 22h
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 147
14.1.1 16 Bpp Color Depth
For 16 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set
to 1.
Display
Buffer
Address
D[15:8]
D[7:0]
15
0
System
Memory
Address
2
0
aa
bb
cc
dd
MSB
15
CPU Data
Byte Swap
bb
aa
dd
cc
0
0
2
Display
Data
Byte Swap
LSB
aabb
System
Memory
(Big-Endian)
ccdd
Display
Buffer
(Little-Endian)
* MSB is assumed to be associated with even address.
* LSB is assumed to be associated with odd address.
Figure 14-1: Byte-swapping for 16 Bpp
For 16 bpp color depth, the MSB of the 16-bit pixel data is stored at the even system
memory address location and the LSB of the 16-bit pixel data is stored at the odd system
memory address location. Bus data byte swapping (automatic when the S1D13706 is
configured for Big-Endian) causes the 16-bit pixel data to be stored byte-swapped in the
S1D13706 display buffer. During display refresh this stored data must be byte-swapped
again before it is sent to the display.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 148
Epson Research and Development
Vancouver Design Center
14.1.2 1/2/4/8 Bpp Color Depth
For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data but not the
display data.
For 1/2/4/8 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be
set to 0.
Display
Buffer
Address
D[15:8]
D[7:0]
15
0
0
11
15
CPU Data
Byte Swap
22
22
11
0
0
System
Memory
Address
11 22
System
Memory
(Big-Endian)
Display
Buffer
(Little-Endian)
* High byte lane (D[15:8]) data (e.g. 11) is associated with even address.
* Low byte lane (D[7:0]) data (e.g. 22) is associated with odd address.
Figure 14-2: Byte-swapping for 1/2/4/8 Bpp
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 149
15 Power Save Mode
A software initiated Power Save Mode is incorporated into the S1D13706 to accommodate
the need for power reduction in the hand-held devices market. This mode is enabled via the
Power Save Mode Enable bit (REG[A0h] bit 0).
Software Power Save Mode saves power by powering down the panel and stopping display
refresh accesses to the display buffer.
Table 15-1: Power Save Mode Function Summary
Software
Power Save
Normal
IO Access Possible?
Yes
Yes
Memory Writes Possible?
Yes1
Yes
Memory Reads Possible?
No
1
Yes
Look-Up Table Registers Access Possible?
Yes
Yes
Sequence Controller Running?
No
Yes
Display Active?
No
Yes
LCD I/F Outputs
Forced Low
Active
PWMCLK
Stopped
Active
GPIO Pins configured for HR-TFT/D-TFD2
Forced Low
Active
GPIO Pins configured as GPIOs Access Possible?2
Yes3
Yes
Note
1
When power save mode is enabled, the memory controller is powered down and the
status of the memory controller is indicated by the Memory Controller Power Save Status bit (REG[A0h] bit 3). However, memory writes are possible during power save
mode because the S1D13706 dynamically enables the memory controller for display
buffer writes.
2
GPIO Pins are configured using the configuration pin CNF3 which is latched on the
rising edge of RESET#. For information on CNF3, see Table 4-7: “Summary of PowerOn/Reset Options,” on page 28.
3
GPIOs can be accessed and if configured as outputs can be changed.
After reset, the S1D13706 is always in Power Save Mode. Software must initialize the chip
(i.e. programs all registers) and then clear the Power Save Mode Enable bit.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 150
Epson Research and Development
Vancouver Design Center
16 Mechanical Data
100-pin TQFP15 surface mount package
16.0 ± 0.4
14.0 ± 0.1
75
51
76
16.0 ± 0.4
14.0 ± 0.1
50
Index
100
26
25
+ 0.05
+ 0.1
0.18 - 0.05
0.125 - 0.025
1.0± 0.1
0.1
1.3 max.
1
0.5
0~10°
0.5 ± 0.2
1
All dimensions in mm
Figure 16-1: Mechanical Data 100pin TQFP15 (S1D13706F00A)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
Epson Research and Development
Vancouver Design Center
Page 151
17 References
The following documents contain additional information related to the S1D13706.
Document numbers are listed in parenthesis after the document name. All documents can
be found at the Epson Research and Development Website at www.erd.epson.com.
• 13706CFG Configuration Utility Users Manual (X31B-B-001-xx)
• 13706SHOW Demonstration Program Users Manual (X31B-B-002-xx)
• 13706PLAY Diagnostic Utility Users Manual (X31B-B-003-xx)
• 13706BMP Demonstration Program Users Manual (X31B-B-004-xx)
• S1D13706 Product Brief (X31B-C-001-xx)
• S1D13706 Windows CE Display Drivers (X31B-E-001-xx)
• Interfacing to the Toshiba TMPR3905/3912 Microprocessor (X31B-G-002-xx)
• S1D13706 Programming Notes And Examples (X31B-G-003-xx)
• S5U13706B00C Rev. 1.0 Evaluation Board User Manual (X31B-G-004-xx)
• Interfacing to the PC Card Bus (X31B-G-005-xx)
• S1D13706 Power Consumption (X31B-G-006-xx)
• Interfacing to the NEC VR4102/VR4111 Microprocessors (X31B-G-007-xx)
• Interfacing to the NEC VR4181 Microprocessor (X31B-G-008-xx)
• Interfacing to the Motorola MPC821 Microprocessor (X31B-G-009-xx)
• Interfacing to the Motorola MCF5307 "Coldfire" Microprocessors (X31B-G-010-xx)
• Connecting to the Sharp HR-TFT Panels (X31B-G-011-xx)
• Connecting to the Epson D-TFD Panels (X31B-G-012-xx)
• Interfacing to the Motorola MC68030 Microprocessor (X31B-G-013-xx)
• Interfacing to the Motorola RedCap2 DSP with Integrated MCU (X31B-G-014-xx)
• Interfacing to 8-Bit Processors (X31B-G-015-xx)
• Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor (X31B-G-016-xx)
• Integrating the CFLGA 104-pin Chip Scale Package (X31B-G-018-xx)
• Interfacing to the Intel StrongARM SA-1110 Microprocessor (X31B-G-019-xx)
• S1D13706 Register Summary (X31B-R-001-xx)
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
Page 152
Epson Research and Development
Vancouver Design Center
18 Sales and Technical Support
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp/
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com/
Taiwan
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: 02-2717-7360
Fax: 02-2712-9164
http://www.epson.com.tw/
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
http://www.epson.com.hk/
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
http://www.epson-electronics.de/
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
http://www.epson.com.sg/
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09